NAND flash memory controller
The reverse-type flash memory controller dynamically adjusts processing power through the host and controller speed estimation and decision modules, solving the energy consumption problem of SSD controllers under low load and achieving high efficiency, energy saving and stable performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2022-06-14
- Publication Date
- 2026-06-23
AI Technical Summary
Existing solid-state drive (SSD) controllers have difficulty effectively entering a low-power state when they do not receive input/output commands, resulting in high energy consumption and frequent frequency adjustments that affect performance.
It adopts an inverse flash memory controller, which includes a host speed estimation module, a controller speed estimation module, a speed decision module, and a speed adjustment module. Based on the access requirements and processing capabilities of the host and controller, it dynamically adjusts the controller's processing capabilities, including frequency and circuit enable/disable, to achieve energy saving and efficient operation.
By dynamically adjusting processing power, the SSD controller achieves high energy efficiency and performance maintenance under different load conditions, avoiding performance loss caused by frequent frequency switching.
Smart Images
Figure CN117270755B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to memory controllers, and more particularly to reverse-type flash memory controllers. Background Technology
[0002] The hardware resources within a typical solid-state drive (SSD) controller can meet the maximum speed of an SSD. More specifically, when all the frequencies within the SSD controller are set to their highest frequencies and all the resources within the SSD controller (such as cache) are enabled, the SSD controller can meet the maximum speed of the SSD. However, at this time, the SSD controller consumes a lot of power and generates a lot of heat.
[0003] To save energy, an existing technology allows the SSD controller to enter a low-power state when it has not received any input / output (I / O) commands from the host for a period of time, thereby reducing / shutting down some of the controller's internal frequencies. However, if this period is too long, the SSD controller typically does not have the opportunity to enter this low-power state, making it difficult to achieve energy savings; if the period is too short, the SSD controller will often frequently repeat frequency reduction and increase operations, which will affect the SSD controller's performance. Summary of the Invention
[0004] One of the objectives of this invention is to provide a reverse-access flash memory controller that can adaptively adjust the processing power of the reverse-access flash memory controller according to the access requirements of the host.
[0005] An embodiment of the reverse-intervention flash memory controller of the present invention includes a host speed estimation module, a controller speed estimation module, a speed decision module, and a speed adjustment module. The host speed estimation module estimates the host speed based on a first total data volume of M first input / output (I / O) commands received by the reverse-intervention flash memory controller within a first time period, wherein the host speed is associated with the host's current access demand, the M first I / O commands originate from the host, and M is a positive integer. The controller speed estimation module estimates the controller speed based on a second total data volume of N second I / O commands processed by the reverse-intervention flash memory controller within a second time period, wherein the controller speed is associated with the current processing capacity of the reverse-intervention flash memory controller, the N second I / O commands originate from the host, and N is a positive integer. The speed decision module generates a decision result based on the relationship between the host speed and the controller speed. The speed adjustment module adjusts or maintains the processing capacity based on the decision result. In short, this embodiment adjusts or maintains the processing capacity of the reverse-intervention flash memory controller based on the relationship between the host speed and the controller speed.
[0006] Another embodiment of the reverse-intervention flash memory controller of the present invention includes a controller speed estimation module, a speed decision module, and a speed adjustment module. The controller speed estimation module estimates the controller speed based on the total data volume of N I / O commands processed by the reverse-intervention flash memory controller over a period of time, wherein the controller speed is related to the current processing capacity of the reverse-intervention flash memory controller, the N I / O commands originate from the host, and N is a positive integer. The speed decision module generates a decision result based on the trend of the controller speed change. The speed adjustment module adjusts or maintains the processing capacity based on the decision result. In short, this embodiment adjusts or maintains the processing capacity of the reverse-intervention flash memory controller based on the trend of the controller speed change.
[0007] Another embodiment of the reverse-intervention flash memory controller of the present invention is used to adjust or maintain the processing power of the reverse-intervention flash memory controller according to the relationship between the host speed and the controller speed or according to the changing trend of the controller speed, wherein the host speed is related to the current access demand of the host and the controller speed is related to the current processing power of the reverse-intervention flash memory controller.
[0008] The features, operation, and effects of the present invention will be described in detail below with reference to the accompanying drawings, specifically the preferred embodiments. Attached Figure Description
[0009] Figure 1 An embodiment of the reverse-type flash memory controller of the present invention is shown; and
[0010] Figure 2 This invention illustrates another embodiment of the reverse-type flash memory controller.
[0011] Symbol explanation:
[0012] 10: Host
[0013] 100: Reverse-type flash memory controller
[0014] 110: Host Speed Estimation Module
[0015] 120: Controller speed estimation module
[0016] 130: Speed Decision Module
[0017] 140: Speed Adjustment Module
[0018] S HOST Host speed
[0019] S CTRL Controller speed
[0020] S CTRL_MAX : Maximum speed limit of the controller
[0021] R SFIN Decision results
[0022] 200: Reverse-type flash memory controller
[0023] 210: Controller speed estimation module
[0024] 220: Speed Decision Module
[0025] 230: Speed Adjustment Module Detailed Implementation
[0026] This specification discloses a reverse-access NAND flash memory controller (e.g., a solid-state drive (SSD) controller; an embedded multimedia card (eMMC) controller; a universal flash storage (UFS) controller; or a secure digital memory card (SD) controller) that can adaptively adjust the processing power of the reverse-access flash memory controller according to the host's access needs, thereby achieving energy saving and other purposes.
[0027] Figure 1 This invention illustrates an embodiment of the reverse-type flash memory controller. Figure 1 The reverse-type flash memory controller 100 (hereinafter referred to as controller 100) includes a host speed estimation module 110, a controller speed estimation module 120, a speed decision module 130, and a speed adjustment module 140. These modules will be described in the following paragraphs.
[0028] Please see Figure 1 The host speed estimation module 110 is used to estimate the host speed S based on the first total data volume of the M first input / output (I / O) commands received by the controller 100 within a first time period. HOST The host speed S HOST The current processing capacity of associated host 10 is given, where the M first I / O commands originate from host 10, and M is a positive integer. For example, if the first time interval is 10 milliseconds (10ms), the M first I / O commands constitute 250 I / O commands, and the data size (or length) of each I / O command is 128 kilobytes (128Kbytes), the total first data size is equal to 250 × 128Kbytes, and the host speed S... HOST equal For example, the first time period is 5ms, the M first I / O commands are 50 I / O commands, and these 50 I / O commands sequentially include 30 I / O commands with a data volume of 128Kbytes and 20 I / O commands with a data volume of 256Kbytes. The first total data volume is equal to 30 × 128Kbytes + 20 × 256Kbytes, and the host speed S HOST equal More examples can be derived from the description above. It is worth noting that the method by which the controller 100 receives I / O commands from the host 10 is a known / self-developed technique, which is outside the scope of this invention. Furthermore, the calculation of the first total data volume described above can be performed by the host speed estimation module 110, or by other known / self-developed calculation circuits (not shown in the figures) according to the description above. Moreover, the host speed estimation module 110 can be implemented in hardware, or by executing firmware through the processor of the controller 100 (not shown in the figures), the contents of which can be based on the host speed S described above. HOST The calculation is derived from the explanation and known firmware writing techniques.
[0029] Please see Figure 1 The controller speed estimation module 120 is used to estimate the controller speed S based on the second total data volume of the N second I / O commands processed by the controller 100 within the second time period. CTRL The controller speed S CTRL The current processing capacity of the associated controller 100 is such that the N second I / O commands originate from the host 10, where N is a positive integer. For example, if the second time period is 10ms, the N second I / O commands constitute 200 I / O commands, and the data size (or length) of each I / O command is 128Kbytes, the total second data size is equal to 200 × 128Kbytes, and the host speed S... HOST equal For example, the second time interval is 20ms, and the N second I / O commands are 300 I / O commands. These 300 I / O commands sequentially include 200 I / O commands with a data size of 128Kbytes and 100 I / O commands with a data size of 256Kbytes. The total second data size is equal to 200 × 128Kbytes + 100 × 256Kbytes. The host speed S HOST equal Further examples can be derived from the description above. It is worth noting that the calculation of the second total data volume described above can be performed by the controller speed estimation module 120, or by other known / self-developed calculation circuits (not shown in the figure) according to the description above. Furthermore, the controller speed estimation module 120 can be implemented in hardware, or by executing firmware through the processor of the controller 100 (not shown in the figure), the contents of which can be based on the controller speed S described above. CTRL The calculation is derived from the explanation and known firmware writing techniques.
[0030] Please see Figure 1 The speed decision module 130 is used to determine the host speed S. HOST With the speed S of the controller CTRL The relationship between the two factors leads to the decision outcome RS. FIN For example, the controller speed S CTRL The maximum speed is S CTRL_MAX The speed decision module 130 compares the host speed S HOST With the speed S of the controller CTRL And compare the speed S of the controller CTRL With this speed limit S CTRL_MAX To produce the decision result RS FIN The decision result RS FIN Indicate one of the following relations: (1) S CTRL HOST And S CTRL CTRL_MAX (2)S CTRL HOST And S CTRL =S CTRL_MAX (3)S CTRL =S HOST ; and (4)S CTRL >S HOST When the decision result RS FIN When the relationship (1) mentioned above is indicated, its display controller speed S CTRL Not keeping up with the host speed S HOST And the controller speed S CTRL It can be adjusted upwards; when the decision result RS FIN When the relationship (2) mentioned above is indicated, the speed S of the display controller is shown. CTRL Not keeping up with the host speed S HOST However, the controller speed S CTRL It cannot be adjusted upwards; when the decision result RS FIN When the relationship (3) mentioned above is indicated, its display controller speed S CTRL Equal to the host speed SHOST When the decision result RS FIN When the relationship (4) mentioned above is indicated, the speed S of the display controller is shown. CTRL Higher than the host speed S HOST And the controller speed S CTRL It can be adjusted downwards. It is worth noting that the speed decision module 130 can further determine the controller speed S. CTRL Has the controller speed S been reached? CTRL Speed limit S CTRL_MIN And based on this, the decision result RS is generated. FIN Additionally, the speed decision module 130 can be implemented in hardware or by executing firmware through the processor of the controller 100 (not shown in the figure), the contents of which can be derived from the description of the comparison above and known firmware writing techniques.
[0031] Please see Figure 1 The speed adjustment module 140 is used to periodically / non-periodically adjust the speed based on the decision result RS. FIN Adjust or maintain this processing capacity. For example, when the decision result RS FIN When the relationship (1) described above is indicated, the speed adjustment module 140 increases the processing capability to increase the controller speed S. CTRL Keep up with the host speed S HOST When the decision result RS FIN When the relationship (2) mentioned above is indicated, the speed adjustment module 140 maintains this processing capability so that the controller 100 operates at full speed; when the decision result RS FIN When the relationship (3) mentioned above is indicated, the speed adjustment module 140 maintains this processing capability; when the decision result RS FIN When the relationship (4) mentioned above is indicated, the speed adjustment module 140 reduces the processing capacity to save power. It is worth noting that when the decision result RS... FIN When indicating the relationship (4) mentioned above, if the decision result RS FIN Indicate the speed S of the controller CTRL Equal to the speed S of the controller CTRL Speed limit S CTRL_MIN The speed adjustment module 140 can maintain this processing capability. Alternatively, the speed adjustment module 140 can be implemented in hardware or by executing firmware through the processor of the controller 100 (not shown in the figure), the contents of which can be derived from the adjustment description above and known firmware writing techniques.
[0032] In summary, the speed adjustment module 140 can adjust the processing capability by at least one of the following methods: adjusting at least one frequency of the controller 100 (e.g., the frequency of the processor of the controller 100 and / or the frequency of the bus of the controller 100); and disabling at least one circuit of the controller 100 (e.g., a portion of the static random access memory (SRAM) of the controller 100), or reducing the power consumption of the at least one circuit. Other known / self-developed methods for adjusting the processing capability may also be used in the speed adjustment module 140.
[0033] Figure 2 This invention illustrates another embodiment of the reverse-type flash memory controller. Figure 2 The reverse-type flash memory controller 200 (hereinafter referred to as controller 200) includes a controller speed estimation module 210, a speed decision module 220, and a speed adjustment module 230. These modules are described in the following paragraphs.
[0034] Please see Figure 2 The controller speed estimation module 210 is used to estimate the controller speed S based on the total data volume of N I / O commands processed by the controller 200 within a certain period of time. CTRL The controller speed S CTRL The current processing capacity of the associated controller 200 is N I / O commands originating from the host 10, where N is a positive integer. The controller speed estimation module 210 is the same as / similar to the controller speed estimation module 120 described above, therefore redundant and repetitive descriptions are omitted here.
[0035] Please see Figure 2 The speed decision module 220 is used to determine the speed S of the controller. CTRL VAR trend SCTRL , generating decision results RS FIN For example, the speed decision module 220 compares the current controller speed S. CTRL_CURR (That is: the controller speed S at the current time point) CTRL ) and the previous controller speed S CTRL_PRE (That is: the controller speed S at the previous time point) CTRL ), to obtain the VAR of this change trend. SCTRL (e.g.: VAR) SCTRL =S CTRL_CURR -S CTRL_ Then, based on this trend, VAR SCTRL The decision result RS was generated FIN The controller speed S CTRL The maximum speed is S CTRL_MAX The decision result RS FIN Identify one of the following relations: (a) VARSCTRL >0 and S CTRL_CURR CTRL_MAX (b) VAR SCTRL >0 and S CTRL_CURR =S CTRL_MAX (c)VAR SCTRL =0; and (d)VAR SCTRL <0. It is worth noting that the speed decision module 220 can further determine the controller speed S. CTRL Has the controller speed S been reached? CTRL Speed limit S CTRL_MIN And based on this, the decision result RS is generated. FIN Additionally, the speed decision module 220 can be implemented in hardware or by executing firmware through the processor of the controller 200 (not shown in the figure), the contents of which can be derived from the decision description above and known firmware writing techniques.
[0036] Please see Figure 2 The speed adjustment module 230 is used to periodically / non-periodically adjust the speed based on the decision result RS. FIN Adjust or maintain the processing capacity. For example, if the speed adjustment module 230 increased the processing capacity during the last adjustment: when the decision result RS... FIN When the relationship (a) described above is indicated, it means that the increase in processing capacity is effective; therefore, the speed adjustment module 230 continues to increase the processing capacity; when the decision result RS FIN When the relationship (b) described above is indicated, it means that the increase in processing capacity is effective, but due to the controller speed S CTRL The speed limit S has been reached. CTRL_MAX The speed adjustment module 230 maintains this processing capacity; when the decision result RS FIN When the relationship (c) described above is indicated, it means that increasing the processing capacity is unnecessary. Therefore, the speed adjustment module 230 maintains or decreases the processing capacity (e.g., restores the processing capacity to its state before the last adjustment); when the decision result RS FIN When the relationship (d) described above is indicated, it means that the adjustment of the processing capacity is contrary to the changing trend of the access demand of host 10; therefore, the speed adjustment module 230 reduces the processing capacity. For example, if the speed adjustment module 230 reduced the processing capacity in the last adjustment: when the decision result RS... FIN When the relationship (a) mentioned above is indicated, it means that the adjustment of the processing capacity is contrary to the changing trend of the access demand of host 10. Therefore, the speed adjustment module 230 increases the processing capacity; when the decision result RS FIN When the relationship (c) mentioned above is indicated, it means that the processing capacity is excessive, and the speed adjustment module 230 continues to reduce the processing capacity; when the decision result RS FIN When the relationship (d) described above is indicated, it means that the processing capacity has been excessively reduced. Therefore, the speed adjustment module 230 maintains or increases the processing capacity (e.g., restores the processing capacity to its state before the last adjustment). The speed adjustment module 230 can be implemented in hardware or by executing firmware through the processor (not shown) of the controller 200, the contents of which can be derived from the adjustment description above and known firmware writing techniques.
[0037] In summary, the speed adjustment module 230 can adjust the processing capability by at least one of the following methods: adjusting at least one frequency of the controller 200 (e.g., the frequency of the processor of the controller 200 and / or the frequency of the bus of the controller 200); and shutting down at least one circuit of the controller 200 (e.g., a portion of the static random access memory of the controller 200), or reducing the power consumption of the at least one circuit. Other known / self-developed methods for adjusting the processing capability may also be used in the speed adjustment module 230.
[0038] Please note that, where feasible, those skilled in the art may selectively implement some or all of the technical features in any of the above embodiments, or selectively implement a combination of some or all of the technical features in the multiple embodiments described above, thereby increasing the flexibility in implementing the present invention.
[0039] In summary, the reverse-access flash memory controller of the present invention can adaptively adjust its processing capability according to the host's access requirements.
[0040] Although preferred and feasible embodiments of the present invention have been disclosed above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention, and all such changes fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope defined in the claims of this application.
Claims
1. A reverse-type flash memory controller, characterized in that, The reverse-type flash memory controller is capable of adaptively adjusting its processing capability, and the reverse-type flash memory controller includes: The host speed estimation module is used to estimate the host speed based on the first total data amount of the M first input / output (I / O) commands received by the reverse-type flash controller within a first time period, wherein the host speed is related to the current access demand of the host, the M first I / O commands are from the host, and M is a positive integer; The controller speed estimation module is used to estimate the controller speed based on the second total data volume of the N second I / O commands processed by the reverse-interactive flash controller within a second time period, wherein the controller speed is related to the current processing capacity of the reverse-interactive flash controller, the N second I / O commands originate from the host, and N is a positive integer; The speed decision module is used to generate a decision result based on the relationship between the host speed and the controller speed; as well as A speed adjustment module is used to adjust or maintain the processing capacity based on the decision result.
2. The reverse-type flash memory controller as described in claim 1, characterized in that, When the relationship indicates that the controller speed is lower than the host speed and lower than the upper limit of the controller speed, the speed decision module generates the decision result to request the speed adjustment module to increase the controller speed.
3. The reverse-type flash memory controller as described in claim 1, characterized in that, When the relationship indicates that the controller speed is lower than the host speed but equal to the upper limit of the controller speed, the speed decision module generates the decision result to require the speed adjustment module to maintain the processing capacity.
4. The reverse-type flash memory controller as described in claim 1, characterized in that, When the relationship indicates that the controller speed is higher than the host speed, the speed decision module generates the decision result to request the speed adjustment module to reduce the controller speed.
5. The reverse-type flash memory controller as described in claim 1, characterized in that, The speed adjustment module adjusts the processing capability by at least one of the following methods: adjusting at least one frequency of the reverse-interactive flash controller; and shutting down at least one circuit of the reverse-interactive flash controller or reducing the power consumption of the at least one circuit.
6. A reverse-intervention flash memory controller, capable of adaptively adjusting the processing capability of the reverse-intervention flash memory controller, the reverse-intervention flash memory controller comprising: The controller speed estimation module is used to estimate the controller speed based on the total data volume of N I / O commands processed by the reverse-interactive flash controller within a certain period of time, wherein the controller speed is related to the current processing capacity of the reverse-interactive flash controller, the N I / O commands originate from the host, and N is a positive integer; The speed decision module is used to generate a decision result based on the changing trend of the controller speed; as well as A speed adjustment module is used to adjust or maintain the processing capacity based on the decision result.
7. The reverse-type flash memory controller as described in claim 6, characterized in that, After the controller speed is increased, when the trend indicates that the controller speed is getting faster and the controller speed is not higher than the upper limit of the controller speed, the speed decision module generates the decision result to request the speed adjustment module to increase the processing capacity again.
8. The reverse-type flash memory controller as described in claim 7, characterized in that, After the processing capacity is increased again, when the trend indicates that the controller speed remains unchanged, the speed decision module generates the decision result to require the speed adjustment module to maintain or reduce the processing capacity.
9. The reverse-type flash memory controller as described in claim 6, characterized in that, After the controller speed is reduced, when the trend indicates that the controller speed remains unchanged, the speed decision module generates the decision result to request the speed adjustment module to reduce the processing capacity again.
10. The reverse-type flash memory controller as described in claim 9, characterized in that, After the processing capacity is reduced again, when the trend indicates that the controller speed is slowing down, the speed decision module generates the decision result to require the speed adjustment module to maintain or increase the controller speed.