Chip design reorganization system based on display interface

Abstract

The present application relates to a chip design reorganization system based on a display interface, which is applied to the reorganization process of chip logic interconnection to physical interconnection, the system constructs chip logic interconnection relationship based on interface description reconfiguration library and logic interconnection database, then further constructs physical interconnection database, displays physical layout diagram on the display interface based on the physical database, the physical layout diagram includes K1 group display areas, K2 atomic unit display areas, K3 buses, each atomic unit display area is located in the corresponding group area, the ith bus is arranged between the atomic unit display area of A ib and the atomic unit display area of B ib . The present application can display based on the display interface and can visually adjust physical reorganization and delay adjustment, improves the efficiency of physical reorganization and delay adjustment, thereby improves the efficiency of chip design.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a chip design reconfiguration system based on a display interface. Background Technology

[0002] In chip design, the logical interconnections between modules must first be established, followed by physical connections based on these logical interconnections, and then physical regrouping. During physical regrouping, different groups need to be defined, and subsequent adjustments are typically required multiple times. Furthermore, due to different physical layout and routing methods, the distances and types of connections between different components may vary. Especially when the distance is too long, directly establishing connections between modules using the logical interconnection method can affect the timing between two interconnected components. Therefore, delay adjustments to the interconnected components are also necessary during the regrouping process.

[0003] However, since existing technologies are based on Register Transfer Level (RTL) chip design, the reassembly process requires writing a large amount of RTL code, which is inefficient and error-prone. Furthermore, using RTL code for delay adjustments results in a complex, inefficient, error-prone, and inflexible process. Moreover, as chip sizes increase, this method is clearly unsuitable for large-scale chip designs, and any changes to delay adjustments require individual modifications to the corresponding RTL sections, leading to low chip design efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a chip design reconfiguration system based on a display interface, which can display and intuitively perform physical reconfiguration and delay adjustments, thereby improving the efficiency of physical reconfiguration and delay adjustment, and thus improving the efficiency of chip design.

[0005] This invention provides a chip design interconnect reconfiguration system based on a display interface, applied to the reconfiguration process of chip logic interconnects to physical interconnects, characterized in that...

[0006] This includes an interface description refactoring library, a logical interconnect database, a physical interconnect database, a display interface, a processor, and a memory storing computer programs. The interface description refactoring library includes K3 predefined interface refactoring structures IDF = (IDF1, IDF2, ..., IDF...). K3 The logical interconnect database includes K1 modules (Mod1, Mod2, ..., Mod...). K1 K2 atomic units (AU1, AU2, ..., AU) K2K4 interconnected design assembly DIY = (X1_Y1_CMD1, X2_Y2_CMD2, ..., X K4 _Y K4 _CMD K4 ), X i5 and Y i5 Belongs to {Mod1,Mod2,...,Mod K1 ,AU1,AU2,...,AU K2 The value of i5 ranges from 1 to K4, and CMD... i5 Used to obtain the corresponding IDF from the interface description refactoring library, Mod i1 Including the module's unique identifier (MID) i and 1Mod i1 The submodule identifier and subatomic unit identifier; the physical interconnect database is initially empty;

[0007] When the processor executes the computer program, it performs the following steps:

[0008] Step S1: Based on (X1_Y1_CMD1, X2_Y2_CMD2, ..., X K4 _Y K4 _CMD K4 (Mod1,Mod2,...,Mod) K1 (AU1,AU2,...,AU) K2 Constructing chip logic interconnections;

[0009] Step S2: Determine the logical interconnection relationship between atomic units (A1_B1_CMD1', A2_B2_CMD2', ..., A) based on the chip logical interconnection relationship. Kb _B Kb _CMD Kb '),A ib B ib Belonging to {AU1,AU2,...,AU} K2},CMD ib 'Used to obtain the corresponding IDF from the interface description refactoring library, the value of ib ranges from 1 to Kb;

[0010] Step S3: Based on the physical layout information, group {AU1, AU2, ..., AU...} K2} Divide into Ka physics groups {AUG1, AUG2, ... AGU} Ka},AUG ia Includes at least one AU i2 Each AU i2 Classified as one of the AUG iaIn this context, the value range of ia is from 1 to Ka, and the value range of i2 is from 1 to K2.

[0011] Step S4: Set {AUG1, AUG2, ... AGU} Ka} and (A1_B1_CMD1',A2_B2_CMD2',...,A Kb _B Kb _CMD Kb Stored in the physical interconnect database;

[0012] Step S5: Display a physical layout diagram on the display interface based on the physical database. The physical layout diagram includes Ka group display areas, K2 atomic unit display areas, and Kb buses. Each atomic unit display area is located in the corresponding group area, and the ib-th bus is set in A. ib The atomic unit display area and B ib Between the atomic unit display areas, the value of ib ranges from 1 to Kb.

[0013] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the chip design reconfiguration system based on a display interface provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It possesses at least the following advantages:

[0014] The system described in this invention can generate physical layout diagrams directly through a display interface based on an interface description reconfiguration library, a logical interconnection database, and a physical interconnection database. This allows for quick and intuitive physical reconfiguration without direct manipulation of RTL code or adjustment of logical interconnection relationships. Furthermore, delay adjustments can be made based on the display interface, improving the efficiency of physical reconfiguration and delay adjustment, thereby enhancing chip design efficiency.

[0015] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a chip design reconfiguration system based on a display interface, provided as an embodiment of the present invention. Detailed Implementation

[0017] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, describes in detail the specific implementation and effects of a chip design reconfiguration system based on a display interface proposed in accordance with the present invention.

[0018] This invention provides a chip design interconnect reconfiguration system based on a display interface, applied to the reconfiguration process of chip logic interconnects to physical interconnects, such as... Figure 1 As shown, it includes an interface description refactoring library, a logical interconnect database, a physical interconnect database, a display interface, a processor, and a memory storing computer programs. The interface description refactoring library includes K3 predefined interface refactoring structures IDF = (IDF1, IDF2, ..., IDF...). K3 Preferably, the interface can be implemented as a bus. The logical interconnect database includes K1 modules (Mod1, Mod2, ..., Mod...). K1 K2 atomic units (AU1, AU2, ..., AU) K2 K4 interconnected design assembly DIY = (X1_Y1_CMD1, X2_Y2_CMD2, ..., X K4 _Y K4 _CMD K4 ), X i5 and Y i5 Belongs to {Mod1,Mod2,...,Mod K1 ,AU1,AU2,...,AU K2 The value of i5 ranges from 1 to K4, and CMD... i5 Used to obtain the corresponding IDF from the interface description refactoring library, Mod i1 Including the module's unique identifier (MID) i and 1Mod i1 The submodule identifier and subatomic unit identifier; the physical interconnect database is initially empty.

[0019] When the processor executes the computer program, it performs the following steps:

[0020] Step S1: Based on (X1_Y1_CMD1, X2_Y2_CMD2, ..., X K4 _Y K4 _CMD K4 (Mod1,Mod2,...,Mod) K1 (AU1,AU2,...,AU) K2 Construct the logical interconnection relationship of the chip.

[0021] Step S2: Determine the logical interconnection relationship between atomic units (A1_B1_CMD1', A2_B2_CMD2', ..., A) based on the chip logical interconnection relationship. Kb _B Kb _CMD Kb '),A ib Bib Belonging to {AU1,AU2,...,AU} K2},CMD ib 'Used to obtain the corresponding IDF from the interface description refactoring library, the value of ib ranges from 1 to Kb.

[0022] Step S3: Based on the physical layout information, group {AU1, AU2, ..., AU...} K2} Divide into Ka physics groups {AUG1, AUG2, ... AGU} Ka},AUG ia Includes at least one AU i2 Each AU i2 Classified as one of the AUG ia In this context, the value range of ia is from 1 to Ka, and the value range of i2 is from 1 to K2.

[0023] Step S4: Set {AUG1, AUG2, ... AGU} Ka} and (A1_B1_CMD1',A2_B2_CMD2',...,A Kb _B Kb _CMD Kb Stored in the physical interconnect database.

[0024] Step S5: Display a physical layout diagram on the display interface based on the physical database. The physical layout diagram includes Ka group display areas, K2 atomic unit display areas, and Kb buses. Each atomic unit display area is located in the corresponding group area, and the ib-th bus is set in A. ib The atomic unit display area and B ib Between the atomic unit display areas, the value of ib ranges from 1 to Kb.

[0025] Preferably, the display interface is a GUI (Graphical User Interface).

[0026] In a preferred embodiment, each bus protocol corresponds to one IDF, that is, one type of bus. When displaying buses in the display area, different colors can be used to display buses of different protocols, and the color displayed for each type of bus can be customized by the user. Furthermore, when the user inputs a target protocol, all buses corresponding to the target protocol on the current interface can be highlighted.

[0027] Steps S1-S5 allow for the intuitive display of the physical layout diagram on the display interface. Based on the displayed physical layout diagram, adjustments to the physical layout can be made directly.

[0028] As one embodiment, step S5 is followed by:

[0029] Step S6: Receive the first physical layout adjustment instruction, and parse the atomic unit identifier to be adjusted, the current group identifier, and the first target group identifier from the first physical layout adjustment instruction.

[0030] Step S7: Move the display area corresponding to the atomic unit to be adjusted from the current group display area to the first target group display area. The bus end connected to the atomic unit to be adjusted moves with the atomic unit to be adjusted, and the logical interconnection relationship between the atomic units remains unchanged.

[0031] Step S8: Update {AUG1, AUG2, ... AGU} in the physical interconnect database. Ka}

[0032] It should be noted that through steps S6-S8, the first physical layout adjustment command can be generated through the display interface by clicking on the display area, staying in the display area for more than a preset time, or dragging the display area. This allows for intuitive adjustment of the physical layout and synchronous updates to the physical interconnection database, thus improving the efficiency of physical layout adjustment.

[0033] During the physical layout process, additional atomic units can be added. As one embodiment, step S5 is followed by:

[0034] Step S6': Receive the second physical layout adjustment instruction, and add atomic unit identifiers, second target group identifiers, and logical interconnection relationships between atomic units (A'_B1'_CMD1", A'_B2'_CMD2", ..., A'_B Kc '_CMD Kc A' represents the identifier for the newly added atomic unit, B ic 'A' and 'B' are the identifiers of existing atomic units in the currently displayed interface. ic '{AU1,AU2,...,AU K2}, CMD ic "Used to obtain the corresponding IDF from the interface description refactoring library."

[0035] Step S7': Add a display area corresponding to the newly added atomic unit identifier to the group display area corresponding to the second target group identifier, based on (A'_B1'_CMD1", A'_B2'_CMD2", ..., A'_B Kc '_CMD Kc Establish A' and B ic The bus between ';

[0036] Step S8': Update {AUG1, AUG2, ... AGU} in the physical interconnect database. Ka} and (A1_B1_CMD1',A2_B2_CMD2',...,A Kb _B Kb _CMD Kb ').

[0037] It should be noted that through steps S6'-S8', a second physical layout adjustment command can be generated through the display interface by clicking on the display area, staying in the display area for more than a preset time, or dragging the display area. This allows for intuitive adjustment of the physical layout and synchronous updates to the physical interconnection database, thus improving the efficiency of physical layout adjustment.

[0038] As one embodiment, step S1 includes:

[0039] Step S11, according to Mod i1 The submodule identifier and subatomic unit identifier determine Mod1, Mod2, ..., Mod K1 AU1, AU2, ..., AU K2 The hierarchical relationship between them;

[0040] Step S12: According to (X1_Y1_CMD1,X2_Y2_CMD2,...,X K4 _Y K4 _CMD K4 Determine each X i5 and Y i5 The IDF between them generates X i5 and Y i5 The bus between them, constructing each X i5 and Y i5 The interconnections between them are used to construct the logical interconnection relationship of the chips.

[0041] As one embodiment, the logical interconnect database also includes pre-written RTL code for each atomic unit, IDF. i3 Including the unique identifier of the interface, IDF-ID i3 Z4(i3) signals (Sig i3 1 Sig i3 2 ,...,Sig i3 z4 (i3) ), Sig i3 i4 Includes signal direction, signal width Wid(i3,i4), and reset value (RST). i3i4 1 RSTi3i4 2 , ..., RST i3i4 Wid (i3,i4) ) and default value (Def i3i4 1 , Def i3i4 2 , ...,Def i3i4 Wid(i3,i4) The values ​​of i3 range from 1 to K3, and the values ​​of i4 range from 1 to Z4(i3), where Z4(i3) is a function of i3. Preferably, IDF-ID i3 This is related to the interface type. Interface types include, for example, AXI, PCIe, HBM, SATA, USB bus, or a custom bus interface. Preferably, all interfaces are buses. The signal direction can be set to input, output, or bidirectional (InOut). The signal width Wid(i3,i4) is the signal Sig. i3 i4 The number of signal wires used. Preferably, IDF. i3 It may also include signal description metadata, for example, implemented as a string. Signal description metadata can be used to describe the composition, function, effect, or purpose of the signal, or it can be used to generate a text document. The text document can be implemented as a Text, Word, or other text type document. Preferably, IDF... i3 It also includes timing diagram information, such as an IDF implementation. i The timing diagram image, or the storage path of the timing diagram image. Timing diagram information can be used to obtain the timing diagram corresponding to the signal and to visualize it.

[0042] As one embodiment, the K4 design interconnects are assembled into DIY = (X1_Y1_CMD1_CON1, X2_Y2_CMD2_CON2, ..., X K4 _Y K4 _CMD K4 _CON K4 CON i5 For X i5 and Y i5 Delay adjustment information between X i5 and Y i5 When they are father and son, X i5 and Y i5 The delay adjustment information between them is empty; CON i5 Including the corresponding IDF type identifier IDFS i5 Delay levels PRO i5 Clock domain identifier CLK i5Each IDF type identifier corresponds to a delay module and delay unit, and the number of delay levels is determined based on the chip's physical layout. The delay adjustment unit can be implemented as a Flip-Flop, and each delay unit can delay for one clock cycle, i.e., one clock cycle.

[0043] Step S12 further includes:

[0044] Step S121, based on CON i5 In X i5 and Y i5 The corresponding delay adjustment module WR is generated on the bus between them. i5 WR i5 Including PRO i5 Each corresponding delay adjustment unit RM i5 WR i5 and RM i5 Connect to CLK i5 On the clock signal.

[0045] Furthermore, in step S2, A ib _B ib _CMD ib 'Including the corresponding WR i5 ib And following A during the physical recombination process ib RM undergoing physical reorganization i Quantity PRO1 i5 ib and following B ib RM undergoing physical reorganization i5 Quantity PRO2 i5 ib PRO1 i5 ib +PRO2 i5 ib =PRO i5 ib In step S3, A ib and PRO1 i5 ib RM i5 ib As a whole, it is assigned to the corresponding physical group, B ib and PRO2 i5 ib RM i5 ib As a whole, they were assigned to the corresponding physical groups.

[0046] As one embodiment, in step S5, A ib The atomic unit display area also includes PRO1 i5ib RM i5 ib The display area, B ib The atomic unit display area also includes PRO2 i5 ib RM i5 ib The display area allows for a clear and intuitive display of delay adjustments.

[0047] As one embodiment, step S5 is followed by:

[0048] Step S6”: Receive the third physical layout adjustment instruction, and parse out the atomic unit identifier A to be delayed from the third physical layout adjustment instruction. ib B ib and the corresponding PRO1 i5 ib’ and PRO2 i5 ib’ .

[0049] Step S7”: Move A, which needs to be adjusted for delay, on the display interface. ib B ib The corresponding RM i5 ib This makes A, which needs to be delayed, ib The display area includes PRO1 i5 ib’ Each corresponding RM i5 ib The display area, B, is to be adjusted for delay. ib The display area includes PRO2 i5 ib’ Each corresponding RM i5 ib The display area.

[0050] Step S8”: Update (A1_B1_CMD1',A2_B2_CMD2',...,A) in the physical interconnect database. Kb _B Kb _CMD Kb ').

[0051] It should be noted that through steps S6”-S8”, a third physical layout adjustment command can be generated through the display interface by clicking on the display area, staying in the display area for more than a preset time, or dragging the display area. This allows for intuitive adjustment of the physical layout and synchronous updates to the physical interconnection database, thus improving the efficiency of physical layout adjustment.

[0052] The system described in this invention can generate physical layout diagrams directly through a display interface based on an interface description reconfiguration library, a logical interconnection database, and a physical interconnection database. This allows for quick and intuitive physical reconfiguration without direct manipulation of RTL code or adjustment of logical interconnection relationships. Furthermore, delay adjustments can be made based on the display interface, improving the efficiency of physical reconfiguration and delay adjustment, thereby enhancing chip design efficiency.

[0053] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the steps as sequential processes, many of these steps can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the steps can be rearranged. A process can be terminated when its operation is complete, but it may also have additional steps not included in the figures. A process can correspond to a method, function, procedure, subroutine, subroutine, etc.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A chip design interconnect reconfiguration system based on a display interface, applied to the reconfiguration process of chip logic interconnects to physical interconnects, characterized in that, This includes an interface description refactoring library, a logical interconnect database, a physical interconnect database, a display interface, a processor, and a memory storing computer programs. The interface description refactoring library includes K3 predefined interface refactoring structures IDF=(IDF1,IDF2,...,IDF...). K3 The logical interconnect database includes K1 modules (Mod1, Mod2, ..., Mod...). K1 K2 atomic units (AU1, AU2, ..., AU) K2 K4 interconnected design assembly DIY = (X1_Y1_CMD1, X2_Y2_CMD2, ..., X K4 _Y K4 _CMD K4 ), X i5 and Y i5 Belongs to {Mod1,Mod2,...,Mod K1 ,AU1,AU2,...,AU K2 The value of i5 ranges from 1 to K4, and CMD... i5 Used to obtain the corresponding IDF from the interface description refactoring library, Mod i1 Including the module's unique identifier (MID) i and Mod i1 The submodule identifier and subatomic unit identifier; the physical interconnect database is initially empty; When the processor executes the computer program, it performs the following steps: Step S1: Based on (X1_Y1_CMD1, X2_Y2_CMD2,..., X K4 _Y K4 _CMD K4 (Mod1, Mod2, ..., Mod) K1 (AU1,AU2,...,AU) K2 Constructing chip logic interconnections; Step S2: Determine the logical interconnection relationship between atomic units (A1_B1_CMD1) based on the chip logical interconnection relationship. , , A2_B2_ CMD2 , , ... , A Kb _B Kb _ CMD Kb , A ib B ib Belonging to {AU1,AU2,...,AU} K2 }, CMD ib , Used to obtain the corresponding IDF from the interface description refactoring library, the value of ib ranges from 1 to Kb; Step S3: Based on the physical layout information, group {AU1, AU2, ..., AU...} K2 } Divide into Ka physics groups {AUG1, AUG2, ..., AUG} Ka },AUG ia Includes at least one AU i2 Each AU i2 Classified as one of the AUG ia In this context, the value range of ia is from 1 to Ka, and the value range of i2 is from 1 to K2. Step S4: Set {AUG1, AUG2, ... AUG} Ka } and (A1_B1_CMD1) , , A2_B2_ CMD2 , , ... , A Kb _B Kb _CMD Kb , Stored in the physical interconnect database; Step S5: Display a physical layout diagram on the display interface based on the physical interconnection database. The physical layout diagram includes Ka group display areas, K2 atomic unit display areas, and Kb buses. Each atomic unit display area is located in the corresponding group area, and the ib-th bus is set in A. ib The atomic unit display area and B ib Between the atomic unit display areas, the value of ib ranges from 1 to Kb.

2. The system according to claim 1, characterized in that, After step S5, the following is included: Step S6: Receive the first physical layout adjustment instruction, and parse the atomic unit identifier to be adjusted, the current group identifier, and the first target group identifier from the first physical layout adjustment instruction; Step S7: Move the display area corresponding to the atomic unit to be adjusted from the current group display area to the first target group display area. The bus end connected to the atomic unit to be adjusted moves with the atomic unit to be adjusted, and the logical interconnection relationship between the atomic units remains unchanged. Step S8: Update {AUG1, AUG2, ... AUG} in the physical interconnect database. Ka } 3. The system according to claim 1, characterized in that, After step S5, the following is included: Step S6 ’ Receive the second physical layout adjustment instruction, and add atomic unit identifiers, second target group identifiers, and logical interconnection relationships between atomic units from the second physical layout adjustment instruction (A). , _B1 , _ CMD1 , , A , _B2 , _CMD2 , , A , _B Kc , _ CMD Kc , , A , To add a new atomic unit identifier, B ic , A is an identifier for an existing atomic unit in the currently displayed interface. , B ic , CMD ic , , Used to obtain the corresponding IDF from the interface description refactoring library; Step S7 ’ 1. Add a display area corresponding to the newly added atomic unit identifier to the group display area corresponding to the second target group identifier, based on (A) , _B1 , _ CMD1 , , A , _B2 , _ CMD2 , , A , _B Kc , _ CMD Kc , , Establish A , With B ic , Bus between; Step S8 ’ Update the {AUG1, AUG2, ... AUG} in the physical interconnect database. Ka } and (A1_B1_CMD1) , , A2_B2_ CMD2 , , ... , A Kb _B Kb _ CMD Kb , ).

4. The system according to claim 1, characterized in that, Step S1 includes: Step S11, according to Mod i1 The submodule identifier and subatomic unit identifier determine Mod1, Mod2, ..., Mod K1 AU1, AU2, ..., AU K2 The hierarchical relationship between them; Step S12: According to (X1_Y1_CMD1, X2_Y2_CMD2,..., X K4 _Y K4 _CMD K4 Determine each X i5 and Y i5 The IDF between them generates X i5 and Y i5 The bus between them, constructing each X i5 and Y i5 The interconnections between them are used to construct the logical interconnection relationship of the chips.

5. The system according to claim 4, characterized in that, The K4 design interconnections are assembled into DIY = (X1_Y1_CMD1_CON1, X2_Y2_CMD2_CON2, ..., X K4 _Y K4 _CMD K4 _CON K4 ), CON i5 For X i5 and Y i5 Delay adjustment information between X i5 and Y i5 When they are father and son, X i5 and Y i5 The delay adjustment information between them is empty; CON i5 Including the corresponding IDF type identifier IDFS i5 Delay levels PRO i5 Clock domain identifier CLK i5 Each IDF type identifier corresponds to a delay module and a delay unit, and the number of delay levels is determined based on the chip physical layout; Step S12 further includes: Step S121, based on CON i5 In X i5 and Y i5 The corresponding delay adjustment module WR is generated on the bus between them. i5 WR i5 Including PRO i5 Each corresponding delay adjustment unit RM i5 WR i5 and RM i5 Connect to CLK i5 On the clock signal.

6. The system according to claim 5, characterized in that, In step S2, A ib _B ib _ CMD ib , Including the corresponding WR i5 ib And following A during the physical recombination process ib RM undergoing physical reorganization i Quantity PRO1 i5 ib and following B ib RM undergoing physical reorganization i5 Quantity PRO2 i5 ib PRO1 i5 ib +PRO2 i5 ib =PRO i5 ib ; In step S3, A ib and PRO1 i5 ib RM i5 ib As a whole, it is assigned to the corresponding physical group, B ib and PRO2 i5 ib RM i5 ib As a whole, they were assigned to the corresponding physical groups.

7. The system according to claim 6, characterized in that, In step S5, A ib The atomic unit display area also includes PRO1 i5 ib RM i5 ib The display area, B ib The atomic unit display area also includes PRO2 i5 ib RM i5 ib The display area.

8. The system according to claim 7, characterized in that, After step S5, the following is included: Step S6 ’ ’ Receive a third physical layout adjustment command, and parse the atomic unit identifier A to be delayed from the third physical layout adjustment command. ib B ib and the corresponding PRO1 i5 ib ’ and PRO2 i5 ib’ ; Step S7 ’ ’ Move A, the model whose delay needs to be adjusted, on the display interface. ib B ib The corresponding RM i5 ib This makes A, which needs to be delayed, ib The display area includes PRO1 i5 ib ’ Each corresponding RM i5 ib The display area, B, is to be adjusted for delay. ib The display area includes PRO2 i5 ib’ Each corresponding RM i5 ib The display area; Step S8 ’ ’ Update (A1_B1_CMD1) in the physical interconnect database. , , A2_B2_ CMD2 , , ... , A Kb _B Kb _ CMD Kb , ).

9. The system according to claim 2, 3 or 8, characterized in that, Physical layout adjustment instructions are generated by clicking on the display area, staying in the display area for more than a preset time, or dragging the display area. The physical layout adjustment instructions include a first physical layout adjustment instruction, a second physical layout adjustment instruction, and a third physical layout adjustment instruction.

10. The system according to claim 1, characterized in that, The display interface is a GUI interface.

Images