A display panel and display device

Abstract

Embodiments of the present application disclose a display panel and a display device. The display panel comprises a special-shaped frame area, the special-shaped frame area intersects with the boundary line of the display area and the extension lines of the data signal lines and the scan signal lines; the special-shaped frame area comprises a gate drive circuit area and a source drive circuit area, the source drive circuit area is located between the gate drive circuit area and the display area; the gate drive circuit area is provided with a shift register circuit, the source drive circuit area is provided with a demultiplexing circuit, the special-shaped frame area further comprises a plurality of data fan-out wires, the data fan-out wires are located in different film layers of the display panel respectively with the shift register circuit and the demultiplexing circuit, and the projection of the data fan-out wires and the shift register circuit and / or the demultiplexing circuit on the light emitting surface of the display panel overlaps. Embodiments of the present application solve the problem that the existing special-shaped vehicle-mounted display product is relatively wide at the special-shaped frame position, realize the reasonable layout of the special-shaped frame area structure, and meet the existing narrow frame trend.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the diversification of display usage scenarios, the demand for irregularly shaped screens is increasing, such as in automotive electronic rearview mirrors. As the market and end-user audiences diversify, various irregularly shaped products are emerging. However, existing irregularly shaped automotive display products tend to have wider bezels at the irregular shape locations, failing to meet the trend towards narrow bezels. Summary of the Invention

[0003] This invention provides a display panel and display device that rationally arranges the irregularly shaped bezel area structure to achieve a narrow bezel design in the irregularly shaped bezel area, thus meeting the trend of narrow bezels.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including a display area and a non-display area, wherein the non-display area is interconnected with the display area; the display area includes multiple data signal lines and multiple scan signal lines, wherein the data signal lines and the scan signal lines intersect;

[0005] The non-display area includes an irregularly shaped border area, the boundary line of which intersects with the display area and the extension lines of the data signal line and the scan signal line; the irregularly shaped border area includes a gate driving circuit area and a source driving circuit area, the source driving circuit area being located between the gate driving circuit area and the display area;

[0006] The gate drive circuit region is provided with a shift register circuit, which is electrically connected to the scan signal line and is used to sequentially provide gate drive signals to multiple scan signal lines.

[0007] The source drive circuit area is provided with a demultiplexing circuit, which is electrically connected to the data signal line and is used to provide data signals to multiple data signal lines in sequence.

[0008] The irregularly shaped frame area also includes multiple data fan-out traces, which are electrically connected to at least two of the data signal lines through the demultiplexing circuit.

[0009] The data fan-out traces are located in different film layers of the display panel, respectively, as are the shift register circuit and the demultiplexing circuit. The projection of the data fan-out traces on the light-emitting surface of the display panel overlaps with the projection of the shift register circuit and / or the demultiplexing circuit on the light-emitting surface of the display panel.

[0010] In a second aspect, embodiments of the present invention also provide a display device, including a display panel as described in any of the first aspects.

[0011] In the display panel and display device provided in the embodiments of the present invention, the irregularly shaped bezel area of ​​the display panel includes a gate driving circuit area and a source driving circuit area. The gate driving circuit area is provided with a shift register circuit, which can provide scanning signals to the pixel units of the display area through a scan signal line. The source driving circuit area is provided with a demultiplexing circuit, which can receive data signals according to the data fan-out traces set in the irregularly shaped bezel area, and provide data signals to the pixel units of the display area through a data signal line. This enables the driving of the corresponding pixel units in the display area and realizes the screen display function. Meanwhile, by placing the data fan-out traces in a different display panel film layer than the shift register circuit and demultiplexing circuit, and by setting the data fan-out traces to overlap with the projection of the shift register circuit and / or demultiplexing circuit, the data fan-out traces and the shift register circuit or demultiplexing circuit can be arranged in a vertically stacked manner. This avoids the data fan-out traces occupying too much of the horizontal area of ​​the irregular bezel area, and can shorten the horizontal spacing between the shift register circuit and the demultiplexing circuit, which can effectively reduce the horizontal width of the irregular bezel area and facilitate the realization of a narrow bezel design. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the structure of a display panel in related technologies;

[0013] Figure 2 yes Figure 1 The image shows a magnified view of a portion of the display panel within the irregularly shaped border area.

[0014] Figure 3 yes Figure 2 The image shows a cross-sectional view of the irregularly shaped border area of ​​the display panel.

[0015] Figure 4 This is a partial structural schematic diagram of a display panel provided in an embodiment of the present invention;

[0016] Figure 5 yes Figure 4 The image shown is a cross-sectional view of a portion of the display panel structure.

[0017] Figure 6 This is a partial structural schematic diagram of a display panel provided in an embodiment of the present invention;

[0018] Figure 7 yes Figure 6 The diagram shows a partial structural cross-sectional view of the display panel;

[0019] Figure 8 This is a partial structural cross-sectional view of another display panel provided in an embodiment of the present invention;

[0020] Figure 9This is a partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 10 and Figure 11 These are partial structural cross-sectional views of two more display panels provided in embodiments of the present invention;

[0022] Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention;

[0023] Figure 13 yes Figure 12 A magnified view of a portion of the display panel shown;

[0024] Figure 14 yes Figure 12 The image shown is a partial sectional view of the display panel.

[0025] Figure 15 This is a partial structural cross-sectional view of another display panel provided in an embodiment of the present invention;

[0026] Figure 16 This is a partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0027] Figure 17 yes Figure 16 The diagram shows a partial structural cross-sectional view of the display panel;

[0028] Figure 18 and Figure 19 These are partial structural cross-sectional views of two more display panels provided in embodiments of the present invention;

[0029] Figure 20 This is a partial structural cross-sectional view of another display panel provided in an embodiment of the present invention;

[0030] Figure 21 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0032] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "on" or "below" another element, it can be formed not only directly on or below the other element, but also indirectly on or below it through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0033] The term "comprising" and its variations as used in this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0034] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish the corresponding contents and are not used to limit the order or interdependence.

[0035] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0036] Figure 1 This is a schematic diagram of the structure of a display panel in related technologies. Figure 2 yes Figure 1 The image shown is a magnified view of a portion of the display panel within the irregularly shaped border area. Figure 3 yes Figure 2 The cross-sectional view of the irregularly shaped border area of ​​the display panel shown is for reference. Figures 1-3First, as those skilled in the art will know, the display area AA of the display panel will have multiple intersecting data signal lines 120' and multiple scanning signal lines 110'. The data signal lines 120' extend along the column direction Y', and the scanning signal lines 110' extend along the row direction X'. Based on this, existing irregularly shaped display panels can define a regular border area NA1 and an irregularly shaped border area NA2. The regular border area NA1 can be understood as the border area that intersects the boundary line of the display area AA only with the data signal lines 120' or scanning signal lines 110' of the display area AA. Therefore, this border area only needs to be equipped with a driving circuit that provides signals to the data signal lines 120' or scanning signal lines 110', that is, only one driving circuit needs to be set. As for the irregularly shaped border area NA2, it can be understood as the border area that intersects the boundary line of the display area AA with both the data signal lines 120' and scanning signal lines 110' of the display area AA. For example... Figure 1 The irregularly shaped border area NA2_1 is shown. At this point, since signals need to be provided to both the data signal line 120' and the scan signal line 110', two types of driving circuits are required, namely... Figure 2 The source drive circuit 12' and gate drive circuit 11' are shown in the irregularly shaped bezel area NA2_1. In addition, to achieve different functions such as VT testing and touch control, the irregularly shaped bezel area NA2 in related technologies will also include a VT testing circuit and touch control traces (not shown in the figure). Furthermore, as... Figure 2 and Figure 3 As shown, for the irregularly shaped frame area NA2, it is necessary not only to set up the source drive circuit 12', the gate drive circuit 11', the VT test circuit and the touch trace, but also to lay out the data fan-out trace 130' to provide data signals to each source drive circuit 12'.

[0037] Currently, regarding the structural layout of the irregular border area NA2, refer to Figure 2 and Figure 3 The data fan-out trace 130' is generally located between the source drive circuit 12' and the gate drive circuit 11', arranged horizontally side by side. Therefore, compared with the regular border area NA1, the irregular border area NA2 has a larger area and a wider border width due to the more complex circuit structure and the horizontal layout of the circuits and some traces, which is not conducive to narrow border design.

[0038] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, which includes a display area and a non-display area, wherein the non-display area and the display area are interconnected; the display area includes multiple data signal lines and multiple scan signal lines, wherein the data signal lines and the scan signal lines intersect.

[0039] The non-display area includes the irregularly shaped border area, the boundary line between the irregularly shaped border area and the display area, and the extension lines of the data signal lines and scan signal lines. The irregularly shaped border area includes the gate drive circuit area and the source drive circuit area, with the source drive circuit area located between the gate drive circuit area and the display area.

[0040] The gate drive circuit area is provided with a shift register circuit, which is electrically connected to the scan signal lines and is used to sequentially provide gate drive signals to multiple scan signal lines;

[0041] The source drive circuit area is equipped with a demultiplexing circuit, which is electrically connected to the data signal lines and is used to sequentially provide data signals to multiple data signal lines.

[0042] The irregularly shaped frame area also includes multiple data fan-out traces, which are electrically connected to at least two data signal lines through a demultiplexing circuit.

[0043] The data fan-out traces are located in different film layers of the display panel, respectively, as are the shift register circuit and the demultiplexing circuit. The projection of the data fan-out traces on the light-emitting surface of the display panel overlaps with the projection of the shift register circuit and / or the demultiplexing circuit on the light-emitting surface of the display panel.

[0044] In the above technical solution, the irregular bezel area of ​​the display panel includes a gate driving circuit area and a source driving circuit area. The gate driving circuit area is equipped with a shift register circuit, which can provide scanning signals to the pixel units of the display area through scanning signal lines. The source driving circuit area is equipped with a demultiplexing circuit, which can receive data signals according to the data fan-out traces set in the irregular bezel area, and provide data signals to the pixel units of the display area through data signal lines. This enables the driving of the corresponding pixel units in the display area and realizes the screen display function. Meanwhile, by placing the data fan-out traces in a different display panel film layer than the shift register circuit and demultiplexing circuit, and by setting the data fan-out traces to overlap with the projection of the shift register circuit and / or demultiplexing circuit, the data fan-out traces and the shift register circuit or demultiplexing circuit can be arranged in a vertically stacked manner. This avoids the data fan-out traces occupying too much of the horizontal area of ​​the irregular bezel area, and can shorten the horizontal spacing between the shift register circuit and the demultiplexing circuit, which can effectively reduce the horizontal width of the irregular bezel area and facilitate the realization of a narrow bezel design.

[0045] The above is the core idea of ​​this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0046] Figure 4This is a partial structural diagram of a display panel provided in an embodiment of the present invention. Figure 5 yes Figure 4 The diagram shown is a sectional view of a portion of the display panel structure. (Refer to...) Figure 4 and Figure 5 The display panel includes a display area AA and a non-display area NA, with the non-display area NA and the display area AA interconnected. The display area AA includes multiple data signal lines 120 and multiple scan signal lines 110, with the data signal lines 120 and scan signal lines 110 intersecting.

[0047] The non-display area NA includes the irregularly shaped border area NA2. The boundary line of the irregularly shaped border area NA2 and the display area AA intersects with the extension lines of the data signal line 120 and the scan signal line 110. The irregularly shaped border area NA2 includes the gate drive circuit area and the source drive circuit area (not shown in the figure). The source drive circuit area is located between the gate drive circuit area and the display area AA.

[0048] The gate drive circuit area is provided with a shift register circuit 11, which is electrically connected to the scan signal line 110 and is used to sequentially provide gate drive signals to multiple scan signal lines 110.

[0049] The source drive circuit area is provided with a demultiplexing circuit 12, which is electrically connected to the data signal line 120 and is used to provide data signals to multiple data signal lines 120 in sequence.

[0050] The irregular border area NA2 also includes multiple data fan-out traces 130, which are electrically connected to at least two data signal lines 120 via a demultiplexing circuit 12.

[0051] The data fan-out trace 130 is located in different film layers of the display panel, respectively, with the shift register circuit 11 and the demultiplexing circuit 12. The projection of the data fan-out trace 130 on the light-emitting surface of the display panel overlaps with the projection of the shift register circuit 11 and / or the demultiplexing circuit 12 on the light-emitting surface of the display panel.

[0052] In the display area AA, the scan signal lines 110 extend in the row direction (for example, along the first direction X) and are arranged in the column direction (for example, along the second direction Y). The data signal lines 120 extend in the column direction (for example, along the second direction Y) and are arranged in the row direction (for example, along the first direction X). Those skilled in the art will understand that the multiple scan signal lines 110 and multiple data signal lines 120 in the display area AA intersect to form multiple pixel units (not shown in the figure). The scan signal lines 110 provide scan signals to the pixel units, and the data signal lines 120 provide data signals to the pixel units, thereby driving each pixel unit in the display area to light up sequentially, achieving the display of the entire image. Based on this, as mentioned earlier, for irregularly shaped display panels, the border area NA can be divided into a regular border area NA1 and an irregularly shaped border area NA2. The boundary line between the regular border area NA1 and the display area AA intersects only with the scan signal line 110 or the data signal line 120. Therefore, a shift register circuit 11 for the scan signal line 110 or a demultiplexing circuit 12 for the data signal line 120 can be set in the regular border area NA1. The regular border area NA1 is generally located on both sides of the display area AA in the first direction X or the second direction Y. For the irregularly shaped border area NA2, its boundary line with the display area AA intersects with both the data signal line 120 and the scan signal line 110, respectively. That is, a demultiplexing circuit 12 and a shift register circuit 11 need to be set for the data signal line 120 and the scan signal line 110 respectively. The irregularly shaped border area NA2 is generally located at the boundary between the two types of regular border areas NA1. The difference between the two types of regular border areas NA1 is that one is located on one side of the display area AA in the first direction X, and the other is located on one side of the display area AA in the second direction Y. In a simplified sense, the irregular border area NA2 can be understood as the border area at the corner of the display area AA.

[0053] In this embodiment of the invention, regarding the circuit and wiring layout in the irregularly shaped frame area NA2, the data fan-out wiring 130 that provides data signals to the demultiplexing circuit 12 is positioned in different film layers of the display panel, respectively, as the shift register circuit 11 and the demultiplexing circuit 12. The projection of the data fan-out wiring 130 onto the light-emitting surface of the display panel overlaps with the projections of the shift register circuit 11 and / or the demultiplexing circuit 12 onto the light-emitting surface of the display panel. In effect, the data fan-out wiring 130 is moved vertically above the shift register circuit 11 and / or the demultiplexing circuit 12. Figure 4In the example, the data fan-out trace 130 is located above the shift register circuit 11. This allows the data fan-out trace 130 and the shift register circuit 11 or demultiplexing circuit 12 to be arranged vertically in a stacked manner. This avoids the problem of excessive horizontal spacing between the shift register circuit 11 and the demultiplexing circuit 12 when the data fan-out trace 130 is placed between them. Shortening the horizontal spacing between the shift register circuit and the demultiplexing circuit effectively reduces the horizontal width of the irregular border area, preventing the data fan-out trace 130 from occupying too much horizontal area of ​​the irregular border area NA2, which is beneficial for achieving a narrow border design. Here, "vertical" refers to the direction perpendicular to the plane formed by the intersection of the first direction X and the second direction Y, i.e., as shown... Figure 5 The Z direction is shown; the lateral direction refers to the direction parallel to the plane formed by the intersection of the first direction X and the second direction Y, for example... Figure 4 W direction shown.

[0054] Figure 6 This is a partial structural diagram of a display panel provided in an embodiment of the present invention. Figure 7 yes Figure 6 The partial structural cross-sectional view of the display panel shown is for reference. Figure 6 First, the shift register circuit 11 includes multiple shift registers 111 and multiple first signal lines 112; the multiple shift registers 111 are cascaded sequentially; the multiple first signal lines 112 extend in parallel and are located on the side of the shift registers 111 away from the display area AA; each shift register 111 is electrically connected to at least one first signal line 112. (Reference) Figure 7 The projection of the optional data fan-out trace 130 on the light-emitting surface of the display panel overlaps with the projection of the shift register 111 and / or the first signal trace 112 on the light-emitting surface of the display panel. Figure 7 In the example, both the shift register 111 and the first signal trace 112 are provided with data fan-out traces 130.

[0055] First, it should be noted that, as Figure 6 In the structural diagram shown, signal traces and connecting lines are represented by dashed lines, solid lines, and thick solid lines, respectively. These are only used to distinguish between different signal lines and do not represent the actual width or shape of the signal lines. This method will be used to distinguish them in subsequent diagrams, and no further explanation will be provided.

[0056] Those skilled in the art will understand that the shift register circuit 11 needs to provide scan signals to the scan signal lines 110 line by line. To achieve the line-by-line scanning process, it needs to output scan signals sequentially through cascaded shift registers 111. In the cascaded shift registers 111, the first shift register 111 receives the trigger signal STV and generates a scan signal, which is then output to the corresponding scan signal line 110 and the next-level shift register 111. The next-level shift register 111 then shifts the scan signal to generate a second-level scan signal, which is also output to the corresponding scan signal line 110 and the next-level shift register 111, and so on, thereby realizing the scanning process of all scan signal lines 110. The first signal trace 112 in the shift register circuit 11 can be understood as the clock signal, level signal, trigger signal STV, etc. required during the operation of the shift register circuit 11. For example, the clock signal may include two signals, CK and XCK. In other shift register circuit designs, only one clock signal CK may be set, or more clock signals may be set. This embodiment does not impose any restrictions. The level signal may include a high-level signal VGH and a low-level signal VGL. Therefore, for multiple cascaded shift registers 111, these first signal traces 112 need to be laid on the side away from the display area AA to provide clock signals, level signals, trigger signals, etc. to the shift registers 111.

[0057] In summary, the area where the shift register circuit 11 is located can be divided into the area where the shift register 111 is located and the area where the first signal trace 112 is located. Based on this, in a specific embodiment of the present invention, the projection of the data fan-out trace 130 on the light-emitting surface of the display panel overlaps with the projections of the shift register 111 and / or the first signal trace 112 on the light-emitting surface of the display panel. In essence, the data fan-out trace 130 is set in the area where the shift register 111 is located, stacked vertically with the shift register 111; or, it is set in the area where the first signal trace 112 is located, stacked vertically with the first signal trace 112; or, it is partially set in the area where the shift register 111 is located, stacked vertically with the shift register 111, and partially set in the area where the first signal trace 112 is located, stacked vertically with the first signal trace 112.

[0058] The following section will further introduce the specific location of the data fan-out routing line 130 and the corresponding optimization design. Figure 8 This is a partial structural cross-sectional view of another display panel provided in an embodiment of the present invention, with reference to... Figure 8Optionally, the projection of the data fan-out trace 130 on the light-emitting surface of the display panel overlaps with the projection of the first signal trace 112 on the light-emitting surface of the display panel; the data fan-out trace 130 and the first signal trace 112 are located in different film layers of the display panel, and a signal shielding layer 201 is provided between the film layers where the data fan-out trace 130 and the first signal trace 112 are located.

[0059] The data fan-out trace 130 is electrically connected to the demultiplexing circuit 12 and is responsible for providing data signals to the demultiplexing circuit 12. The first signal trace 112 contains clock signal lines and trigger signal lines, responsible for providing clock signals, trigger signals, and other pulse signals to the shift register. Clearly, when the data fan-out trace 130 is stacked on top of the first signal trace 112, voltage changes on the first signal trace 112 will capacitively couple with the data fan-out trace 130. The higher frequency clock signals and trigger signals will interfere with the data signals transmitted on the data fan-out trace 130, causing data signal deviations and resulting in bright and dark lines on the display, thus affecting the accuracy of pixel display. Based on this, in this embodiment, the data fan-out trace 130 and the first signal trace 112 are arranged in different film layers of the display panel, and a signal shielding layer 201 is provided between the film layers where the data fan-out trace 130 and the first signal trace 112 are located. The signal shielding layer 201 can shield the interference of high-frequency signals such as clock signals and trigger signals in the first signal trace 112 on the data signals transmitted on the data fan-out trace 130. This can ensure the normal transmission of data signals on the data fan-out trace 130, ensure that the shift register circuit signals and the data fan-out trace signals are independent of each other, thereby improving the accuracy of pixel display, avoiding uneven display problems such as bright and dark lines in the display screen, and improving the display quality of the display panel.

[0060] Continue to refer to Figure 8 In a specific embodiment, the display panel further includes a substrate 200, a first metal layer 210, a second metal layer 220, and a third metal layer 230. In a direction perpendicular to the plane of the substrate and away from the substrate 200, the first metal layer 210, the second metal layer 220, and the third metal layer 230 are sequentially distributed on one side of the substrate 200. An interlayer insulating layer 202 is provided between adjacent layers of the first metal layer 210, the second metal layer 220, and the third metal layer 230. The data fan-out trace 130 is located in the third metal layer 230, the first signal trace 112 is located in the first metal layer 210, and the signal shielding layer 201 is located in the second metal layer 220.

[0061] The first metal layer 210, the second metal layer 220, and the third metal layer 230 are the basic metal layers for fabricating circuits and traces in the display panel. By patterning the metal layers, traces and connections between circuit components can be formed. The data fan-out trace 130 is fabricated in the third metal layer 230; the first signal trace 112 is fabricated in the first metal layer 210. The signal shielding layer 201 between the data fan-out trace 130 and the first signal trace 112 can be fabricated in the second metal layer 220 between the third metal layer 230 and the first metal layer 210. It can be understood that reusing a portion of the second metal layer 220 as the signal shielding layer 201 avoids the need for a separate metal layer for the signal shielding layer 201, thereby simplifying the fabrication process and technology of the display panel. This allows for cost savings while shielding the data fan-out trace 130 from interference through the signal shielding layer 201.

[0062] Continue to refer to Figure 8 More specifically, the shift register circuit 11 also includes multiple first connection traces 113, which are located in the second metal layer 220. One end of the first connection trace 113 is electrically connected to the shift register 111, and the other end is electrically connected to the first signal trace 112 through a first via 20201. The first via 20201 is located in the interlayer insulating layer 202 between the first metal layer 210 and the second metal layer 220. The projection of the signal shielding layer 201 on the light-emitting surface of the display panel does not overlap with the projection of the first connection trace 113 on the light-emitting surface of the display panel.

[0063] The first connection trace 113 is mainly responsible for providing the signal on the corresponding first signal trace 112 to the shift register 111. Since the first signal trace 112 is located in the first metal layer 210, and the component in the shift register 111 that receives the signal transmitted by the first signal trace 112 is generally a transistor, whose source, drain, or gate is generally located in the second metal layer 220, it is necessary to set the first connection trace 113 and the first via 20201 to achieve the crossing of the two metal layers when connecting the first signal trace 112 and the shift register 111. Of course, it can also be understood that in order to avoid the influence of the signal shielding layer 201 on the same layer, when setting the first signal trace 112, it is necessary to insulate the first signal trace 112 from the signal shielding layer 201. That is, when fabricating the second metal layer 220, it is necessary to separate the pattern of the first connection trace 113 and the signal shielding layer 201 by patterning.

[0064] Furthermore, to achieve better shielding, as in the above embodiment, a fixed potential signal can be introduced into the signal shielding layer 201 between the data fan-out trace 130 and the first signal trace 112.

[0065] Specifically, refer to Figure 6 In a specific embodiment of the present invention, the first signal trace 112 includes a first-level signal line V1 and a second-level signal line V2, wherein the potential on the first-level signal line V1 is lower than the potential on the second-level signal line V2. The first-level signal line V1 or the second-level signal line V2 can be electrically connected to the signal shielding layer 201. The first-level signal line V1 can be understood as the low-level signal line VGL in the shift register circuit 11, and the second-level signal line V2 can be understood as the high-level signal line VGH in the shift register circuit 11. In this embodiment, the high-level signal or low-level signal in the shift register circuit 11 is essentially fed into the signal shielding layer 201 to stabilize the potential of the signal shielding layer 201. It should be added that, according to... Figure 8 As shown in the cross-sectional view, when a fixed level signal is transmitted to the signal shielding layer 201 via the first level signal line V1 or the second level signal line V2 in the first signal trace 112, a hole can be drilled in the interlayer insulating layer 202 between the first metal layer 210 and the second metal layer 220 to achieve electrical connection between the signal shielding layer 201 and the first level signal line V1 or the second level signal line V2, thereby realizing the transmission of a fixed signal.

[0066] Figure 9 This is a partial structural schematic diagram of another display panel provided in an embodiment of the present invention, for reference. Figure 8 and Figure 9 In another specific embodiment of the present invention, the non-display area NA further includes a bonding pad 13 and a fixed potential signal line 150. The bonding pad 13 is used to bond the driver chip IC. One end of the fixed potential signal line 150 is electrically connected to the signal shielding layer 201, and the other end is electrically connected to the driver chip IC through the bonding pad 13. The driver chip IC is used to provide a fixed potential signal to the signal shielding layer 201 through the fixed potential signal line 150.

[0067] In the two embodiments described above, by introducing a fixed potential signal into the signal shielding layer 201, the signal shielding layer 201 can have a stable potential, thereby shielding the electromagnetic interference generated by the high-frequency signal. This allows the signal shielding layer 201 to effectively block the electromagnetic interference generated by the first signal trace 112 on the data fan-out trace 130, effectively solving the signal interference problem caused by capacitive coupling between signal lines.

[0068] Figure 10 and Figure 11 These are partial structural cross-sectional views of two more display panels provided in embodiments of the present invention, for reference. Figure 10 and Figure 11The display panel further includes a substrate 200, a first metal layer 210, a second metal layer 220, and a third metal layer 230. The first metal layer 210, the second metal layer 220, and the third metal layer 230 are sequentially distributed on one side of the substrate 200 in a direction perpendicular to the plane of the substrate 200 and away from the substrate 200. An interlayer insulating layer 202 is provided between adjacent layers of the first metal layer 210, the second metal layer 220, and the third metal layer 230. A first signal trace 112 is located on the first metal layer 210, and at least a portion of the data fan-out traces 130 are located on the second metal layer 220.

[0069] Specifically, the data fan-out routing 130 can be as follows: Figure 10 All of the shown elements are disposed in the second metal layer 220, or as shown in the figure. Figure 11 As shown, a portion is disposed in the second metal layer 220, and another portion is disposed in the third metal layer 230. In this embodiment, at least a portion of the data fan-out trace 130 is disposed in the second metal layer 220. Essentially, this also involves stacking the data fan-out trace 130 on top of the first signal trace 112 located in the first metal layer 210, thereby preventing the data fan-out trace 130 from occupying the lateral area of ​​the irregularly shaped border area NA2, facilitating narrow border design. For example, Figure 11 The illustrated embodiment is primarily for situations where the number of first signal traces 112 is relatively small, while the number of data fan-out traces 130 is relatively large. It can be understood that in this case, if all the data fan-out traces 130 are placed on the third metal layer 230 and above the first signal traces 112, the lateral width of the area where the first signal traces 112 are located cannot accommodate all the data fan-out traces 130. In this situation, some of the data fan-out traces 130 can be placed in the second metal layer 220. Furthermore, as... Figure 11 As shown, in the area of ​​the second metal layer 220 where no data fan-out trace 130 is provided, a signal shielding layer 201 can also be provided to isolate the capacitive coupling between the first signal trace 112 of the first metal layer 210 and the data fan-out trace 130 of the third metal layer 230.

[0070] Furthermore, as mentioned earlier, since the first signal trace 112 needs to transmit high-frequency clock signals or trigger signals, when the data fan-out trace 130 is stacked on top of the first signal trace 112, capacitive coupling can easily occur between the traces, causing electromagnetic interference to the data fan-out trace 130. Therefore, when at least a portion of the data fan-out trace 130 is placed on the second metal layer 220 to be stacked on top of the first signal trace 112, it is also necessary to overcome the capacitive coupling problem between this portion of the data fan-out trace 130 and the first signal trace 112.

[0071] Specifically, please refer to Figure 10 and Figure 11The interlayer insulating layer 202 includes a first interlayer insulating layer 2021 and a second interlayer insulating layer 2022. The first interlayer insulating layer 2021 is located between the first metal layer 210 and the second metal layer 220, and the second interlayer insulating layer 2022 is located between the second metal layer 220 and the third metal layer 230. The thickness d1 of the first interlayer insulating layer 2021 is greater than the thickness d2 of the second interlayer insulating layer 2022, and / or the dielectric constant ε1 of the first interlayer insulating layer 2021 is less than the dielectric constant ε2 of the second interlayer insulating layer 2022.

[0072] As those skilled in the art will know, the capacitance formula is C = εA / d, where C is directly proportional to the dielectric constant ε and inversely proportional to the thickness d of the dielectric layer between the capacitor plates. In this embodiment, the thickness d of the first interlayer insulating layer 2021 between the data fan-out trace 130 in the second metal layer 220 and the first signal trace 112 in the first metal layer 210 is increased, thereby reducing the capacitance between the two traces and preventing capacitive coupling. Similarly, setting a smaller dielectric constant ε for the first interlayer insulating layer 2021 between the data fan-out trace 130 in the second metal layer 220 and the first signal trace 112 in the first metal layer 210 can also reduce the capacitance between the two traces and prevent capacitive coupling.

[0073] It is understandable that increasing the thickness of the first interlayer insulating layer 2021 while decreasing its dielectric constant can better reduce capacitance and thus avoid capacitive coupling between the two traces. Those skilled in the art can select and configure this according to the actual situation. Furthermore, it should be noted that the first interlayer insulating layer 2021 can be made of a different insulating material than the second interlayer insulating layer 2022 to achieve the purpose of reducing the dielectric constant.

[0074] It should also be noted that in practical applications, since the components in the shift register 111 will occupy the first metal layer 210 and the second metal layer 220, when laying out some data fan-out traces 130 in the second metal layer 220, they can be laid out above the first signal trace 112. That is, the data fan-out traces 130 in the second metal layer 220 can be set to not overlap with the projection of the shift register 111, but overlap with the projection of the first signal trace 112.

[0075] Continue to refer to Figure 6The data fan-out trace 130 includes a first trace segment 1301, the extension direction of which is parallel to the extension direction of the boundary line between the irregular frame area NA2 and the display area AA. In a specific embodiment, the projection of a portion of the first trace segment 1301 of the data fan-out trace 130 on the light-emitting surface of the display panel may overlap with the projection of the shift register 111 on the light-emitting surface of the display panel; the projection of a portion of the first trace segment 1302 of the data fan-out trace 130 on the light-emitting surface of the display panel may overlap with the projection of the first signal trace 112 on the light-emitting surface of the display panel; the data signal line 120 includes a first data signal line 1201 and a second data signal line 1202, the first trace segment 1301 and... The overlapping data fan-out traces 130 of the first signal trace 112 are electrically connected to the first data signal line 1201 through the demultiplexing circuit 12. The overlapping data fan-out traces 130 of the first trace segment 1301 and the shift register 111 are electrically connected to the second data signal line 1202 through the demultiplexing circuit 12. In the first direction X, the first data signal line 1201 is located on the side of the second data signal line 1202 near the irregular border area NA2. The first direction X is the arrangement direction of the multiple data signal lines 120.

[0076] First, it should be noted that the first segment 1301 in the data fan-out trace 130 extends parallel to the boundary line of the irregular border area NA2 and the display area AA. This means that some segments in each data fan-out trace 130 extend in parallel and are arranged along the W direction shown in the figure. Of course, to ensure electrical connection between the data fan-out trace 130 and the demultiplexing circuit 12, a second segment 1302 is also provided in the data fan-out trace 130. The second segment 1302 extends along the W direction, with its two ends connected to the first segment 1301 and the demultiplexing circuit 12, respectively. Therefore, the multiple first segments 1301 arranged in the W direction can be configured to partially overlap with the first signal trace 112 and partially overlap with the shift register 111. That is, some first segments 1301 can be located above the area where the first signal trace 112 is located, and some first segments 1301 can be located above the area where the shift register 111 is located.

[0077] It is understandable that, since the first signal trace 112 is located on the side of the shift register 111 furthest from the display area AA, the first trace segment 1301, which overlaps with the projection of the shift register 111, is farther from the display area AA than the first trace segment 1301, which overlaps with the projection of the shift register 111. Furthermore, since the data fan-out trace 130 needs to connect to at least one data signal line 120 of the display area AA via the demultiplexing circuit 12, the lengths of different data fan-out traces 130 will vary when extending them to the display area AA. This can be simply understood as the lengths of the second trace segment 1302 varying. In this embodiment, the data signal line 120 connecting the data fan-out trace 130 overlapping the projection of the first trace segment 1301 and the first signal trace 112 is set as the first data signal line 1201, and the data signal line 120 connecting the data fan-out trace 130 overlapping the projection of the first trace segment 1302 and the shift register 111 is set as the second data signal line 1202. Furthermore, the first data signal line 1201 is set to be closer to the irregular border area NA2 in the X direction of the data signal line 120 arrangement direction. This ensures that in the data signal line 120 arrangement direction, the data signal line 120 connecting the data fan-out trace 130 overlapping the projection of the first trace segment 1301 and the shift register 111 is farther from the irregular border area NA2, while the data signal line 120 connecting the data fan-out trace 130 overlapping the projection of the first trace segment 1301 and the first signal trace 112 is relatively closer to the irregular border area NA2. In short, this configuration ensures that the data fan-out trace 130 overlapping with the first trace segment 1301 and the shift register 111, and the data fan-out trace 130 overlapping with the first signal trace 112, have similar lengths when connecting to the data signal line 120. This avoids impedance differences caused by significant differences in the lengths of the connecting traces for the two types of data fan-out traces 130, and thus ensures a more balanced data signal provided by the two types of data fan-out traces 130 to the corresponding data signal line 120, preventing uneven display issues.

[0078] Figure 12 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 13 yes Figure 12 The image shown is a partial enlarged view of the display panel. Figure 14 yes Figure 12 The diagram shown is a partial sectional view of the display panel. (Refer to...) Figures 12-14In other embodiments of the present invention, the display area AA may also include a plurality of touch electrodes 14, and the irregular frame area NA2 may also include a plurality of touch fan-out traces 140, which are electrically connected to the touch electrodes 14; the touch fan-out traces 140 and the data fan-out traces 130 are located in the same at least one film layer, and the projections of the data fan-out traces 130 and the touch fan-out traces 140 on the light-emitting surface of the display panel overlap with the projections of the shift register circuit 11 and the demultiplexing circuit 12 on the light-emitting surface of the display panel.

[0079] The touch fan-out trace 140 is responsible for transmitting touch signals, and it also needs to pass through the irregularly shaped bezel area NA2. It is understandable that due to the presence of the touch fan-out trace 140, the circuit-wiring layout of the irregularly shaped bezel area NA2 needs to be rationally designed to avoid an excessively large area. This embodiment addresses this by placing the data fan-out trace 130 and the touch fan-out trace 140 in a projection overlap with the shift register circuit 11 and the demultiplexing circuit 12. Essentially, this involves vertically stacking the two types of fan-out traces above the shift register circuit 11 and the demultiplexing circuit 12 to reduce the problem of an excessively large area of ​​the irregularly shaped bezel area NA2 caused by horizontal layout.

[0080] Figure 15 This is a partial structural cross-sectional view of another display panel provided in an embodiment of the present invention, compared with... Figure 14 and Figure 15 As can be seen, in the optional embodiments of the present invention, the left and right positions of the two fan-out lines, namely the data fan-out line 130 and the touch fan-out line 140, can be adjusted according to actual needs, and no further limitations are imposed here.

[0081] like Figure 13 and Figure 14 As shown, in an optional embodiment, the projection of the data fan-out trace 130 on the light-emitting surface of the display panel can overlap with the projection of the shift register circuit 11 on the light-emitting surface of the display panel; the projection of the touch fan-out trace 140 on the light-emitting surface of the display panel can overlap with the projection of the demultiplexing circuit 12 on the light-emitting surface of the display panel.

[0082] More specifically, such as Figure 14 and Figure 15 As shown, in a specific embodiment, the projection areas of the data fan-out traces 130 and touch fan-out traces 140 on the light-emitting surface of the display panel can be arranged on the third direction W, overlapping with the projection areas of the shift register circuit 11 and demultiplexing circuit 12 on the light-emitting surface of the display panel; wherein, the third direction W is the arrangement direction of the multiple data fan-out traces 130 and multiple touch fan-out traces 140.

[0083] The overlap of the projection area on the third direction W here means that the two sides of the projection area on the third direction W coincide. Therefore, by setting the two sides of the data fan-out trace 130 and the touch fan-out trace 140 on the third direction W to coincide with the two sides of the shift register circuit 11 and the demultiplexing circuit 12 on the third direction W, the space of the shift register circuit 11 and the demultiplexing circuit 12 on the third direction W is fully utilized. The data fan-out trace 130 and the touch fan-out trace 140 are placed in this area. On the one hand, as mentioned above, this can avoid the data fan-out trace 130 and the touch fan-out trace 140 occupying too much of the horizontal area of ​​the irregular frame area NA2. On the other hand, it can ensure that the data fan-out trace 130 and the touch fan-out trace 140 have sufficient horizontal wiring space. Setting both types of fan-out traces to have a relatively wide line width and line spacing can balance the impedance on the fan-out traces and avoid the problem of low impedance caused by the signal line being too narrow. At the same time, it can also avoid the problem of mutual interference caused by the signal lines being too close together.

[0084] Figure 16 This is a partial structural schematic diagram of another display panel provided in an embodiment of the present invention. Figure 17 yes Figure 16 The partial structural cross-sectional view of the display panel shown is for reference. Figure 16 and Figure 17 Specifically, the source drive circuit 12 includes multiple demultiplexers 121 and multiple second signal lines 122, with the second signal lines 122 located on the side of the demultiplexer 121 away from the display area AA.

[0085] The demultiplexer 121 includes a control terminal Ctrl, an input terminal IN, and at least two output terminals OUT. The control terminal Ctrl is connected to a second signal line 122, the input terminal IN is connected to a data fan-out line 130, and the output terminal OUT is connected to a data signal line 120.

[0086] The touch fan-out trace 140 and the second signal trace 122 are located on different film layers of the display panel, and a signal shielding layer 201 is provided between the film layers where the touch fan-out trace 140 and the second signal trace 122 are located.

[0087] The demultiplexer 121 is essentially a selector, which can be a transistor or a MOSFET. In this embodiment, the demultiplexer 121 has two output terminals OUT, i.e., connected to two data signal lines 120. This is only an example; those skilled in the art will understand that in actual applications, the demultiplexer 121 can be configured with three, four, or six output terminals to achieve source driving such as one-to-three, one-to-four, or one-to-six. No limitation is made here.

[0088] Similarly, continue to refer to Figure 17The display panel also includes a substrate 200, a first metal layer 210, a second metal layer 220, and a third metal layer 230. The first metal layer 210, the second metal layer 220, and the third metal layer 230 are sequentially distributed on one side of the substrate 200 in a direction perpendicular to the plane of the substrate 200 and away from the substrate 200. An interlayer insulating layer 202 is provided between adjacent layers of the first metal layer 210, the second metal layer 220, and the third metal layer 230. The touch fan-out trace 140 is located in the third metal layer 230, the second signal trace 122 is located in the first metal layer 210, and the signal shielding layer 201 is located in the second metal layer 220.

[0089] The principle here is the same as in the embodiment described above where a signal shielding layer 201 is provided between the data fan-out trace 130 and the first signal trace 112 in the shift register circuit 11. The signal shielding layer 201 can shield the touch signals transmitted on the touch fan-out trace 140 from interference by high-frequency signals such as the strobe signal in the second signal trace 112. This ensures the normal transmission of touch signals on the touch fan-out trace 140 and guarantees the accuracy of touch detection. Furthermore, the signal shielding layer 201 can also be disposed within the second metal layer 220, thereby avoiding the need to add a separate metal layer for the signal shielding layer 201. This simplifies the manufacturing process and fabrication procedures of the display panel, saving manufacturing costs while shielding the touch fan-out trace 140 from interference through the signal shielding layer 201.

[0090] Similarly, to achieve better shielding, as in the above embodiment, a fixed potential signal can be introduced into the signal shielding layer 201 between the touch fan-out trace 140 and the second signal trace 122.

[0091] Specifically, please refer to Figure 6 In one specific embodiment of the present invention, the first signal trace 112 includes a first-level signal line V1 and a second-level signal line V2, wherein the potential on the first-level signal line V1 is lower than the potential on the second-level signal line V2. The first-level signal line V1 or the second-level signal line V2 can be electrically connected to the signal shielding layer 201. The first-level signal line V1 can be understood as the low-level signal line VGL in the shift register circuit 11, and the second-level signal line V2 can be understood as the high-level signal line VGH in the shift register circuit 11. In this embodiment, the high-level signal or low-level signal in the shift register circuit 11 is essentially fed into the signal shielding layer 201 to stabilize the potential of the signal shielding layer 201.

[0092] Continue to refer to Figure 9 In another specific embodiment of the present invention, the non-display area NA further includes bonding pads 13 and fixed potential signal lines 150, wherein the bonding pads 13 are used to bond the driver chip IC.

[0093] One end of the fixed potential signal line 150 is electrically connected to the signal shielding layer 201, and the other end is electrically connected to the driver chip IC through the bonding pad 13; the driver chip IC is used to provide a fixed potential signal to the signal shielding layer 201 through the fixed potential signal line 150.

[0094] In the two embodiments described above, by introducing a fixed potential signal into the signal shielding layer 201, the signal shielding layer 201 can be made to have a stable potential, thereby shielding the electromagnetic interference generated by the high-frequency signal, so that the signal shielding layer 201 can effectively block the electromagnetic interference generated by the first signal trace 112 on the data fan-out trace 130.

[0095] Figure 18 and Figure 19 These are partial structural cross-sectional views of two more display panels provided in embodiments of the present invention, for reference. Figure 18 and Figure 19 The display panel further includes a substrate 200, a first metal layer 210, a second metal layer 220, and a third metal layer 230. In a direction perpendicular to the plane of the substrate 200 and away from the substrate 200, the first metal layer 210, the second metal layer 220, and the third metal layer 230 are sequentially distributed on one side of the substrate 200. An interlayer insulating layer 202 is provided between adjacent layers of the first metal layer 210, the second metal layer 220, and the third metal layer 230. In other embodiments of the present invention, at least a portion of the data fan-out traces 130 and at least a portion of the touch fan-out traces 140 may be located on the third metal layer 230.

[0096] Specifically, refer to Figure 18 The irregularly shaped bezel area NA2 also includes multiple second connection traces 123, which are located in the second metal layer 220. One end of each second connection trace 123 is electrically connected to a data fan-out trace 130 located in the third metal layer 230 via a second via 20202, and the other end is electrically connected to the demultiplexing circuit 12. The second via 20202 is located in the interlayer insulating layer 2020 between the second metal layer 220 and the third metal layer 230. Furthermore, the projection of the second via 20202 onto the light-emitting surface of the display panel is located between the projections of the shift register circuit 11 and the demultiplexing circuit 12 onto the light-emitting surface of the display panel. Figure 18 As shown, when the data fan-out trace 130 and the touch fan-out trace 140 are both disposed in the third metal layer 230, and the data fan-out trace 130 is disposed above the shift register circuit 11, in order to electrically connect the data fan-out trace 130 with the demultiplexing circuit 12, a via, namely the second via 20202, can be disposed between the shift register circuit 11 and the demultiplexing circuit 12, and a second connecting line 123 can be disposed in the second metal layer 220 to realize the connection between the data fan-out trace 130 and the demultiplexing circuit 12.

[0097] Continue to refer to Figure 19 In one specific embodiment, some data fan-out traces 130 may be located in the second metal layer 220, and some data fan-out traces 130 may be located in the third metal layer 230; and / or, some touch fan-out traces 140 may be located in the second metal layer 220, and some touch fan-out traces 140 may be located in the third metal layer 230. Figure 19 The example only illustrates the case where data fan-out traces 130 and touch fan-out traces 140 are simultaneously arranged in the second metal layer 220 and the third metal layer 230. Those skilled in the art can choose to arrange only data fan-out traces 130 in the second metal layer 220 and the third metal layer 230, or choose to arrange only touch fan-out traces 140 in the second metal layer 220 and the third metal layer 230, according to actual needs. No limitation is made here.

[0098] Figure 20 This is a partial structural cross-sectional view of another display panel provided in an embodiment of the present invention, with reference to... Figure 20 Furthermore, in another embodiment of the present invention, the optional data fan-out trace 130 may include a first data fan-out trace 131 and a second data fan-out trace 132, wherein the first data fan-out trace 131 is located in the second metal layer 220 and the second data fan-out trace 132 is located in the third metal layer 230.

[0099] The projection of the first data fan-out trace 131 onto the light-emitting surface of the display panel lies between the projections of the shift register circuit 11 and the demultiplexing circuit 12 onto the light-emitting surface of the display panel, and is located within the projection of the second data fan-out trace 132 onto the light-emitting surface of the display panel; and / or,

[0100] The touch fan-out trace 140 includes a first touch fan-out trace 141 and a second touch fan-out trace 142. The first touch fan-out trace 141 is located in the second metal layer 220, and the second touch fan-out trace 142 is located in the third metal layer 230.

[0101] The projection of the first touch fan-out trace 141 on the light-emitting surface of the display panel is located between the projections of the shift register circuit 11 and the demultiplexing circuit 12 on the light-emitting surface of the display panel, and is located within the projection of the second touch fan-out trace 142 on the light-emitting surface of the display panel.

[0102] Specifically, the first data fan-out trace 131 can be understood as the data fan-out trace 130 disposed on the second metal layer 220, and the first touch fan-out trace 141 can be understood as the touch fan-out trace 140 disposed on the second metal layer 220. Figure 19The difference between the data fan-out trace 130 and the touch fan-out trace 140 arranged in the second metal layer 220 is that, in this embodiment, the first data fan-out trace 131 is located between the shift register circuit 11 and the demultiplexing circuit 12, and does not overlap with the projection of the shift register circuit 11 and the demultiplexing circuit 12. Similarly, in this embodiment, the first touch fan-out trace 141 is also located between the shift register circuit 11 and the demultiplexing circuit 12, and does not overlap with the projection of the shift register circuit 11 and the demultiplexing circuit 12. It should be noted that in this embodiment, the data fan-out traces 130 and touch fan-out traces 140 are set on the second metal layer 220 and positioned between the shift register circuit 11 and the demultiplexing circuit 12. This is mainly applicable when there are too many data fan-out traces 130 or too many touch fan-out traces 140 in the irregular bezel area NA2, and the lateral width of the shift register circuit 11 and the demultiplexing circuit 12 is small, making it impossible to place all the data fan-out traces 130 and touch fan-out traces 140 on the third metal layer 230, with their projections located within the projections of the shift register circuit 11 and the demultiplexing circuit 12. In other words, when there are too many data fan-out traces 130 or too many touch fan-out traces 140 in the irregular bezel area NA2, causing them all to be placed on the same layer, the projection area of ​​the data fan-out traces 130 and touch fan-out traces 140 will be larger than the projection area of ​​the shift register circuit 11 and the demultiplexing circuit 12. Based on this, the excess data fan-out traces 130 or touch fan-out traces 140 that cannot be accommodated by the projection areas of the shift register circuit 11 and the demultiplexing circuit 12 are arranged in two metal layers, namely the second metal layer 220 and the third metal layer 230. This can minimize the projection area of ​​the excess data fan-out traces 130 and touch fan-out traces 140, that is, minimize the width of the irregular bezel area NA2, thereby facilitating the implementation of a narrow bezel design.

[0103] Similarly, Figure 20 The example only illustrates the case where both data fan-out traces 130 and touch fan-out traces 140 are simultaneously arranged on the second metal layer 220 and the third metal layer 230, i.e., there are too many data fan-out traces 130 and too many touch fan-out traces 140. For actual needs, when there are too many data fan-out traces 130 or too many touch fan-out traces 140, it is possible to arrange only data fan-out traces 130 on both the second metal layer 220 and the third metal layer 230, or only touch fan-out traces 140 on both the second metal layer 220 and the third metal layer 230. This is not a limitation.

[0104] Another point I'd like to add is, such as Figure 19 and Figure 20In the illustrated embodiment, since some data fan-out traces 130 and some touch fan-out traces 140 are disposed in the second metal layer 220, and as mentioned above, there will be signal lines in the second signal traces 122 that need to transmit pulse signals, in order to avoid capacitive coupling of the pulse signals in the second signal traces 122 to the data fan-out traces 130 and touch fan-out traces 140 located in the second metal layer 220, reference can be made to... Figure 10 and Figure 11 In the embodiment shown, the interlayer insulating layer 202 between the first metal layer 210 and the second metal layer 220 is thickened, or it is made of a material with a low dielectric constant, thereby reducing the coupling capacitance between the traces of the first metal layer 210 and the second metal layer 220 and avoiding interference between signals.

[0105] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 21 This is a schematic diagram of a display device provided in an embodiment of the present invention, with reference to... Figure 21 The display device includes the display panel 1 provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention has the corresponding beneficial effects of the display panel provided in the embodiments of the present invention, which will not be elaborated here. For example, the display device may be an electronic device such as an in-vehicle display device, such as an in-vehicle electronic rearview mirror, electronic instrument panel, central control screen, etc. The embodiments of the present invention do not limit this.

[0106] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area, the non-display area being interconnected with the display area; the display area includes multiple data signal lines and multiple scan signal lines, the data signal lines and the scan signal lines intersecting. The non-display area includes an irregularly shaped border area, the boundary line of which intersects with the display area and the extension lines of the data signal line and the scan signal line; the irregularly shaped border area includes a gate driving circuit area and a source driving circuit area, the source driving circuit area being located between the gate driving circuit area and the display area; The gate drive circuit region is provided with a shift register circuit, which is electrically connected to the scan signal line and is used to sequentially provide gate drive signals to multiple scan signal lines. The source drive circuit area is provided with a demultiplexing circuit, which is electrically connected to the data signal line and is used to provide data signals to multiple data signal lines in sequence. The irregularly shaped frame area also includes multiple data fan-out traces, which are electrically connected to at least two of the data signal lines through the demultiplexing circuit. The data fan-out traces are located in different film layers of the display panel, respectively, as are the shift register circuit and the demultiplexing circuit. The projection of the data fan-out traces on the light-emitting surface of the display panel overlaps with the projection of the shift register circuit and / or the demultiplexing circuit on the light-emitting surface of the display panel.

2. The display panel according to claim 1, characterized in that, The shift register circuit includes multiple shift registers and multiple first signal lines; the multiple shift registers are cascaded in sequence; the multiple first signal lines extend in parallel and are located on the side of the shift registers away from the display area; each shift register is electrically connected to at least one of the first signal lines. The projection of the data fan-out trace onto the light-emitting surface of the display panel overlaps with the projection of the shift register and / or the first signal trace onto the light-emitting surface of the display panel.

3. The display panel according to claim 2, characterized in that, The projection of the data fan-out trace on the light-emitting surface of the display panel overlaps with the projection of the first signal trace on the light-emitting surface of the display panel. The data fan-out trace and the first signal trace are located in different film layers of the display panel, and a signal shielding layer is provided between the film layers where the data fan-out trace and the first signal trace are located.

4. The display panel according to claim 3, characterized in that, The display panel further includes a substrate, a first metal layer, a second metal layer, and a third metal layer; the first metal layer, the second metal layer, and the third metal layer are sequentially distributed on one side of the substrate in a direction perpendicular to the plane of the substrate and away from the substrate; an interlayer insulating layer is disposed between adjacent layers of the first metal layer, the second metal layer, and the third metal layer. The data fan-out trace is located on the third metal layer, the first signal trace is located on the first metal layer, and the signal shielding layer is located on the second metal layer.

5. The display panel according to claim 4, characterized in that, The shift register circuit also includes multiple first connection traces, which are located in the second metal layer; One end of the first connection trace is electrically connected to the shift register, and the other end is electrically connected to the first signal trace through the first via. The first via is located in the interlayer insulating layer between the first metal layer and the second metal layer. The projection of the signal shielding layer onto the light-emitting surface of the display panel does not overlap with the projection of the first connecting trace onto the light-emitting surface of the display panel.

6. The display panel according to claim 2, characterized in that, The display panel further includes a substrate, a first metal layer, a second metal layer, and a third metal layer; the first metal layer, the second metal layer, and the third metal layer are sequentially distributed on one side of the substrate in a direction perpendicular to the plane of the substrate and away from the substrate; an interlayer insulating layer is provided between adjacent layers of the first metal layer, the second metal layer, and the third metal layer. The first signal trace is located on the first metal layer, and at least a portion of the data fan-out trace is located on the second metal layer.

7. The display panel according to claim 6, characterized in that, The interlayer insulation layer includes a first interlayer insulation layer and a second interlayer insulation layer, wherein the first interlayer insulation layer is located between the first metal layer and the second metal layer, and the second interlayer insulation layer is located between the second metal layer and the third metal layer; The thickness of the first interlayer insulation layer is greater than the thickness of the second interlayer insulation layer, and / or the dielectric constant of the first interlayer insulation layer is less than the dielectric constant of the second interlayer insulation layer.

8. The display panel according to claim 2, characterized in that, The data fan-out trace includes a first trace segment, the extension direction of which is parallel to the extension direction of the boundary line between the irregular frame area and the display area. The projection of the first segment of the data fan-out trace on the light-emitting surface of the display panel overlaps with the projection of the shift register on the light-emitting surface of the display panel; the projection of the first segment of the data fan-out trace on the light-emitting surface of the display panel overlaps with the projection of the first signal trace on the light-emitting surface of the display panel. The data signal lines include a first data signal line and a second data signal line. The data fan-out trace where the first trace segment overlaps with the projection of the first signal trace is electrically connected to the first data signal line through the demultiplexing circuit. The data fan-out trace where the first trace segment overlaps with the projection of the shift register is electrically connected to the second data signal line through the demultiplexing circuit. In a first direction, the first data signal line is located on the side of the second data signal line near the irregular border area, and the first direction is the arrangement direction of the multiple data signal lines.

9. The display panel according to claim 1, characterized in that, The display area also includes multiple touch electrodes, and the irregularly shaped frame area also includes multiple touch fan-out traces, which are electrically connected to the touch electrodes. The touch fan-out trace and the data fan-out trace are located in the same at least one film layer, and the projections of the data fan-out trace and the touch fan-out trace on the light-emitting surface of the display panel overlap with the projections of the shift register circuit and the demultiplexing circuit on the light-emitting surface of the display panel.

10. The display panel according to claim 9, characterized in that, The projection of the data fan-out trace on the light-emitting surface of the display panel overlaps with the projection of the shift register circuit on the light-emitting surface of the display panel; the projection of the touch fan-out trace on the light-emitting surface of the display panel overlaps with the projection of the demultiplexing circuit on the light-emitting surface of the display panel.

11. The display panel according to claim 10, characterized in that, The source drive circuit includes multiple demultiplexers and multiple second signal traces, wherein the second signal traces are located on the side of the demultiplexer away from the display area; The demultiplexer includes a control terminal, an input terminal, and at least two output terminals. The control terminal is connected to a second signal trace, the input terminal is connected to a data fan-out trace, and the output terminal is connected to a data signal line. The touch fan-out trace and the second signal trace are located in different film layers of the display panel, and a signal shielding layer is provided between the film layers where the touch fan-out trace and the second signal trace are located.

12. The display panel according to claim 11, characterized in that, The display panel further includes a substrate, a first metal layer, a second metal layer, and a third metal layer; the first metal layer, the second metal layer, and the third metal layer are sequentially distributed on one side of the substrate in a direction perpendicular to the plane of the substrate and away from the substrate; an interlayer insulating layer is disposed between adjacent layers of the first metal layer, the second metal layer, and the third metal layer. The touch fan-out trace is located on the third metal layer, the second signal trace is located on the first metal layer, and the signal shielding layer is located on the second metal layer.

13. The display panel according to claim 9, characterized in that, The display panel further includes a substrate, a first metal layer, a second metal layer, and a third metal layer; the first metal layer, the second metal layer, and the third metal layer are sequentially distributed on one side of the substrate in a direction perpendicular to the plane of the substrate and away from the substrate; an interlayer insulating layer is provided between adjacent layers of the first metal layer, the second metal layer, and the third metal layer. At least a portion of the data fan-out traces and at least a portion of the touch fan-out traces are located in the third metal layer.

14. The display panel according to claim 13, characterized in that, The irregularly shaped frame area also includes multiple second connection traces, which are located in the second metal layer; One end of the second connection trace is electrically connected to the data fan-out trace located on the third metal layer through the second via, and the other end is electrically connected to the demultiplexing circuit. The second via is located in the interlayer insulating layer between the second metal layer and the third metal layer.

15. The display panel according to claim 14, characterized in that, The projection of the second via on the light-emitting surface of the display panel is located between the projections of the shift register circuit and the demultiplexing circuit on the light-emitting surface of the display panel.

16. The display panel according to claim 13, characterized in that, Some of the data fan-out traces are located in the second metal layer, and some of the data fan-out traces are located in the third metal layer; and / or, some of the touch fan-out traces are located in the second metal layer, and some of the touch fan-out traces are located in the third metal layer.

17. The display panel according to claim 13, characterized in that, The data fan-out trace includes a first data fan-out trace and a second data fan-out trace, wherein the first data fan-out trace is located in the second metal layer and the second data fan-out trace is located in the third metal layer. The projection of the first data fan-out trace on the light-emitting surface of the display panel is located between the projections of the shift register circuit and the demultiplexing circuit on the light-emitting surface of the display panel, and is located within the projection of the second data fan-out trace on the light-emitting surface of the display panel; and / or, The touch fan-out routing includes a first touch fan-out routing and a second touch fan-out routing, wherein the first touch fan-out routing is located in the second metal layer and the second touch fan-out routing is located in the third metal layer; The projection of the first touch fan-out trace on the light-emitting surface of the display panel is located between the projections of the shift register circuit and the demultiplexing circuit on the light-emitting surface of the display panel, and is located within the projection of the second touch fan-out trace on the light-emitting surface of the display panel.

18. The display panel according to claim 9, characterized in that, In the third direction, the projection areas of the data fan-out traces and the touch fan-out traces on the light-emitting surface of the display panel overlap with the projection areas of the shift register circuit and the demultiplexing circuit on the light-emitting surface of the display panel; wherein, the third direction is the arrangement direction of the multiple data fan-out traces and the multiple touch fan-out traces.

19. The display panel according to claim 3 or 11, characterized in that, The signal shielding layer receives a fixed potential signal.

20. The display panel according to claim 19, characterized in that, The shift register circuit includes multiple shift registers and multiple first signal lines; the multiple shift registers are cascaded in sequence; the multiple first signal lines extend in parallel and are located on the side of the shift registers away from the display area; each shift register is electrically connected to at least one of the first signal lines. The first signal trace includes a first-level signal line and a second-level signal line, wherein the potential on the first-level signal line is lower than the potential on the second-level signal line; The first level signal line or the second level signal line is electrically connected to the signal shielding layer.

21. The display panel according to claim 19, characterized in that, The non-display area also includes bonding pads and fixed potential signal lines, wherein the bonding pads are used to bond the driver chip; One end of the fixed potential signal line is electrically connected to the signal shielding layer, and the other end is electrically connected to the driver chip through the bonding pad; the driver chip is used to provide the fixed potential signal to the signal shielding layer through the fixed potential signal line.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1-21.

Images