Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate structure, wherein the substrate structure comprises a mark area, and the mark area comprises a silicon substrate and a first dielectric layer on the silicon substrate; forming a first opening in the first dielectric layer and the silicon substrate; forming a first mark structure on a part of the bottom of the first opening, and the bottom surface of the first mark structure is coplanar with the bottom surface of the silicon substrate; forming a second dielectric layer in the first opening, and the surface of the second dielectric layer is flush with the surface of the first dielectric layer; and forming a second mark structure in the second dielectric layer above the first mark structure or on the second dielectric layer, and the orthographic projection of the second mark structure falls on the first mark structure. The semiconductor structure and the forming method thereof can improve the recognition rate of the mark structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] When performing the wafer acceptable test (WAT), the clarity of the marking structure is required to be very high. Otherwise, it will cause difficulties in machine recognition, leading to alignment failure and preventing the WAT test from being carried out normally.

[0003] The main reasons for the low clarity of the marking structure include: low light transmittance of the marking structure; and simple graphic design and small size of the marking structure, making it difficult for the machine to identify. Summary of the Invention

[0004] The technical problem this application aims to solve is to improve the recognition rate of marker structures.

[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor structure, comprising: providing a substrate structure, the substrate structure including a marking region, the marking region including a silicon substrate, the silicon substrate including a first dielectric layer; forming a first opening in the first dielectric layer and the silicon substrate; forming a first marking structure at the bottom of a portion of the first opening, wherein the bottom surface of the first marking structure is coplanar with the bottom surface of the silicon substrate; forming a second dielectric layer in the first opening, wherein the surfaces of the second dielectric layer and the first dielectric layer are flush; forming a second marking structure in or on the second dielectric layer above the first marking structure, wherein the orthographic projection of the second marking structure falls on the first marking structure.

[0006] In some embodiments, the first marking structure and / or the second marking structure includes a cross-shaped structure and a ring structure surrounding the cross-shaped structure, wherein the cross-shaped structure and the ring structure are continuously distributed structures or dot matrix structures.

[0007] In some embodiments, the cross-shaped structure and the ring structure are continuously distributed, and the width of the cross-shaped structure and the ring structure is 6μm to 20μm. The cross-shaped structure and the ring structure may be connected or not connected.

[0008] In some embodiments, the cross-shaped structure and the ring structure are lattice structures and include several unconnected substructures, and the key dimensions of the substructures may be the same or different.

[0009] In some embodiments, the first marker structure includes a first metal layer.

[0010] In some embodiments, the material of the first metal layer includes aluminum, and the thickness of the first metal layer is 1000 nm to 4000 nm.

[0011] In some embodiments, the second marking structure includes a titanium layer, a first titanium nitride layer, a second metal layer, and a second titanium nitride layer stacked sequentially.

[0012] In some embodiments, the material of the second metal layer includes aluminum, and the thickness of the second metal layer is 200 nm to 4000 nm.

[0013] In some embodiments, the method of forming the first marker structure includes: forming a first marker structure material layer on the first dielectric layer and on the sidewalls and bottom of the first opening; etching the first marker structure material layer on the first dielectric layer, on the sidewalls and part of the bottom of the first opening to form the first marker structure.

[0014] In some embodiments, the second marking structure is located in the second dielectric layer, and the method of forming the second marking structure includes: forming a second opening in the second dielectric layer; forming a second marking structure material layer on the sidewalls and bottom of the first dielectric layer, the second dielectric layer, and the second opening; forming a third dielectric layer on the surface of the second marking structure material layer; and grinding the third dielectric layer and the second marking structure material layer so that the second marking structure material layer is flush with the surface of the second dielectric layer to form the second marking structure.

[0015] In some embodiments, the material of the first dielectric layer includes a high-K material with a dielectric constant of less than 2.5, and the materials of the second dielectric layer and the third dielectric layer include silicon oxide.

[0016] In some embodiments, the second marker structure is located on the second dielectric layer, and the method of forming the second marker structure includes: forming a second marker structure material layer on the first dielectric layer and the second dielectric layer; etching the second marker structure material layer on the first dielectric layer and a portion of the second dielectric layer to form the second marker structure.

[0017] In some embodiments, the substrate structure further includes a logic wafer and a pixel wafer bonded to each other, wherein the silicon substrate is located on the pixel wafer, the first dielectric layer is located on the silicon substrate, and the first marker structure is located on the pixel wafer.

[0018] This application also provides a semiconductor structure, comprising: a substrate structure including a marking region, the marking region including a silicon substrate, the silicon substrate including a first dielectric layer; a second dielectric layer located in the silicon substrate and the first dielectric layer, and the surfaces of the second dielectric layer and the first dielectric layer being flush; a first marking structure located in the second dielectric layer, and the bottom surface of the first marking structure being coplanar with the bottom surface of the silicon substrate; and a second marking structure located in or on the second dielectric layer above the first marking structure, and the orthographic projection of the second marking structure falling on the first marking structure.

[0019] In some embodiments, the first marking structure and / or the second marking structure includes a cross-shaped structure and a ring structure surrounding the cross-shaped structure, wherein the cross-shaped structure and the ring structure are continuously distributed structures or lattice structures.

[0020] In some embodiments, the cross-shaped structure and the ring structure are continuously distributed, and the width of the cross-shaped structure and the ring structure is 6μm to 20μm. The cross-shaped structure and the ring structure may be connected or not connected.

[0021] In some embodiments, the cross-shaped structure and the ring structure are lattice structures and include several unconnected substructures, and the key dimensions of the substructures may be the same or different.

[0022] In some embodiments, the first marker structure includes a first metal layer.

[0023] In some embodiments, the material of the first metal layer includes aluminum, and the thickness of the first metal layer is 1000 nm to 4000 nm.

[0024] In some embodiments, the second marking structure includes a titanium layer, a first titanium nitride layer, a second metal layer, and a second titanium nitride layer stacked sequentially.

[0025] In some embodiments, the material of the second metal layer includes aluminum, and the thickness of the second metal layer is 200 nm to 4000 nm.

[0026] In some embodiments, the substrate structure further includes a logic wafer and a pixel wafer bonded to each other, wherein the silicon substrate is located on the pixel wafer, the first dielectric layer is located on the silicon substrate, and the first marker structure is located on the pixel wafer.

[0027] The semiconductor structure and its formation method of this application improve the process flow, transforming the original single and unclear alignment mark into a mark structure combining a first mark structure and a second mark structure, thereby greatly enhancing the clarity of the mark.

[0028] Furthermore, increasing the size of the marker structure enlarges the recognition process window. Using a dot-matrix marker structure significantly enhances graphic contrast, thereby improving the success rate of recognition. Attached Figure Description

[0029] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0030] Figures 1 to 5 This is a schematic diagram of the steps in a method for forming alignment marks;

[0031] Figure 6 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of this application;

[0032] Figures 7 to 22 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0033] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0034] To improve alignment accuracy, the clarity of the alignment mark structure in wafer tamper testing (WAT) requires high precision. Currently, BSI lot WAT testing typically uses locking corners (marks located at the four vertices of the shot) as alignment marks for positioning, but alignment failures frequently occur. Optical microscopy studies have revealed that this problem is caused by the low clarity of the alignment marks, making it difficult for the equipment to recognize them.

[0035] Further research into the clarity of the alignment marks revealed two main reasons for the low clarity: first, the films that make up the alignment marks mostly have low light transmittance, and even if there are films with good recognition, their thickness is very small; second, the graphics of the alignment marks are limited by size requirements, so their design is relatively simple and small, making them difficult for the machine to recognize.

[0036] The following is combined first Figures 1 to 5 A method for forming alignment marks is introduced, wherein the alignment marks are formed in the marking region of a bonded wafer, and Figure 1 and Figure 5 Only a partial cross-sectional view of the marked area on the bonding wafer is shown.

[0037] refer to Figure 1 The bonding wafer includes a logic wafer 10 and a pixel wafer 20. The surface of the pixel wafer 20 has a silicon substrate 30, which has been thinned.

[0038] refer to Figure 2 A high-K dielectric layer 40 is deposited on the surface of the silicon substrate 30 in the marking region. In the actual formation process, before depositing the high-K dielectric layer 40, a DTI etching process and a pad etching process are required in the device region of the bonding wafer, while the structure of the marking region of the bonding wafer is not affected by these two etching processes.

[0039] refer to Figure 3 Because an aluminum pad needs to be formed in the device region, an aluminum layer needs to be deposited in the device region. Simultaneously, an aluminum layer 50 is also formed on the surface of the high-K dielectric layer 40 in the marking region. (See reference) Figure 4 When removing excess aluminum layer in the device area, the aluminum layer 50 in the marking area is also removed simultaneously.

[0040] refer to Figure 5 Alignment marks 60 are formed on a portion of the surface of the high-K dielectric layer 40 in the marking area. The alignment marks 60 include a titanium layer, a first titanium nitride layer, an aluminum layer, and a second titanium nitride layer. The titanium layer, the first titanium nitride layer, and the second titanium nitride layer have poor light transmittance, while the aluminum layer has slightly better light transmittance, but its thickness is very thin, only about 2000 angstroms. Simultaneously, the width of the alignment marks 60 is only 3 μm. Therefore, the alignment marks 60 are generally difficult for the machine to identify. Furthermore, the material of the alignment marks 60 cannot be replaced due to process limitations throughout the manufacturing process; improvements can only be made by adjusting the process.

[0041] Based on this, the technical solution of this application aims to improve the recognition rate of alignment marks by adjusting the process sequence and film layer combination to increase the light transmittance of the mark position, and further by adjusting the size and pattern of the mark to improve the success rate of mark pattern recognition and increase the process window during mark alignment.

[0042] refer to Figure 6 This application provides a method for forming a semiconductor structure, including:

[0043] Step S1: Provide a substrate structure, the substrate structure including a marking region, the marking region including a silicon substrate, and the silicon substrate including a first dielectric layer;

[0044] Step S2: Form a first opening in the first dielectric layer and the silicon substrate;

[0045] Step S3: A first marking structure is formed at the bottom of the portion of the first opening, and the bottom surface of the first marking structure is coplanar with the bottom surface of the silicon substrate;

[0046] Step S4: A second dielectric layer is formed in the first opening, and the surfaces of the second dielectric layer and the first dielectric layer are flush.

[0047] Step S5: A second marker structure is formed in or on the second dielectric layer above the first marker structure, and the orthographic projection of the second marker structure falls on the first marker structure.

[0048] refer to Figure 7 A substrate structure is provided, comprising a device region and a marking region, wherein the marking region is used to form a marking structure, and various devices are designed in the device region according to actual conditions. Since the purpose of this embodiment is to form a marking structure, only the structure of the marking region is shown in the figures. The substrate structure of the device region and the marking region may include mutually bonded logic wafers 100 and pixel wafers 200, and a silicon substrate 300 located on the pixel wafer 200, the silicon substrate 300 being thinned. A first dielectric layer 400 is included on the marking region. Specifically, the first dielectric layer 400 may be located on the silicon substrate 300. Simultaneously, the first dielectric layer 400 may also be located on the silicon substrate 300 of the device region. The material of the first dielectric layer 400 may include a high-K material.

[0049] refer to Figure 8 A first opening 500 is formed in the first dielectric layer 400 and the substrate structure in the marking area. The formation process of the first opening 500 and the etching process of the device area pad can be performed in the same step. Specifically, the first opening 500 can be located in the first dielectric layer 400 and the silicon substrate 300, that is, the bottom of the first opening 500 is the pixel wafer 200. The formation process of the first opening 500 can be a photolithography and etching process.

[0050] Next, a first marking structure is formed at the bottom of a portion of the first opening 500. (See reference) Figure 9A first marking structure material layer 610 is formed on the first dielectric layer 400 and on the sidewalls and bottom of the first opening 500. The first marking structure material layer 610 can be formed in the same process as the pad material layer of the device region. The material of the first marking structure material layer 610 may include a first metal, which may include aluminum. The thickness of the first marking structure material layer 610 located at the bottom of the first opening 500 can be 1000 nm to 4000 nm.

[0051] refer to Figure 10 The first marking structure material layer 610 on the first dielectric layer 400, the sidewalls of the first opening 500, and part of the bottom are etched to form the first marking structure 600. The bottom surface of the first marking structure 600 is coplanar with the bottom surface of the silicon substrate 300. The etching process for forming the first marking structure 600 can be performed in the same etching process as the etching process for removing excess pad material layers in the device region. The formed first marking structure 600 can be located on the pixel wafer 200. The first marking structure 600 includes a first metal layer, the material of which includes aluminum, and the thickness of the first metal layer is 1000 nm to 4000 nm.

[0052] Figure 11 This is a schematic diagram of the planar structure of the first marker structure 600, as described above. Figures 7 to 10 And the following Figures 12 to 17 All are in Figure 11 A cross-sectional view at position AA. In this embodiment, the first marking structure 600 includes a cross-shaped structure 611 and an annular structure 612 surrounding the cross-shaped structure 611, wherein the cross-shaped structure 611 and the annular structure 612 are continuously distributed. The width W1 of the cross-shaped structure 611 and the annular structure 612 can be 6μm to 20μm. The cross-shaped structure 611 and the annular structure 612 may or may not be connected.

[0053] In other embodiments, the cross-shaped structure 611 and the ring structure 612 may also be a lattice structure, which will be described in detail later.

[0054] refer to Figure 12 A second dielectric layer 700 is formed in the first opening 500, and the surface of the second dielectric layer 700 is flush with that of the first dielectric layer 400. The material of the second dielectric layer 700 may include silicon oxide. Then, a second marking structure is formed over the first marking structure 600, which may be located in or on the second dielectric layer 700.

[0055] refer to Figure 13First, the scheme in which the second marking structure is located in the second dielectric layer 700 will be described. The method of forming the second marking structure includes: forming a second opening in the second dielectric layer 700, and forming a second marking structure material layer 810 on the first dielectric layer 400, the second dielectric layer 700, and the sidewalls and bottom of the second opening. The second marking structure material layer 810 is a stacked structure, specifically including a titanium material layer, a first titanium nitride material layer, a second metal material layer, and a second titanium nitride material layer stacked sequentially. Then, a third dielectric layer 820 is formed on the surface of the second marking structure material layer 810. The material of the third dielectric layer 820 may include silicon oxide.

[0056] refer to Figure 14 The third dielectric layer 820 and the second marking structure material layer 810 are ground using a chemical mechanical polishing process, making the second marking structure material layer 810 flush with the surface of the second dielectric layer 700, thus forming the second marking structure 800. The orthographic projection of the second marking structure 800 can fall on the first marking structure 600. The second marking structure 800 includes a titanium layer, a first titanium nitride layer, a second metal layer, and a second titanium nitride layer stacked sequentially. The material of the second metal layer can include aluminum, and the thickness of the second metal layer can be 200 nm to 4000 nm. The thickness of the titanium layer can be 6 nm to 30 nm. The thickness of the first titanium nitride layer can be 20 nm to 100 nm. The thickness of the second titanium nitride layer can be 10 nm to 100 nm. The second marking structure 800 can also be a combination of a cross-shaped structure and a ring structure, similar to the first marking structure 600, and the relevant dimensions of the second marking structure 800 can also be referenced to the first marking structure 600.

[0057] refer to Figure 15 After forming the second marker structure 800, the method further includes forming a fourth dielectric layer 900 on the surfaces of the first dielectric layer 400, the second dielectric layer 700, and the second marker structure 800.

[0058] refer to Figure 16 When the second marker structure is located on the second dielectric layer 700, the method for forming the second marker structure includes: forming a second marker structure material layer on the first dielectric layer 400 and the second dielectric layer 700; etching the second marker structure material layer on the first dielectric layer 400 and a portion of the second dielectric layer 700 to form the second marker structure 800. The structure and material of the second marker structure 800 are as described above.

[0059] refer to Figure 17A fourth dielectric layer 900 is formed on the surface of the first dielectric layer 400, the second dielectric layer 700, and the surface and sidewalls of the second marking structure 800.

[0060] Figure 18 and Figure 19 This is a schematic diagram of the planar structure when the cross-shaped structure 611 and the ring structure 612 of the first marking structure 600 are lattice structures. Figures 20 to 22 for Figure 18 A sectional view at position BB in the middle. (See image below.) Figure 18 As shown and Figure 19 As shown, both the cross-shaped structure 611 and the ring structure 612 include several unconnected substructures, and the key dimensions of the substructures may be the same or different. When the dimensions are different, the graphic contrast can be further enhanced, thereby improving the success rate of recognition. In some embodiments, the length of the substructure can be 2μm to 20μm, and the width can be 1μm to 4μm.

[0061] refer to Figure 20 and Figure 21 After forming the first marker structure 600 with a lattice structure, a second marker structure 800 with a lattice structure is formed on top of the first marker structure 600. The formation process of the first marker structure 600 and the second marker structure 800 is similar to that of the continuously distributed structure, except that the pattern of the mask is changed during etching. Then, a fourth dielectric layer 900 is formed on the surface of the first dielectric layer 400, the second dielectric layer 700, and the second marker structure 800.

[0062] refer to Figure 22 The second marker structure 800 of the dot matrix structure can also be located on the second dielectric layer 700. Correspondingly, the fourth dielectric layer 900 is located on the surface of the first dielectric layer 400, the second dielectric layer 700, and the surface and sidewalls of the second marker structure 800.

[0063] Combination Figure 15 and Figure 17This application also provides a semiconductor structure, including: a substrate structure, the substrate structure including a marking region, the marking region including a silicon substrate 300, the silicon substrate 300 including a first dielectric layer 400; a second dielectric layer 700 located in the silicon substrate 300 and the first dielectric layer 400, and the surfaces of the second dielectric layer 700 and the first dielectric layer 400 are flush; a first marking structure 600 located in the second dielectric layer 700, and the bottom surface of the first marking structure 600 is coplanar with the bottom surface of the silicon substrate 300; a second marking structure 800 located in the second dielectric layer 700 above the first marking structure 600 or on the second dielectric layer 700, and the orthographic projection of the second marking structure 800 falls on the first marking structure 600.

[0064] The substrate structure further includes a logic wafer 100 and a pixel wafer 200 bonded to each other, wherein a silicon substrate 300 is located on the pixel wafer 200, a first dielectric layer 400 is located on the silicon substrate 300, and a first marking structure 600 is located on the pixel wafer 200.

[0065] Combination Figure 11 , Figure 18 and Figure 19 The first marking structure 600 includes a cross-shaped structure 611 and an annular structure 612 surrounding the cross-shaped structure 611. The cross-shaped structure 611 and the annular structure 612 are either continuously distributed or lattice-like structures. When the cross-shaped structure and the annular structure are continuously distributed, the width of the cross-shaped structure 611 and the annular structure 612 is 6μm to 20μm. The cross-shaped structure 611 and the annular structure 612 may or may not be connected. When the cross-shaped structure 611 and the annular structure 612 are lattice-like structures, they include several unconnected substructures, and the key dimensions of the substructures may be the same or different. The shape and size of the second marking structure 800 may also refer to the first marking structure 600.

[0066] The first marking structure 600 includes a first metal layer. The material of the first metal layer includes aluminum, and the thickness of the first metal layer is 1000 nm to 4000 nm. The second marking structure 800 includes a titanium layer, a first titanium nitride layer, a second metal layer, and a second titanium nitride layer stacked sequentially. The material of the second metal layer includes aluminum, and the thickness of the second metal layer is 200 nm to 4000 nm.

[0067] The semiconductor structure in this embodiment consists of a single BMG (Backside Metal) marker structure. Through process adjustments, a marker structure combining a first marker structure and a second marker structure is formed. This increases the thickness of the film layers (first metal layer and second metal layer) with better light transmittance. For example, it can be increased from the original 200nm AL to 200nm+1450nm AL, which greatly enhances the clarity of the marker structure. At the same time, it also increases the size of the marker structure, further expanding the process window for marker structure recognition.

[0068] Furthermore, changing the continuously distributed marker structure into a dot matrix structure can greatly enhance the graphic contrast, thereby increasing the success rate of marker recognition during WAT testing.

[0069] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0070] It should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" indicates the absence of intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0071] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0072] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate structure is provided, the substrate structure including a marking region, the marking region including a silicon substrate, the silicon substrate including a first dielectric layer; A first opening is formed in the first dielectric layer and the silicon substrate; A first marking structure is formed at the bottom of the portion of the first opening, and the bottom surface of the first marking structure is coplanar with the bottom surface of the silicon substrate; A second dielectric layer is formed in the first opening, and the surfaces of the second dielectric layer and the first dielectric layer are flush. A second marker structure is formed in or on the second dielectric layer above the first marker structure, and the orthographic projection of the second marker structure falls on the first marker structure.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The first marking structure and / or the second marking structure includes a cross-shaped structure and a ring structure surrounding the cross-shaped structure, wherein the cross-shaped structure and the ring structure are continuously distributed or are lattice structures.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The cross-shaped structure and the ring structure are continuously distributed, and the width of the cross-shaped structure and the ring structure is 6μm to 20μm. The cross-shaped structure and the ring structure may be connected or not connected.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, The cross-shaped structure and the ring structure are lattice structures, and include several unconnected substructures, with the key dimensions of the substructures being the same or different.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The first marking structure includes a first metal layer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The material of the first metal layer includes aluminum, and the thickness of the first metal layer is 1000nm to 4000nm.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, The second marking structure includes a titanium layer, a first titanium nitride layer, a second metal layer, and a second titanium nitride layer stacked sequentially.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The material of the second metal layer includes aluminum, and the thickness of the second metal layer is 200nm to 4000nm.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The method for forming the first marker structure includes: A first marking structure material layer is formed on the first dielectric layer and on the sidewalls and bottom of the first opening; The first marking structure material layer on the first dielectric layer, the sidewall of the first opening, and part of the bottom is etched to form the first marking structure.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The second marker structure is located in the second dielectric layer, and the method for forming the second marker structure includes: A second opening is formed in the second dielectric layer, and a second marking structure material layer is formed on the sidewalls and bottom of the first dielectric layer, the second dielectric layer, and the second opening; A third dielectric layer is formed on the surface of the second marker structure material layer; The third dielectric layer and the second marking structure material layer are ground until the surface of the second marking structure material layer is flush with the surface of the second dielectric layer, thus forming the second marking structure.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The first dielectric layer is made of a high-K material with a dielectric constant of less than 2.5, and the second and third dielectric layers are made of silicon oxide.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, The second marker structure is located on the second dielectric layer, and the method for forming the second marker structure includes: A second marker structure material layer is formed on the first dielectric layer and the second dielectric layer; The second marker structure material layer on the first dielectric layer and a portion of the second dielectric layer is etched to form the second marker structure.

13. The method for forming a semiconductor structure according to claim 1, characterized in that, The substrate structure further includes a logic wafer and a pixel wafer bonded to each other, wherein the silicon substrate is located on the pixel wafer, the first dielectric layer is located on the silicon substrate, and the first marker structure is located on the pixel wafer.

14. A semiconductor structure, characterized in that, include: A substrate structure, the substrate structure including a marking region, the marking region including a silicon substrate, the silicon substrate including a first dielectric layer; A second dielectric layer is located between the silicon substrate and the first dielectric layer, and the surfaces of the second dielectric layer and the first dielectric layer are flush. A first marking structure is located in the second dielectric layer, and the bottom surface of the first marking structure is coplanar with the bottom surface of the silicon substrate; The second marker structure is located in or on the second dielectric layer above the first marker structure, and the orthographic projection of the second marker structure falls on the first marker structure.

15. The semiconductor structure according to claim 14, characterized in that, The first marking structure and / or the second marking structure includes a cross-shaped structure and a ring structure surrounding the cross-shaped structure, wherein the cross-shaped structure and the ring structure are continuously distributed structures or dot matrix structures.

16. The semiconductor structure according to claim 15, characterized in that, The cross-shaped structure and the ring structure are continuously distributed, and the width of the cross-shaped structure and the ring structure is 6μm to 20μm. The cross-shaped structure and the ring structure may or may not be connected.

17. The semiconductor structure according to claim 15, characterized in that, The cross-shaped structure and the ring structure are lattice structures, and include several unconnected substructures, with the key dimensions of the substructures being the same or different.

18. The semiconductor structure according to claim 14, characterized in that, The first marking structure includes a first metal layer.

19. The semiconductor structure according to claim 18, characterized in that, The material of the first metal layer includes aluminum, and the thickness of the first metal layer is 1000nm to 4000nm.

20. The semiconductor structure according to claim 14, characterized in that, The second marking structure includes a titanium layer, a first titanium nitride layer, a second metal layer, and a second titanium nitride layer stacked sequentially.

21. The semiconductor structure according to claim 20, characterized in that, The material of the second metal layer includes aluminum, and the thickness of the second metal layer is 200nm to 4000nm.

22. The semiconductor structure according to claim 14, characterized in that, The substrate structure further includes a logic wafer and a pixel wafer bonded to each other, wherein the silicon substrate is located on the pixel wafer, the first dielectric layer is located on the silicon substrate, and the first marker structure is located on the pixel wafer.

Images