Semiconductor structure and method of forming the same
By doping ions into the isolation material layer to generate compressive stress, the problems of easy bending and bridging of the fins are solved, thus improving the electrical performance of the semiconductor structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2020-09-30
- Publication Date
- 2026-06-02
AI Technical Summary
In semiconductor manufacturing, as the channel length of a device shortens, the gate structure's control over the channel deteriorates, leading to an increase in short-channel effects, making the fins prone to bending and bridging, and affecting the electrical performance of the semiconductor structure.
By doping ions into the isolation material layer, compressive stress is generated, causing the chemical bonds in the isolation material layer to break, thereby causing the target pattern to bend in the opposite direction, reducing the risk of fin bridging and improving electrical performance.
By controlling the morphological quality of the fins, the risk of bridging between adjacent fins is reduced, thereby improving the electrical performance of the semiconductor structure.
Smart Images
Figure CN114334826B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.
[0003] Therefore, to reduce the impact of short-channel effects, semiconductor processes have gradually transitioned from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least both sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. Furthermore, FinFETs have better compatibility with existing integrated circuit manufacturing processes compared to other devices.
[0004] The fins are slender and ultra-thin bodies. During the formation of the semiconductor structure, the fins are prone to bending, and the formation quality of the fins is crucial to the performance of the semiconductor structure. Summary of the Invention
[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the semiconductor structure.
[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and a target pattern located on the substrate; forming an isolation material layer covering the substrate and the target pattern, the top of the isolation material layer being higher than the top surface of the target pattern; and doping the isolation material layer with ions to generate stress in the isolation material layer.
[0007] Optionally, the method for forming the semiconductor structure further includes: after doping the isolation material layer with ions, annealing the isolation material layer.
[0008] Optionally, in the step of doping the isolation material layer with ions, the doping ions may include He, Ne, Kr, or Ar.
[0009] Optionally, ion implantation is used to dope the isolation material layer with ions.
[0010] Optionally, the process temperature for doping the isolation material layer with ions is 300°C to 600°C.
[0011] Optionally, in the step of providing the substrate, the substrate includes a first region and a second region, the target pattern located in the first region is designated as the first target pattern, the target pattern located in the second region is designated as the second target pattern, and the height of the second target pattern is greater than the height of the first target pattern; the step of doping the isolation material layer with ions includes: forming a first mask layer covering the first region and exposing the second region; doping the isolation material layer exposed by the first mask layer with ions using a first doping process; forming a second mask layer covering the second region and exposing the first region; and doping the isolation material layer exposed by the second mask layer with ions using a second doping process, wherein the doping dose in the second doping process is less than the doping dose in the first doping process.
[0012] Optionally, the process temperature in the first doping process is higher than the process temperature in the second doping process; the doping energy in the first doping process is higher than the doping energy in the second doping process.
[0013] Optionally, the first doping process includes an ion implantation process, and the process parameters of the first doping process include: a process temperature of 400°C to 600°C, an implantation energy of 2 KeV to 30 KeV, and a doping dose of 1E15 atoms per square centimeter to 1E17 atoms per square centimeter.
[0014] Optionally, the second doping process includes an ion implantation process, and the process parameters of the second doping process include: a process temperature of 300°C to 600°C, an implantation energy of 0.5 KeV to 20 KeV, and a doping dose of 1E14 atoms per square centimeter to 1E17 atoms per square centimeter.
[0015] Optionally, a layer of insulating material covering the substrate and the target pattern may be formed using a flowable chemical vapor deposition process, a spin-coating dielectric process, or a high aspect ratio process.
[0016] Optionally, the material of the insulating material layer includes flowing silicon dioxide, spin-coated glass, and chemical vapor deposition oxide.
[0017] Optionally, the process parameters for annealing the insulating material layer include an annealing temperature of 500°C to 700°C.
[0018] Optionally, the method for forming the semiconductor structure further includes: after providing the substrate and before forming the isolation material layer, forming a conformal protective layer covering the target pattern.
[0019] Optionally, the target pattern may include a fin or a pseudo-gate structure.
[0020] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate; a target pattern located on the substrate; an isolation material layer located on the substrate where the target pattern is exposed, wherein the top of the isolation material layer is higher than the top surface of the target pattern; and dopant ions located in the isolation material layer.
[0021] Optionally, the substrate includes a first region and a second region, the target pattern located in the first region is designated as the first target pattern, the target pattern located in the second region is designated as the second target pattern, and the height of the second target pattern is greater than the height of the first target pattern; the doping ion concentration of the isolation material layer in the second region is greater than the doping ion concentration of the isolation material layer in the first region.
[0022] Optionally, the doped ions include He, Ne, Kr, or Ar.
[0023] Optionally, the material of the insulating material layer includes silicon oxide.
[0024] Optionally, the semiconductor structure further includes: a protective layer located between the target pattern and the isolation material layer, and between the substrate and the isolation material layer.
[0025] Optionally, the target pattern may include a fin or a pseudo-gate structure.
[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0027] In the semiconductor structure formation method provided by this invention, during the substrate provision step, the spacing between target patterns varies. During the formation of the isolation material layer, the filling rate of the isolation material layer between target patterns with larger spacing is faster, while the filling rate between target patterns with smaller spacing is slower. This difference is more pronounced at the top of the target patterns during the formation of the isolation material layer, resulting in uneven stress on the top of the target patterns and making them prone to bending. Taking the bending direction of the target patterns as the first direction, during the doping process of the isolation material layer, the doping ions can break the chemical bonds in the isolation material layer, resulting in compressive stress in the isolation material layer. This compressive stress causes the target patterns to bend in the opposite direction to the first direction, giving the target patterns better morphological quality, reducing the risk of bridging between adjacent target patterns, and improving the electrical performance of the semiconductor structure.
[0028] In an optional embodiment, after doping the isolation material layer with ions, the isolation material layer is annealed. During the annealing process, energy is provided for the ions in the isolation material layer to recombine into chemical bonds, thereby reducing the volume of the isolation material layer and correspondingly increasing the compressive stress present in the isolation material layer. This causes the target pattern to continue to bend in the opposite direction to the first direction, making the target pattern easier to be located in the normal direction of the substrate surface, thus optimizing the electrical performance of the semiconductor structure. In addition, the annealing process of the isolation material layer can also improve the density of the isolation material layer. Attached Figure Description
[0029] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0030] Figures 4 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0031] The semiconductor structures currently being formed still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure formation method.
[0032] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0033] like Figure 1As shown, a substrate is provided, the substrate including a first region I and a second region II, the first region I being used to form an NMOS and the second region II being used to form a PMOS, the substrate including a substrate 10 and fins located on the substrate 10, the fins located in the first region I being designated as first fins 1, and the fins located in the second region II being designated as second fins 2, the second fins 2 including a bottom fin 21 and a top fin 22 located on the bottom fin 21.
[0034] Specifically, the first fin 1 is made of silicon, the bottom fin 21 is made of silicon, and the top fin 22 is made of silicon germanide.
[0035] like Figure 2 As shown, an isolation material layer 3 is formed covering the fin and the substrate 10, with the top surface of the isolation material layer 3 being higher than the top of the fin.
[0036] like Figure 3 As shown, the isolation material layer 3 of a certain thickness is etched to form an isolation layer 4, the top surface of the isolation layer 4 being higher than the bottom surface of the top fin portion 22.
[0037] Typically, the spacing between fins varies. During the step of forming the isolation material layer 3, the filling rate of the isolation material layer 3 between fins with larger spacing is faster, while the filling rate of the isolation material layer 3 between fins with smaller spacing is slower. In the step of forming the isolation material layer 3, this difference is more obvious at the top of the fins, resulting in uneven stress on the top of the fins and easy bending of the fins. This makes the first fin 1 and the second fin 2 easy to bend, which in turn makes it easy for the first fin 1 or the second fin 2 to bridge, resulting in poor electrical performance of the semiconductor structure.
[0038] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a substrate and a target pattern located on the substrate; forming an isolation material layer covering the substrate and the target pattern, the top of the isolation material layer being higher than the top surface of the target pattern; and doping the isolation material layer with ions to generate stress in the isolation material layer.
[0039] This invention provides a method for forming a semiconductor structure, including: in the step of providing a substrate, the spacing between target patterns varies; in the step of forming an isolation material layer, the filling rate of the isolation material layer between target patterns with larger spacing is faster, while the filling rate of the isolation material layer between target patterns with smaller spacing is slower; in the step of forming the isolation material layer, this difference is more pronounced at the top of the target patterns, resulting in uneven stress at the top of the target patterns and easy bending of the target patterns; taking the bending direction of the target patterns as a first direction, during the process of doping the isolation material layer with ions, the doping ions can break the chemical bonds in the isolation material layer, resulting in compressive stress in the isolation material layer; the compressive stress causes the target patterns to bend in the opposite direction to the first direction, resulting in better morphological quality of the target patterns, reducing the risk of bridging between adjacent target patterns, and improving the electrical performance of the semiconductor structure.
[0040] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0041] Figures 4 to 12 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0042] refer to Figure 4 A substrate is provided, the substrate including a substrate 100 and a target pattern located on the substrate 100.
[0043] The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.
[0044] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.
[0045] In this embodiment, the target pattern includes a fin. In other embodiments, the target pattern also includes a pseudo-gate structure.
[0046] The fins are used to subsequently provide the channels for fin field-effect transistors.
[0047] In the step of providing a base, the base includes a first region I and a second region II, the target graphic located in the first region I is designated as a first target graphic 101, the target graphic located in the second region II is designated as a second target graphic 102, and the height of the second target graphic 102 is greater than the height of the first target graphic 101.
[0048] In this embodiment, the first region I is used to form an NMOS (Negative channel Metal Oxide Semiconductor), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor).
[0049] In this embodiment, the first target pattern 101 is made of the same material as the substrate 100, which is silicon. In other embodiments, the first target pattern may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0050] In this embodiment, the second target pattern 102 includes a bottom fin portion 1021 and a top fin portion 1022 located on the bottom fin portion 1021.
[0051] When the semiconductor structure is in operation, the top fin 1022 is used as the channel region of the PMOS.
[0052] Specifically, the material of the bottom fin 1021 is the same as the material of the substrate 100, and the material of the fin is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0053] The material of the top fin 1022 includes silicon germanide, that is, the molar volume percentage of germanium in the top fin 1022 is higher than that in the bottom fin 1021. Because germanium atoms are larger than silicon atoms, when the bottom fin 1021 with a lower germanium concentration comes into contact with the top fin 1022 with a higher germanium concentration, compressive stress will be generated in the top fin 1022 and tensile stress will be generated in the bottom fin 1021. The compressive stress in the top fin 1022 is beneficial to improving the carrier mobility in the PMOS.
[0054] It should be noted that the spacing values between the target graphics vary during the step of providing the base; that is, the spacing between the target graphics can be large or small.
[0055] It should also be noted that the substrate further includes a mask layer 104, located on the target pattern.
[0056] Subsequently, an isolation material layer is formed covering the target pattern and the substrate 100. The top of the isolation material layer is higher than the top surface of the target pattern. During the process of doping the isolation material layer with ions, the mask layer 104 can protect the top of the target pattern.
[0057] Specifically, the mask layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the mask layer 104 includes silicon nitride.
[0058] It should be noted that the steps of forming the substrate 100 and the target pattern include: providing an initial substrate (not shown in the figure), a first semiconductor material layer (not shown in the figure) located on the initial substrate in the first region I, and a second semiconductor material layer (not shown in the figure) located on the initial substrate in the second region II, wherein the etching resistance of the second semiconductor material layer is less than that of the first semiconductor material layer; etching the first semiconductor material layer, the second semiconductor material layer, and the initial substrate using the mask layer 104 as a mask to form the substrate 100 and the target pattern located on the substrate 100.
[0059] Because the etching resistance of the second semiconductor material layer is less than that of the first semiconductor material layer, during the etching process of forming the substrate 100 and the target pattern using the mask layer 104 as a mask, when the first semiconductor material layer is etched, the second semiconductor material layer has already been etched, and a portion of the initial substrate thickness has been etched. Therefore, if the initial substrate is etched further, the height of the second target pattern 102 formed is greater than the height of the first target pattern 101.
[0060] In this embodiment, the tops of the first target graphic 101 and the second target graphic 102 are flush, therefore, the bottom of the second target graphic 102 is lower than the bottom of the first target graphic 101.
[0061] Typically, the mask layer 104 is formed using self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) techniques. However, there is a problem of inconsistent spacing (pitching-walking) between the mask layers 104.
[0062] The height of the second target pattern 102 is greater than the height of the first target pattern 101, which may cause the second target pattern 102 to be more curved than the first target pattern 101 during the subsequent formation of the isolation material layer covering the substrate 100 and the fin.
[0063] It should be noted that, in this embodiment, a pad oxide layer 105 is also formed between the mask layer 104 and the target pattern.
[0064] The pad oxide layer 105 serves as a stress buffer during the formation of the mask layer 104, improving the adhesion between the mask layer 104 and the target pattern and avoiding the problem of dislocation caused by direct contact between the mask layer 104 and the target pattern.
[0065] In this embodiment, the material of the pad oxide layer 105 is silicon oxide.
[0066] The method for forming the semiconductor structure further includes: after providing the substrate and before forming the isolation material layer 103, forming a conformal protective layer 106 covering the target pattern.
[0067] Subsequently, an isolation material layer covering the target pattern is formed. During the process of doping the isolation material layer with ions, the protective layer 106 protects the target pattern, making it difficult for the doped ions to enter the target pattern and preventing damage such as stacking faults from occurring in the target pattern. In this embodiment, the target pattern includes fins, and the top of the fins serves as a channel region. Accordingly, the fins have good formation quality, which is beneficial to improving the migration rate of charge carriers in the channel.
[0068] In this embodiment, the protective layer 106 includes a silicon oxide layer. In other embodiments, the protective layer may also be a silicon oxynitride layer, or the silicon oxide layer and a silicon nitride layer located on the silicon oxide layer.
[0069] In this embodiment, the protective layer 106 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the protective layer 106, allowing for precise control of its thickness. Furthermore, ALD offers good gap-filling performance and step coverage, thereby enhancing the conformal coverage of the protective layer 106. In other embodiments, the protective layer can also be formed using chemical vapor deposition (CVD).
[0070] It should be noted that the protective layer 106 should not be too thick or too thin. If the protective layer 106 is too thick, the gravitational force exerted by the protective layer 106 on the target pattern will be too great, and the target pattern will be prone to bending or tilting, resulting in poor electrical performance of the semiconductor structure. If the protective layer 106 is too thin, during the subsequent doping of the isolation material layer, the protective layer 106 will not be able to protect the target pattern well. In other words, the protective layer 106 will not be able to protect the fins well, and the fins will be prone to damage such as stacking faults. Subsequently, the top of the fins serves as the channel region, where carriers are prone to scattering, resulting in a low carrier migration rate in the channel. In this embodiment, the thickness of the protective layer 106 is 3 nanometers to 6 nanometers.
[0071] It should be noted that in the step of forming the conformal protective layer 106 covering the target pattern, the protective layer 106 is also formed on the surface of the mask layer 104 and the substrate 100 between the target pattern.
[0072] refer to Figure 5 An isolation material layer 103 is formed covering the substrate 100 and the target pattern, with the top of the isolation material layer 103 being higher than the top surface of the target pattern.
[0073] The insulating material layer 103 is used to prepare for the subsequent formation of the insulating layer.
[0074] Specifically, the top of the isolation material layer 103 is higher than the mask layer 104.
[0075] In this embodiment, the isolation material layer 103 comprises flowable silicon oxide, which contains a high concentration of Si-N and Si-H bonds. In other embodiments, the isolation material layer may also comprise spin-on glass coating (SOG) or chemical vapor deposition oxide.
[0076] In this embodiment, a flowable chemical vapor deposition (FCVD) process is used to form an isolation material layer 103 covering the substrate 100 and the target pattern. The FCVD process has good filling ability and is suitable for filling openings with high aspect ratios, which helps reduce the probability of voids and other defects forming within the isolation material layer 103. The isolation material layer 103 includes flowable silicon oxide and contains a high concentration of Si-H bonds, Si-O, and Si-OH. These chemical bonds give the isolation material layer 103 good fluidity and filling ability, which helps reduce the probability of voids and other defects forming within the isolation material layer 103, and consequently improves the film quality of the isolation layer.
[0077] In other embodiments, a spin coating dielectric process or a high aspect ratio process (HARP) can be used to form an isolation material layer covering the substrate and the target pattern.
[0078] It should be noted that during the formation of the isolation material layer 103, the filling rate of the isolation material layer 103 between target patterns with larger spacing is faster, while the filling rate of the isolation material layer 103 between target patterns with smaller spacing is slower. In the step of forming the isolation material layer 103, this difference is more obvious at the top of the target pattern, resulting in uneven stress on the top of the target pattern and easy bending of the target pattern. The bending direction of the target pattern is taken as the first direction.
[0079] It should be noted that the height of the second target graphic 102 is greater than the height of the first target graphic 101, and the aspect ratio of the second target graphic 102 is greater than that of the first target graphic 101. During the formation of the isolation material layer 103, the curvature of the second target graphic 102 is greater than that of the first target graphic 101.
[0080] refer to Figures 6 to 9 Ions are doped into the isolation material layer 103 to generate stress in the isolation material layer 103.
[0081] The isolation material layer 103 is doped with ions, which can break the chemical bonds in the isolation material layer 103, thereby generating compressive stress in the isolation material layer 103. This causes the target pattern to bend in the opposite direction to the first direction. The compressive stress causes the target pattern to bend in the opposite direction to the first direction, which makes the target pattern have better morphological quality, reduces the risk of bridging between adjacent target patterns, and is beneficial to improving the electrical performance of the semiconductor structure.
[0082] Specifically, the doped ions can break the Si-N and Si-H bonds in the isolation material layer 103.
[0083] In this embodiment, ion implantation is used to dope the isolation material layer 103 with ions. Ion implantation has advantages such as simple operation and low process cost.
[0084] Specifically, in the step of doping the isolation material layer 103 with ions, the doping ions include He, Ne, Kr, or Ar. In this embodiment, the doping ions in the step of doping the isolation material layer 103 with ions include He.
[0085] It should be noted that the process temperature should not be too high or too low during the doping of the isolation material layer 103. If the process temperature is too high, it will increase the thermal budget, leading to excessive breakage of chemical bonds in the isolation material layer 103. This results in excessive compressive stress in the isolation material layer 103. The compressive stress causes the second target pattern to bend in the opposite direction to the first direction until it is vertical, and then continue to bend in the opposite direction to the first direction, resulting in poor morphology of the second target pattern. Furthermore, if the temperature is too high, the doped ions will easily diffuse into the target pattern. In this embodiment, the target pattern is a fin, and the subsequent fin serves as a channel region. Doped ions located in the channel region tend to reduce the carrier migration rate, resulting in poor electrical performance of the semiconductor structure. If the process temperature is too low, too few chemical bonds in the isolation material layer 103 will break during the ion doping process, resulting in insufficient compressive stress in the isolation material layer 103. This compressive stress will cause the target pattern to bend too little in the direction opposite to the first direction, causing the target pattern to still bend in the first direction. Furthermore, if the temperature is too low, too few chemical bonds in the isolation material layer 103 will break, and the isolation material layer 103 will still have strong fluidity, resulting in insignificant improvement in the density of the isolation material layer 103. In this embodiment, the process temperature for doping the isolation material layer 103 with ions is between 300°C and 600°C.
[0086] In this embodiment, the target pattern located in the first region I is the first target pattern 101, and the target pattern located in the second region II is the second target pattern 102. The step of doping the isolation material layer 103 with ions includes: doping the isolation material layer 103 in the second region II with ions using a first doping process; and doping the isolation material layer 103 in the first region I with ions using a second doping process.
[0087] It should be noted that the bottom of the second target pattern 102 is lower than the bottom of the first target pattern 101. Correspondingly, the thickness of the isolation material layer 103 in the second region II is greater than the thickness of the isolation material layer 103 in the first region I.
[0088] The process temperature in the first doping process 108 is higher than the process temperature in the second doping process 110.
[0089] In this embodiment, the thickness of the isolation material layer 103 in the second region II is greater than the thickness of the isolation material layer 103 in the first region I, and the process temperature in the first doping process 108 is greater than the process temperature in the second doping process 110. This makes the Si-N bonds and Si-H bonds in the isolation material layer 103 at the bottom between the second target patterns 102 more likely to break. The bottom of the isolation material layer 103 exerts a larger compressive stress on the second target pattern 102, causing the second target pattern 102 to bend in the opposite direction to the first direction. The second target pattern 102 has better morphological quality, reducing the risk of bridging between adjacent second target patterns 102, thereby improving the electrical performance of the semiconductor structure.
[0090] The doping dose in the first doping process 108 is greater than the doping dose in the second doping process 110.
[0091] In this embodiment, the thickness of the isolation material layer 103 in the second region II is greater than the thickness of the isolation material layer 103 in the first region I, the doping dose in the first doping process 108 is greater than the doping dose in the second doping process 110, and the concentration of doped ions in the isolation material layer 103 in the second region II is higher, making the Si-N bonds and Si-H bonds in the isolation material layer 103 in the second region II easier to break. As a result, during the doping process, the compressive stress on the second target pattern 102 is greater than the compressive stress on the first target pattern layer 101. The first target pattern 101 with a smaller degree of curvature is subjected to a smaller force, while the second target pattern 102 with a larger degree of curvature is subjected to a larger force. This makes it easier for both the first and second target patterns to be aligned in the normal direction of the substrate 100 surface, reducing the risk of bridging between adjacent second target patterns 102 and first target patterns 101, thereby improving the electrical performance of the semiconductor structure.
[0092] The doping energy in the first doping process 108 is greater than the doping energy in the second doping process 110.
[0093] In this embodiment, the doping energy in the first doping process 108 is greater than the doping energy in the second doping process 110, making it easier for doped ions to reach the bottom of the isolation material layer 103 between the second target patterns 102. This makes it easier for the Si-N bonds and Si-H bonds in the isolation material layer 103 at the bottom between the second target patterns 102 to break. The bottom of the isolation material layer 103 exerts a larger compressive stress on the second target pattern 102, causing the second target pattern 102 to bend in the opposite direction to the first direction. The second target pattern 102 has better morphological quality, reducing the risk of bridging between adjacent second target patterns 102, thereby improving the electrical performance of the semiconductor structure.
[0094] Specifically, the step of doping the isolation material layer 103 with ions includes:
[0095] like Figure 6 As shown, a first mask layer 107 is formed that covers the first region I and exposes the second region II.
[0096] The first mask layer 107 is an implantation mask for subsequent ion implantation in the second region II.
[0097] Specifically, the material of the first mask layer 107 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the material of the first mask layer 107 is silicon nitride.
[0098] like Figure 7 As shown, the isolation material layer 103 exposed by the first mask layer 107 is doped with ions using the first doping process 108.
[0099] It should be noted that the process temperature during the first doping process 108 should not be too high or too low. If the process temperature is too high, it will increase the thermal budget, leading to excessive breakage of chemical bonds in the isolation material layer 103. This results in excessive compressive stress in the isolation material layer 103, causing the second target pattern 102 to bend in the opposite direction to the first direction until it reaches a vertical position, and then continue to bend in the opposite direction to the first direction, resulting in poor morphology of the second target pattern 102. Furthermore, if the temperature is too high, the doped ions are more likely to diffuse into the second target pattern 102. In this embodiment, the second target pattern 102 is a fin, and the subsequent fin serves as a channel region. Doped ions located in the channel region tend to reduce the carrier migration rate, resulting in poor electrical performance of the semiconductor structure. If the process temperature is too low, too few chemical bonds will break in the isolation material layer 103 during the doping process, resulting in insufficient compressive stress in the isolation material layer 103. This compressive stress will cause the second target pattern 102 to bend too little in the direction opposite to the first direction, causing the second target pattern 102 to still bend in the first direction. Furthermore, if the temperature is too low, too few chemical bonds will break in the isolation material layer 103, resulting in the isolation material layer 103 still having strong fluidity, leading to insignificant improvement in the density of the isolation material layer 103. In this embodiment, the process temperature during the first doping process 108 is 400°C to 600°C.
[0100] It should be noted that during the first doping process 108, the injection energy should not be too high or too low. Subsequently, a gate structure covering the top fin 1022 is formed. The top fin 1022 covered by the gate structure serves as the channel region. If the injection energy is too high, dopant ions can easily penetrate the protective layer 106 and be doped into the top fin 1022, causing lattice damage to the top fin 1022. During semiconductor structure operation, the carrier migration rate in the channel is poor, resulting in poor electrical performance of the semiconductor structure. If the implantation energy is too low, the dopant ions will have difficulty doping into the isolation material layer 103 at the bottom between the second target patterns 102. Consequently, fewer Si-N and Si-H bonds will break in the isolation material layer 103, resulting in insufficient compressive stress in the isolation material layer 103. This compressive stress causes the second target pattern 102 to bend too little in the direction opposite to the first direction, resulting in the second target pattern 102 still bending in the first direction. This leads to poor morphology of the second target pattern 102 and consequently, poor electrical performance of the semiconductor structure. In this embodiment, the implantation energy during the first doping process 108 is between 2 KeV and 30 KeV.
[0101] It should be noted that during the first doping process 108, the doping dose should not be too large or too small. If the doping dose is too large, too many chemical bonds in the isolation material layer 103 will break, resulting in excessive compressive stress in the isolation material layer 103. This compressive stress causes the second target pattern 102 to bend in the opposite direction to the first direction until it reaches a vertical position, and then continues to bend in the opposite direction, resulting in poor morphology of the second target pattern 102. If the doping dose is too small, too few chemical bonds in the isolation material layer 103 will break, resulting in insufficient compressive stress in the isolation material layer 103. This compressive stress causes the second target pattern 102 to bend too little in the opposite direction to the first direction, resulting in the second target pattern 102 still bending in the first direction. Insufficient chemical bond breakage in the isolation material layer 103 also means that the isolation material layer 103 still has strong fluidity, resulting in insignificant improvement in the density of the isolation material layer 103. In this embodiment, the doping dose is 1E15 atoms per square centimeter to 1E17 atoms per square centimeter.
[0102] The method for forming the semiconductor structure further includes: after doping the isolation material layer 103 of the first mask layer 107 with ions using a first doping process 108, removing the first mask layer 107.
[0103] In this embodiment, a wet etching process is used to remove the first mask layer 107. Wet etching is an isotropic etching process, characterized by high etching rates, simple operation, and low cost. The material of the first mask layer 107 includes silicon nitride, and correspondingly, the wet etching solution includes a phosphoric acid solution.
[0104] like Figure 8 As shown, a second mask layer 110 is formed that covers the second region II and exposes the first region I.
[0105] The second mask layer 110 is an implantation mask for subsequent ion implantation in the first region I.
[0106] Specifically, the material of the second mask layer 110 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, and silicon boron carbide. In this embodiment, the material of the second mask layer 110 is silicon nitride.
[0107] like Figure 9 As shown, the isolation material layer 103 exposed by the second mask layer 110 is doped with ions using the second doping process 110.
[0108] It should be noted that during the second doping process 110, the process temperature should not be too high or too low. If the process temperature is too high, it will increase the thermal budget, leading to excessive breakage of chemical bonds in the isolation material layer 103. This results in excessive compressive stress in the isolation material layer 103, causing the first target pattern 101 to bend in the opposite direction to the first direction until it reaches a vertical position, and then continue to bend in the opposite direction to the first direction, resulting in poor morphology of the first target pattern 101. Furthermore, if the temperature is too high, the doped ions are more likely to diffuse into the first target pattern 101. In this embodiment, the first target pattern 101 is a fin, and the subsequent fin serves as a channel region. Doped ions located in the channel region tend to reduce the carrier migration rate, resulting in poor electrical performance of the semiconductor structure. If the process temperature is too low, too few chemical bonds will break in the isolation material layer 103 during the doping process, resulting in insufficient compressive stress in the isolation material layer 103. This compressive stress will cause the first target pattern 101 to bend too little in the direction opposite to the first direction, causing the first target pattern 101 to still bend in the first direction. Furthermore, if the temperature is too low, too few chemical bonds will break in the isolation material layer 103, resulting in strong fluidity and insignificant improvement in the density of the isolation material layer 103. In this embodiment, the process temperature during the second doping process 110 is between 300°C and 600°C.
[0109] It should be noted that during the second doping process 110, the injection energy should not be too high or too low. Subsequently, a gate structure covering the first target pattern 101 is formed. The first target pattern 101 covered by the gate structure serves as the channel region. If the injection energy is too high, dopant ions can easily penetrate the protective layer 106 and be incorporated into the first target pattern 101, causing lattice damage. During semiconductor structure operation, the carrier migration rate in the channel is poor, resulting in poor electrical performance of the semiconductor structure. If the injection energy is too low, dopant ions cannot easily be incorporated into the isolation material layer 103 at the bottom between the first target patterns 101. Fewer Si-N and Si-H bonds in the isolation material layer 103 at the bottom between the first target patterns 101 break, resulting in insufficient compressive stress in the isolation material layer 103. This compressive stress causes the first target pattern 101 to bend too little in the direction opposite to the first direction, resulting in the first target pattern 101 still bending in the first direction. This leads to poor morphology of the first target pattern 101 and poor electrical performance of the semiconductor structure. In this embodiment, during the second doping process 110, the implantation energy is 0.5 KeV to 20 KeV.
[0110] It should be noted that during the second doping process 110, the doping dosage should not be too high or too low. If the doping dosage is too high, too many chemical bonds in the isolation material layer 103 will break, resulting in excessive compressive stress in the isolation material layer 103. This compressive stress causes the first target pattern 101 to bend in the opposite direction to the first direction until it reaches a vertical position, and then continues to bend in the opposite direction, resulting in poor morphology of the first target pattern 101. If the doping dosage is too low, too few chemical bonds in the isolation material layer 103 will break, resulting in insufficient compressive stress in the isolation material layer 103. This compressive stress causes the first target pattern 101 to bend too little in the opposite direction to the first direction, resulting in the first target pattern 101 still bending in the first direction. With too few chemical bonds broken in the isolation material layer 103, the corresponding isolation material layer 103 will still have strong fluidity, resulting in insignificant improvement in the density of the isolation material layer 103. In this embodiment, during the second doping process 110, the doping dose is from 1E14 atoms per square centimeter to 1E17 atoms per square centimeter.
[0111] like Figure 10 As shown, the method for forming the semiconductor structure further includes: after doping the isolation material layer 103 of the second mask layer 110 with ions using a second doping process 110, removing the second mask layer 110.
[0112] In this embodiment, a wet etching process is used to remove the second mask layer 110. Wet etching is an isotropic etching process, characterized by high etching rates, simple operation, and low cost. The material of the second mask layer 110 includes silicon nitride, and correspondingly, the wet etching solution includes a phosphoric acid solution.
[0113] refer to Figure 11 The method for forming the semiconductor structure further includes: after doping the isolation material layer 103 with ions, annealing the isolation material layer 103.
[0114] During the annealing process of the isolation material layer 103, energy is provided for the ions in the isolation material layer 103 to recombine into chemical bonds, thereby reducing the volume of the isolation material layer 103 and correspondingly increasing the compressive stress present in the isolation material layer 103. This results in a greater force for the target pattern to continue bending in the direction opposite to the first direction, making the target pattern more likely to be located in the normal direction of the substrate surface, thus optimizing the electrical performance of the semiconductor structure. In addition, the annealing process of the isolation material layer 103 can also improve the density of the isolation material layer 103.
[0115] It should be noted that the annealing temperature of the isolation material layer 103 should not be too high or too low. If the process temperature is too high, it will increase the thermal budget, resulting in too many recombination of chemical bonds in the isolation material layer 103, excessive volume reduction of the isolation material layer 103, and thus excessive compressive stress in the isolation material layer 103. This compressive stress causes the second target pattern to bend in the opposite direction to the first direction until it is vertical, and then continue to bend in the opposite direction to the first direction, resulting in poor morphology of the second target pattern 102. Furthermore, if the temperature is too high, the doped ions will easily diffuse into the target pattern. In this embodiment, the target pattern is a fin, and the subsequent fin serves as a channel region. Doped ions located in the channel region tend to reduce the carrier migration rate, resulting in poor electrical performance of the semiconductor structure. If the process temperature is too low, there will be too few recombinated chemical bonds in the isolation material layer 103, resulting in insufficient volume reduction of the isolation material layer 103. Consequently, the compressive stress in the isolation material layer 103 will be too low, causing insufficient bending of the target pattern in the direction opposite to the first direction, resulting in the target pattern still bending in the first direction. Furthermore, if the temperature is too low, too few chemical bonds in the isolation material layer 103 will break, and the isolation material layer 103 will still have strong fluidity, resulting in insignificant improvement in the density of the isolation material layer 103. In this embodiment, the process parameters for annealing the isolation material layer 103 include an annealing temperature of 500°C to 700°C.
[0116] refer to Figure 12 After annealing the isolation material layer 103, a portion of the thickness of the isolation material layer 103 is etched to form the isolation layer 112.
[0117] The isolation layer 112 is used to electrically isolate adjacent target patterns; in addition, a gate structure spanning the first target pattern 101 and the second target pattern 102 is subsequently formed on the isolation layer 112, and the isolation layer 112 is used to electrically isolate the gate structure and the substrate 100.
[0118] In this embodiment, a dry etching process is used to etch a portion of the thickness of the isolation material layer 103 to form the isolation layer 112. The dry etching process has anisotropic etching characteristics, which is beneficial for precisely controlling the removal thickness of the isolation material layer 103, ensuring that the thickness of the isolation layer 112 meets the process requirements, and reducing damage to other film structures.
[0119] Specifically, the dry etching process used is the Certas etching process. Using the Certas process helps to reduce the probability of dishing on the top surface of the isolation layer 112 during the etching of the isolation material layer 103.
[0120] It should also be noted that, in the step of forming the isolation layer 112, the top surface of the isolation layer 112 is higher than or flush with the bottom surface of the top fin portion 1022.
[0121] It should be noted that in the step of etching the isolation material layer 103 to form the isolation layer 112, the protective layer 106 that exposes the isolation layer 112 is removed.
[0122] In this embodiment, the material of the protective layer 106 includes a silicon oxide layer. Therefore, during the formation of the isolation layer 112, the protective layer 106 that exposes the isolation layer 112 can be removed, allowing the subsequently formed gate structure to better control the first target pattern 101 and the top fin 1022, which is beneficial to improving the electrical performance of the semiconductor structure.
[0123] The method for forming the semiconductor structure further includes: after forming the isolation layer 112, removing the mask layer 104 and the pad oxide layer 105.
[0124] The mask layer 104 and the pad oxide layer 105 are removed to prepare for the subsequent formation of a gate structure spanning the first target pattern 101 and the second target pattern 102.
[0125] Accordingly, refer to Figure 11 The present invention also provides a semiconductor structure.
[0126] The semiconductor structure includes: a substrate 100; a target pattern located on the substrate 100; an isolation material layer 103 located on the substrate 100 where the target pattern is exposed, the top of the isolation material layer 103 being higher than the top surface of the target pattern; and doped ions located in the isolation material layer 103.
[0127] In the semiconductor structure provided by this invention, the spacing between target patterns typically varies. During the step of forming an isolation material layer 103 on the substrate 100 exposed by the target patterns, the filling rate of the isolation material layer 103 between target patterns with larger spacing is faster, while the filling rate between target patterns with smaller spacing is slower. This difference is more pronounced at the top of the target patterns during the formation of the isolation material layer 103, resulting in uneven stress on the top of the target patterns and making them prone to bending. Taking the bending direction of the target patterns as a first direction, the doping ions can break the chemical bonds in the isolation material layer 103, causing compressive stress in the isolation material layer 103. This compressive stress causes the target patterns to bend in the direction opposite to the first direction, resulting in better morphological quality of the target patterns, reducing the risk of bridging between adjacent target patterns, and improving the electrical performance of the semiconductor structure.
[0128] In this embodiment, the target pattern includes a fin. In other embodiments, the target pattern also includes a pseudo-gate structure.
[0129] The fins are used to subsequently provide the channels for fin field-effect transistors.
[0130] The base includes a first region I and a second region II. The target graphic located in the first region I is designated as a first target graphic 101, and the target graphic located in the second region II is designated as a second target graphic 102. The height of the second target graphic 102 is greater than the height of the first target graphic 101.
[0131] In this embodiment, the first region I is used to form an NMOS (Negative channel Metal Oxide Semiconductor), and the second region II is used to form a PMOS (Positive Channel Metal Oxide Semiconductor).
[0132] In this embodiment, the first target pattern 101 is made of the same material as the substrate 100, which is silicon. In other embodiments, the first target pattern may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0133] In this embodiment, the second target pattern 102 includes a bottom fin portion 1021 and a top fin portion 1022 located on the bottom fin portion 1021.
[0134] When the semiconductor structure is in operation, the top fin 1022 is used as the channel region of the PMOS.
[0135] Specifically, the material of the bottom fin 1021 is the same as the material of the substrate 100, and the material of the fin is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0136] The material of the top fin 1022 includes silicon germanide, that is, the molar volume percentage of germanium in the top fin 1022 is higher than that in the bottom fin 1021. Because germanium atoms are larger than silicon atoms, when the bottom fin 1021 with a lower germanium concentration comes into contact with the top fin 1022 with a higher germanium concentration, compressive stress will be generated in the top fin 1022 and tensile stress will be generated in the bottom fin 1021. The compressive stress in the top fin 1022 is beneficial to improving the carrier mobility in the PMOS.
[0137] It should be noted that the substrate also includes a mask layer 104, located on the target pattern.
[0138] During the doping process, the mask layer 104 can protect the top of the target pattern.
[0139] Specifically, the mask layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, and boron silicon carbide. In this embodiment, the mask layer 104 includes silicon nitride.
[0140] In this embodiment, the isolation material layer 103 prepares for the subsequent formation of an isolation layer. The isolation layer is used to electrically isolate adjacent fins and also to electrically isolate the substrate 100 and the gate structure formed subsequently.
[0141] In this embodiment, the material of the isolation layer 103 includes silicon oxide. Silicon oxide has high process compatibility and is also a commonly used and low-cost material, which helps to reduce process difficulty and cost.
[0142] It should be noted that the height of the second target graphic 102 is greater than the height of the first target graphic 101. Specifically, the tops of the first target graphic 101 and the second target graphic 102 are flush, and the bottom of the second target graphic 102 is lower than the bottom of the first target graphic 101.
[0143] Accordingly, the dopant ion concentration of the isolation material layer 103 in the second region II is greater than the dopant ion concentration of the isolation material layer 103 in the first region I.
[0144] In this embodiment, the concentration of doped ions in the isolation material layer 103 of the second region II is relatively high, making the Si-N bonds and Si-H bonds in the isolation material layer 103 of the second region II easier to break. The compressive stress exerted by the isolation material layer 103 of the second region II on the second target pattern 102 is greater than the compressive stress exerted by the isolation material layer 103 of the first region I on the first target pattern layer 101. The first target pattern 101 with a smaller degree of curvature is subjected to a smaller compressive stress, while the second target pattern 102 with a larger degree of curvature is subjected to a larger compressive stress. This makes it easier for both the first and second target patterns to be aligned in the normal direction of the substrate 100 surface, reducing the risk of bridging between adjacent second target patterns 102 and first target patterns 101, thereby improving the electrical performance of the semiconductor structure.
[0145] In this embodiment, the doping ions include He, Ne, Kr, or Ar. During the subsequent annealing process of the isolation material layer 103, energy is provided for the ions in the isolation material layer 103 to recombine into chemical bonds, thereby reducing the volume of the isolation material layer 103 and creating compressive stress. This compressive stress causes the target pattern to bend in the opposite direction to the first direction, resulting in better morphological quality of the target pattern, reducing the risk of bridging between adjacent target patterns, and improving the electrical performance of the semiconductor structure.
[0146] It should be noted that the semiconductor structure further includes a pad oxide layer 105, located between the mask layer 104 and the target pattern.
[0147] The pad oxide layer 105 serves as a stress buffer during the formation of the mask layer 104, improving the adhesion between the mask layer 104 and the target pattern and avoiding the problem of dislocation caused by direct contact between the mask layer 104 and the target pattern.
[0148] In this embodiment, the material of the pad oxide layer 105 is silicon oxide.
[0149] The semiconductor structure further includes a protective layer 106 located between the isolation material layer 103 and the substrate 100, and between the isolation material layer 103 and the target pattern.
[0150] In this embodiment, the protective layer 106 is made of a silicon oxide layer. In other embodiments, the protective layer may also be made of a silicon oxynitride layer, or the silicon oxide layer and a silicon nitride layer located on the silicon oxide layer.
[0151] During the doping of the isolation material layer 103 with ions, the protective layer 106 protects the target pattern, making the target pattern less susceptible to damage such as stacking faults. In this embodiment, the target pattern includes fins, and the top of the fins is subsequently used as a channel region. Accordingly, the fins are less susceptible to stacking faults, which is beneficial to improving the migration rate of charge carriers in the channel.
[0152] The semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; these descriptions will not be repeated here.
[0153] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a substrate and a target pattern located on the substrate; An isolation material layer is formed covering the substrate and the target pattern, wherein the top of the isolation material layer is higher than the top surface of the target pattern; Ions are doped into the isolation material layer to generate stress in the isolation material layer in the opposite direction to the bending direction of the target pattern; The method for forming the semiconductor structure further includes: after doping the isolation material layer with ions, annealing the isolation material layer to increase the stress in the isolation material layer in the opposite direction to the bending direction of the target pattern.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of doping the isolation material layer with ions, the doping ions include He, Ne, Kr or Ar.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The isolation material layer is doped with ions using an ion implantation process.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the process of doping the isolation material layer with ions, the process temperature is 300°C to 600°C.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a base, the base includes a first region and a second region, the target graphic located in the first region is used as a first target graphic, the target graphic located in the second region is used as a second target graphic, and the height of the second target graphic is greater than the height of the first target graphic; The step of doping the isolation material layer with ions includes: forming a first mask layer that covers the first region and exposes the second region; and doping the isolation material layer exposed by the first mask layer with ions using a first doping process. A second mask layer is formed to cover the second region and expose the first region; the isolation material layer exposed by the second mask layer is doped with ions using a second doping process, wherein the doping dose in the second doping process is less than the doping dose in the first doping process.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process temperature in the first doping process is higher than the process temperature in the second doping process; The doping energy in the first doping process is greater than the doping energy in the second doping process.
7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The first doping process includes an ion implantation process, and the process parameters of the first doping process include: a process temperature of 400°C to 600°C, an implantation energy of 2 KeV to 30 KeV, and a doping dose of 1E15 atoms per square centimeter to 1E17 atoms per square centimeter.
8. The method for forming a semiconductor structure as described in claim 5, characterized in that, The second doping process includes an ion implantation process, and the process parameters of the second doping process include: a process temperature of 300°C to 600°C, an implantation energy of 0.5 KeV to 20 KeV, and a doping dose of 1E14 atoms per square centimeter to 1E17 atoms per square centimeter.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, An isolation material layer covering the substrate and target pattern is formed using a flowable chemical vapor deposition process, a spin-coating dielectric process, or a high aspect ratio process.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the isolation material layer include flowable silicon dioxide, spin-coated glass, and chemical vapor deposition oxide.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for annealing the insulating material layer include: an annealing temperature of 500°C to 700°C.
12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after providing the substrate and before forming the isolation material layer, forming a conformal protective layer covering the target pattern.
13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The target pattern includes fins or pseudo-gate structures.
14. A semiconductor structure, characterized in that, include: Substrate; The target pattern is located on the substrate; An isolation material layer is located on the substrate exposed by the target pattern, with the top of the isolation material layer higher than the top surface of the target pattern; Doped ions are located in the insulating material layer; The dopant ions are implanted before the isolation material layer is annealed to generate stress in the isolation material layer in the opposite direction to the bending direction of the target pattern; the isolation material layer is annealed to increase the stress in the isolation material layer in the opposite direction to the bending direction of the target pattern.
15. The semiconductor structure as described in claim 14, characterized in that, The substrate includes a first region and a second region, the target pattern located in the first region is designated as the first target pattern, the target pattern located in the second region is designated as the second target pattern, and the height of the second target pattern is greater than the height of the first target pattern; The doped ion concentration of the isolation material layer in the second region is greater than that of the isolation material layer in the first region.
16. The semiconductor structure as claimed in claim 14, characterized in that, The doped ions include He, Ne, Kr, or Ar.
17. The semiconductor structure as claimed in claim 14, characterized in that, The material of the insulating material layer includes silicon oxide.
18. The semiconductor structure as described in claim 14, characterized in that, The semiconductor structure further includes: a protective layer located between the target pattern and the isolation material layer, and between the substrate and the isolation material layer.
19. The semiconductor structure as claimed in claim 14, characterized in that, The target pattern includes fins or pseudo-gate structures.