Capless LDO with reduced temperature impact on output accuracy

Abstract

The application provides a Capless LDO which reduces the influence of temperature on output precision, which is composed of PM0, PM1, PM2, PM3, PM4, NM0, NM1, NM2, NM3, R1, R2, R3 and the like, wherein PM0, PM1, PM2, NM0, NM1 and NM2 constitute a current mirror circuit; PM3 is a power regulating tube and has a certain load capacity; NM3 and PM4 are two-stage source followers, wherein NM3 is a native tube and stabilizes the output voltage Vout to a fixed value; R2 is a loop negative feedback resistor, so that the LDO has the ability to adjust different loads; R1 and R3 are matching resistors, which ensure that the source end voltage of NM0 and NM2 is consistent with the source end voltage of NM1. The Vout of the Capless LDO is greater than the reference voltage VREF, and the Vout is very small in the influence of temperature, and can even be ignored.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a Capless LDO that reduces the impact of temperature on output accuracy. Background Technology

[0002] LDO (Low Drop Out Linear Voltage Regulator) is an IP circuit structure used to provide a stable voltage source with a certain load-carrying capacity. It is widely used in various IC chips to power different functional modules. Based on whether the LDO output needs to be connected to a large capacitor on the PCB via wire bonding, LDOs are simply divided into external capacitor LDOs and capless LDOs (without external capacitors).

[0003] Although Capless LDOs offer the cost advantage of no external capacitors and are easy to integrate, their voltage output value is affected by the temperature coefficient, meaning that temperature affects the accuracy of their voltage output value. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a Capless LDO that reduces the impact of temperature on output accuracy, thereby solving the problem of temperature affecting the accuracy of the voltage output value of Capless LDO in the prior art.

[0005] To achieve the above and other related objectives, this application provides a capless LDO that reduces the impact of temperature on output accuracy, comprising a first PMOS transistor (PM0), a second PMOS transistor (PM1), a third PMOS transistor (PM2), a fourth PMOS transistor (PM3), a fifth PMOS transistor (PM4), a first NMOS transistor (NM0), a second NMOS transistor (NM1), a third NMOS transistor (NM2), a fourth NMOS transistor (NM3), a first resistor (R1), a second resistor (R2), and a third resistor (R3), wherein,

[0006] The source of the first PMOS transistor is connected to the source of the second PMOS transistor, the gate of the first PMOS transistor is connected to the gate of the second PMOS transistor, the connection point is connected to the drain of the first PMOS transistor, and the drain of the first PMOS transistor is connected to the bias current (IBIAS).

[0007] The drain of the second PMOS transistor is connected to the drain of the first NMOS transistor;

[0008] The source of the third PMOS transistor is connected to the junction of the source of the first PMOS transistor and the source of the second PMOS transistor. The gate of the third PMOS transistor is connected to the bias current. The drain of the third PMOS transistor is connected to the gate of the fourth PMOS transistor.

[0009] The source of the fourth PMOS transistor is connected to the junction of the source of the first PMOS transistor and the source of the second PMOS transistor, and the drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor. This junction is the output terminal.

[0010] The gate of the fifth PMOS transistor is connected to the junction of the drain of the third NMOS transistor and the source of the fourth NMOS transistor, and the drain of the fifth PMOS transistor is connected to the junction of the source of the second NMOS transistor and the second resistor.

[0011] The source of the first NMOS transistor is connected to the first resistor, the gate of the first NMOS transistor is connected to the gate of the second NMOS transistor, and the connection point is connected to the connection point of the drain of the first NMOS transistor and the drain of the second PMOS transistor.

[0012] The source of the second NMOS transistor is connected to the second resistor, and the drain of the second NMOS transistor is connected to the junction of the drain of the third PMOS transistor and the gate of the fourth PMOS transistor.

[0013] The source of the third NMOS transistor is connected to the third resistor, the gate of the third NMOS transistor is connected to the junction of the drain of the first NMOS transistor and the drain of the second PMOS transistor, and the drain of the third NMOS transistor is connected to the source of the fourth NMOS transistor.

[0014] The gate of the fourth NMOS transistor is connected to the reference voltage (VREF), and the drain of the fourth NMOS transistor is connected to the junction of the source of the first PMOS transistor and the source of the second PMOS transistor.

[0015] The other ends of the first, second, and third resistors are connected together and then grounded.

[0016] Preferably, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor form a current mirror circuit, and the bias current input to it is provided by the bandgap reference source circuit.

[0017] Preferably, the fourth NMOS transistor and the fifth PMOS transistor are two-stage source followers that stabilize the output voltage to a fixed value.

[0018] Preferably, the fourth NMOS transistor is a native transistor, and the reference voltage connected to the gate of the fourth NMOS transistor is provided by a bandgap reference source circuit.

[0019] Preferably, the output voltage is the sum of the difference between the reference voltage and the product of the threshold voltage and temperature coefficient of the fifth PMOS transistor and the product of the threshold voltage and temperature coefficient of the fourth NMOS transistor.

[0020] Preferably, the threshold voltage of the fifth PMOS transistor and the threshold voltage of the fourth NMOS transistor both exhibit negative temperature coefficients. By adjusting the threshold voltage and temperature coefficient of the fifth PMOS transistor and the threshold voltage and temperature coefficient of the fourth NMOS transistor, the influence of temperature on the output voltage can be reduced or eliminated.

[0021] Preferably, the threshold voltage and temperature coefficient of the fifth PMOS transistor and the threshold voltage and temperature coefficient of the fourth NMOS transistor are adjusted by adjusting the dimensions of the fifth PMOS transistor and the fourth NMOS transistor.

[0022] Preferably, the first resistor and the third resistor are matching resistors to ensure that the source voltage of the first NMOS transistor and the third NMOS transistor are consistent with the source voltage of the second NMOS transistor.

[0023] Preferably, the second resistor is a loop negative feedback resistor, enabling the Capless LDO to adjust to different loads.

[0024] Preferably, the fourth PMOS transistor is a power regulation transistor with a certain load-carrying capacity.

[0025] As described above, the Capless LDO that reduces the impact of temperature on output accuracy provided in this application has the following beneficial effects: the voltage output Vout is larger than the reference voltage VREF, it has a certain load-carrying capacity, and the effect of temperature on Vout is very small, even negligible. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 The diagram shows the existing Capless LDO circuit architecture.

[0028] Figure 2 The diagram shown is a circuit architecture diagram of a Capless LDO that reduces the impact of temperature on output accuracy, as provided in an embodiment of this application.

[0029] Figure 3 The graph shows a comparison of the voltage output curves of the Capless LDO provided in this application embodiment and the existing Capless LDO as a function of temperature. Detailed Implementation

[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0031] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0033] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0034] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0035] like Figure 1As shown, an existing capless LDO consists of devices such as PM0, PM1, PM2, PM3, PM4, NM0, NM1, R1, and R2. Among them, PM0, PM1, PM2, NM0, and NM1 form a current mirror circuit, whose current bias input can be provided by a bandgap reference source circuit (BGR); PM3 is a power regulator with a certain load-driving capability; PM4 is a source follower that can stabilize the output voltage to a fixed value, and its voltage bias can be provided by the bandgap reference source circuit (BGR); R2 is a loop negative feedback resistor, enabling the LDO to adjust its ability to drive different loads; R1 is a matching resistor, ensuring that the source voltage of NM0 is consistent with the source voltage of NM1, so that the mirrored current is as accurate as possible.

[0036] The voltage output Vout is mainly obtained by superimposing the threshold voltage Vt of the PM4 transistor (i.e., Vout = VREF + Vt(PM4)). Vt decreases with increasing temperature, exhibiting a negative temperature coefficient characteristic. Assuming the reference voltage VREF has no temperature coefficient, Vout has a negative temperature coefficient because it is VREF superimposed with a Vt voltage. Although the Vt of the PM4 transistor can be minimized by adjusting its dimensions, the influence of the temperature coefficient cannot be completely eliminated. Furthermore, VREF needs to be modified to ensure the correct value of Vout.

[0037] The rapid development of portable electronic products and the widespread adoption of wearable electronic information products have led to the widespread use of Capless LDOs, which require the LDO's voltage output Vout to have a small deviation with temperature changes.

[0038] To address this issue, this application provides a Capless LDO that reduces the impact of temperature on output accuracy. Based on the existing Capless LDO circuit architecture, the circuit is updated and improved to reduce or eliminate the influence of temperature on the LDO's voltage output Vout, thereby ensuring the stability of the LDO's voltage output Vout and improving output accuracy.

[0039] Please see Figure 2 The diagram shows the circuit architecture of a Capless LDO that reduces the impact of temperature on output accuracy, as provided in an embodiment of this application.

[0040] like Figure 2As shown, this Capless LDO, which reduces the impact of temperature on output accuracy, consists of devices such as PM0, PM1, PM2, PM3, PM4, NM0, NM1, NM2, NM3, R1, R2, and R3. PM0, PM1, PM2, NM0, NM1, and NM2 form a current mirror circuit, providing a normal operating current for each channel. Its current bias input (bias current IBIAS) can be provided by a bandgap reference source circuit (BGR). PM3 is a power regulator transistor with a certain load-driving capability. NM3 and PM4 are two-stage source followers that can convert the output current... To stabilize the voltage to a fixed value, and to ensure that the output voltage Vout is greater than the reference voltage VREF, a native transistor is selected for NM3. Its voltage bias (reference voltage VREF) can be provided by the bandgap reference source circuit (BGR). R2 is the loop negative feedback resistor, enabling the LDO to adjust to different loads. R1 and R3 are matching resistors to ensure that the source voltages of NM0 and NM2 are consistent with the source voltage of NM1, making the mirror current as accurate as possible. The values ​​of R1, R2, and R3 can be calculated based on the magnitude of each current value.

[0041] The voltage output Vout is mainly obtained by superimposing the Vt voltages of NM3 and PM4 transistors (i.e., V2 = VREF - Kn3 * Vt(NM3), Vout = V2 + Kp4 * Vt(PM4), Vout = VREF - Kn3 * Vt(NM3) + Kp4 * Vt(PM4)). Both Vt(NM3) and Vt(PM4) decrease with increasing temperature, exhibiting a negative temperature coefficient characteristic. Assuming the reference voltage VREF has no temperature coefficient, since V2 is VREF minus a negative temperature coefficient Kn3 * Vt(NM3), the output value of V2 has a positive temperature coefficient. Adding the positive temperature coefficient V2 to the negative temperature coefficient Kp4 * Vt(PM4) yields Vout. Adding these two temperature coefficients allows the final Vout output temperature coefficient to be controlled between these two values. If the dimensions of the NM3 and PM4 transistors are adjusted to make their respective Vt temperature coefficients identical, i.e. Furthermore, assuming VREF has no temperature coefficient, Vout will ultimately also lack a temperature coefficient.

[0042] The Capless LDO that reduces the impact of temperature on output accuracy provided in this application embodiment... Figure 1 The diagram shows an existing Capless LDO circuit architecture with the addition of a native transistor NM3, a current mirror transistor NM2, and a matching resistor R3. Figure 2 (The part outlined in the dashed box) can reduce or eliminate the effect of temperature on the output voltage Vout of the Capless LDO.

[0043] right Figure 1 The existing Capless LDO and shown Figure 2 The Capless LDOs for reducing the impact of temperature on output accuracy provided in the embodiments of this application are shown in the design and simulation of actual LDO circuits, such as... Figure 3 As shown, the voltage output of existing Capless LDOs varies greatly with temperature. The Capless LDO provided in this application, which reduces the impact of temperature on output accuracy, exhibits a very small change in voltage output with temperature. Figure 2 The temperature coefficients of the NM3 and PM4 transistors shown are adjusted to be close enough that the temperature coefficient can be completely eliminated, meaning that the voltage output of the Capless LDO is unaffected by temperature.

[0044] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] In summary, the Capless LDO provided in this application, which reduces the impact of temperature on output accuracy, has a voltage output Vout larger than the sub-quadrant voltage VREF, possesses a certain load-carrying capacity, and the effect of temperature on Vout is very small, even negligible. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0046] Those skilled in the art will recognize that the temperature compensation method implemented in the Capless LDO that reduces the impact of temperature on output accuracy provided in this application is based on the cancellation of the temperature coefficients of the two MOS transistors, and this temperature compensation method is applicable to other circuits with similar characteristics.

[0047] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A Capless LDO that reduces the effect of temperature on output accuracy, characterized by, The Capless LDO comprises a first PMOS tube (PM0), a second PMOS tube (PM1), a third PMOS tube (PM2), a fourth PMOS tube (PM3), a fifth PMOS tube (PM4), a first NMOS tube (NM0), a second NMOS tube (NM1), a third NMOS tube (NM2), a fourth NMOS tube (NM3), a first resistor (R1), a second resistor (R2), and a third resistor (R3), wherein, a source of the first PMOS tube is connected to a source of the second PMOS tube, a gate of the first PMOS tube is connected to a gate of the second PMOS tube and a drain of the first PMOS tube, and a drain of the first PMOS tube is connected to a bias current; a drain of the second PMOS tube is connected to a drain of the first NMOS tube; a source of the third PMOS tube is connected to a connection point of the source of the first PMOS tube and the source of the second PMOS tube, a gate of the third PMOS tube is connected to the bias current, and a drain of the third PMOS tube is connected to a gate of the fourth PMOS tube; a source of the fourth PMOS tube is connected to the connection point of the source of the first PMOS tube and the source of the second PMOS tube, and a drain of the fourth PMOS tube is connected to a source of the fifth PMOS tube as an output terminal of the Capless LDO; a gate of the fifth PMOS tube is connected to a connection point of a drain of the third NMOS tube and a source of the fourth NMOS tube, and a drain of the fifth PMOS tube is connected to a connection point of a source of the second NMOS tube and the second resistor; a source of the first NMOS tube is connected to the first resistor, a gate of the first NMOS tube is connected to a gate of the second NMOS tube, a drain of the first NMOS tube, and a drain of the second PMOS tube; a source of the second NMOS tube is connected to the second resistor, and a drain of the second NMOS tube is connected to a connection point of a drain of the third PMOS tube and the gate of the fourth PMOS tube; a source of the third NMOS tube is connected to the third resistor, a gate of the third NMOS tube is connected to a connection point of the drain of the first NMOS tube and the drain of the second PMOS tube, and a drain of the third NMOS tube is connected to a source of the fourth NMOS tube; a gate of the fourth NMOS tube is connected to a reference voltage, and a drain of the fourth NMOS tube is connected to the connection point of the source of the first PMOS tube and the source of the second PMOS tube; the other ends of the first resistor, the second resistor, and the third resistor are connected to each other and then connected to ground.

2. The Capless LDO of claim 1, wherein, The first PMOS tube, the second PMOS tube, the third PMOS tube, the first NMOS tube, the second NMOS tube, and the third NMOS tube constitute a current mirror circuit, and a bias current input by the current mirror circuit is provided by a bandgap reference circuit.

3. The Capless LDO of claim 1, wherein, The fourth NMOS tube and the fifth PMOS tube are two-stage source followers, and an output voltage is stabilized to a fixed value.

4. The Capless LDO according to claim 1 or 3, wherein, The fourth NMOS transistor is a native transistor, and a reference voltage connected to the gate of the fourth NMOS transistor is provided by a bandgap reference circuit.

5. The Capless LDO of claim 1, wherein, The voltage output of the Capless LDO output terminal is the sum of the reference voltage and the difference between the product of the threshold voltage and the temperature coefficient of the fifth PMOS transistor and the product of the threshold voltage and the temperature coefficient of the fourth NMOS transistor.

6. The Capless LDO of claim 5, wherein, The threshold voltage of the fifth PMOS transistor and the threshold voltage of the fourth NMOS transistor both exhibit a negative temperature coefficient characteristic, and by adjusting the threshold voltage and the temperature coefficient of the fifth PMOS transistor and the threshold voltage and the temperature coefficient of the fourth NMOS transistor, the influence of temperature on the voltage output of the Capless LDO output terminal is reduced or eliminated.

7. The Capless LDO of claim 6, wherein, The threshold voltage and the temperature coefficient of the fifth PMOS transistor and the threshold voltage and the temperature coefficient of the fourth NMOS transistor are adjusted by adjusting the size of the fifth PMOS transistor and the fourth NMOS transistor.

8. The Capless LDO of claim 1, wherein, The first resistor and the third resistor are matched resistors, which ensure that the source voltage of the first NMOS transistor, the third NMOS transistor and the second NMOS transistor are consistent.

9. The Capless LDO of claim 1, wherein, The second resistor is a loop negative feedback resistor, which enables the Capless LDO to have the ability to adjust different loads.

10. The Capless LDO of claim 1, wherein, The fourth PMOS transistor is a power adjustment transistor, which has a certain load capacity.

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