A random number post-processing method and system suitable for an SoC chip

Abstract

The application belongs to the technical field of digital chip design, and discloses a random number post-processing method and system suitable for SoC chips. The system comprises a random source unit, a failure detection unit, a chi-square detection unit, an XOR operation unit, a hash operation unit, an output result unit, and a state control unit, which is used for receiving a user command, configuring a random source reset or an enabling switch, recording detection results of each failure detection and chi-square detection unit, configuring an XOR operation unit random source selection sequence number, configuring an enabling switch and a random number generation command of the hash operation unit, and recording the reading state of the output result. The application proposes a general random number post-processing flow method, and enhances the randomness of true and pseudo random data generated in the SoC chip.

Description

Technical Field

[0001] This invention belongs to the field of digital chip design technology, and in particular relates to a random number post-processing method and system suitable for SoC chips. Background Technology

[0002] True random numbers are an important component of cryptography and security, widely used in key generation, random seeds, and algorithm protocols. Typically, SoC chips with security or cryptographic functions incorporate true random number generators. However, factors such as internal chip noise, ambient temperature, and supply voltage can affect the stability and accuracy of these generators. Therefore, SoC chips employ digital post-processing methods to correct the generated random data, enhancing its randomness.

[0003] Based on the above analysis, the problems and defects of the existing technology are as follows: the post-processing of random numbers in existing SoC chips mostly uses hash algorithms for calculation, which lacks failure detection, makes it difficult to identify failed random sources, and easily causes random data failure. In addition, it lacks discrimination, and still performs high-intensity hash algorithm processing on random sources with excellent randomness, resulting in low processing efficiency. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this invention discloses a random number post-processing method and system suitable for SoC chips. The purpose of this invention is to propose a post-processing method for random numbers, primarily focusing on the random number post-processing workflow, possessing a certain degree of versatility, and suitable for enhancing the randomness of generated random numbers. It can serve as a lightweight random number post-processing solution.

[0005] The technical solution is as follows: A random number post-processing system suitable for SoC chips, the system comprising:

[0006] When the random source unit is enabled or disabled, the random number generation function is enabled or disabled, and the corresponding failure detection and chi-square detection functions are enabled or disabled.

[0007] The failure detection unit is used to continuously collect random source generation data from the random source unit, determine the passage status of the detection signal based on the collected random source generation data, and send the random source generation data to the chi-square detection unit.

[0008] The chi-square detection unit uses the chi-square detection algorithm to calculate the proportion of values ​​appearing in the random source-generated data detected by the failure detection unit, determines the passage status of the detection signal based on the proportion, and sends the passed detection signals to the XOR operation unit.

[0009] The XOR operation unit is used to continuously collect random source generated data detected by the chi-square detection unit, perform XOR operation on the collected random source generated data, and output the operation result.

[0010] The hash operation unit is used to continuously collect the XOR operation output results, process the XOR operation output result data using the hash algorithm, and output the processed result.

[0011] The output result unit is used to store the result data processed by the hash operation unit;

[0012] The status control unit is used to receive user commands, configure the random source reset or enable switch, record the detection results of each failure detection and chi-square detection unit, configure the random source selection sequence number of the XOR operation unit, configure the enable switch and random number generation command of the hash operation unit, and record the reading status of the output results.

[0013] Furthermore, the random source unit employs a random number generator, which may include a true random number generator or a pseudo random number generator.

[0014] Furthermore, the failure detection unit collects 32-bit data continuously generated by the corresponding random source as a group; if the collected group of data is all 0 or all 1, it outputs a high-level signal to the status control unit, indicating that the detection has failed; if the collected group of data is not all 0 and not all 1, it indicates that the detection has not failed, and it outputs a low-level signal to the status control unit, indicating that the detection has passed.

[0015] Furthermore, in the chi-square detection unit, the chi-square detection algorithm is used to calculate the proportion of values ​​appearing in the random source generation data of the random source unit. This includes: taking the collected random source generation data of the random source unit into groups of 512 bits, recording the values ​​of every 4 consecutive bits in each group, and counting the frequency of each value. The formula T = (fr(i) - Ei) is then used. 2 / Ei calculates T, where i is 0 to 15, fr(i) is the frequency of the corresponding value, and Ei is the expected value; if the T value of two consecutive sets of data is greater than 65, a detection failure signal is output; if only one of the T values ​​of two consecutive sets of data is greater than 65, a warning signal is output; if the T value of two consecutive sets of data is not greater than 65, a detection pass signal is output.

[0016] Furthermore, in the XOR operation unit, if the number of random sources selected is 0, the XOR operation unit does not work; if the number of random sources selected is 1, the XOR operation unit directly outputs the generated data of the random source.

[0017] Furthermore, in the hash operation unit, the process of processing the XOR operation output data using the hash algorithm includes: continuously collecting 128 bits of the XOR operation output result, performing the operation using the hash algorithm SM3, and outputting a 256-bit operation result.

[0018] Furthermore, when the hash operation unit is enabled, the SM3 operation result is output; when the hash operation unit is disabled, the XOR operation result is directly output.

[0019] Furthermore, the output result unit adopts a storage structure of 16 32-bit registers, and uses 16-bit one-hot code to mark the status of each register, where 0 indicates that the data has been read and 1 indicates that the data has been newly generated.

[0020] Another object of the present invention is to provide a random number post-processing method suitable for SoC chips, the method processing the random number post-processing system suitable for SoC chips, the method comprising:

[0021] S1: After the SoC chip is powered on or reset, the random source unit and hash operation unit are enabled by default, and the XOR operation unit selects all random sources by default. After that, the status control unit reconfigures the enable switch and random source selection sequence number of the random source unit and hash operation unit according to the user command.

[0022] S2: The failure detection unit and the chi-square detection unit collect and detect the random numbers generated by the corresponding random source, and report the detection results to the status control unit; when the failure detection result is a failure, the status control unit disables the corresponding random source; when the chi-square detection result is a warning, the status control unit resets the corresponding random source; when the chi-square detection result is a failure, the status control unit disables the corresponding random source.

[0023] S3: The XOR operation unit selects the data generated by the corresponding random source according to the random source selection number configured by the state control unit, and performs the operation on the selected random source data and outputs it.

[0024] S4: The hash operation unit continuously collects the output results of the XOR operation unit, performs the operation and outputs the result; when the hash operation unit is enabled, it stops working after each round of operation and starts the next round of operation only after the random number generation command is valid.

[0025] S5: The output result unit collects the output data of the hash operation unit and updates 512 bits each time. At this time, the 16-bit status register is all 1s. After the user reads a 32-bit data, the corresponding status register bit is 0. When the status register is all 0 or the user configures a random number generation command, the status control unit configures the hash operation unit to generate a new random number.

[0026] In step S5, the 512 bits are 16 32-bit data registers. At this time, the status register is marked as 16'b1111111111111111. When the first group of data is read, the corresponding status register bit is marked as 0, i.e., 16'b1111111111111110.

[0027] Combining all the above technical solutions, the advantages and positive effects of this invention are as follows: This invention proposes a random number post-processing system and process method suitable for SoC chips. The system is entirely implemented by hardware circuits, which has higher execution efficiency, stronger data security, and includes a variety of post-processing methods. It is suitable for random sources with different random qualities and can further enhance the randomness of true and pseudo random data generated in SoC chips. It is a general-purpose lightweight hardware solution for random number post-processing. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure;

[0029] Figure 1 This is a schematic diagram of a random number post-processing system suitable for SoC chips provided in an embodiment of the present invention;

[0030] Figure 2 This is a flowchart of a random number post-processing method for SoC chips provided in an embodiment of the present invention;

[0031] In the diagram: A, Random Source Unit; B, Failure Detection Unit; C, Chi-square Detection Unit; D, XOR Operation Unit; E, Hash Operation Unit; F, Output Result Unit; G, Status Control Unit. Detailed Implementation

[0032] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0033] The innovative aspects of the random number post-processing method and system for SoC chips provided in this invention are as follows: a random number post-processing system composed of circuit structures such as state control, multi-source combination, failure detection, chi-square detection, XOR operation and hash operation is proposed. The system fully implements functions such as simple detection of random sources, multi-level post-processing and state flow control in hardware, effectively enhancing the randomness of random numbers in SoC chips.

[0034] Example 1, taking the structure of 4 random sources as an example, the number of random sources can be selected according to actual needs in the application. According to the requirements of security level 2 in the "Security Chip Cryptography Detection Guidelines", 4 independent physical random sources are used.

[0035] like Figure 1 As shown, the random number post-processing system for SoC chips provided in this embodiment of the invention consists of a random source unit A, a failure detection unit B, a chi-square detection unit C, an XOR operation unit D, a hash operation unit E, an output result unit F, and a status control unit G.

[0036] The random source unit A is used to enable the random number generation function and to turn on and off the corresponding failure detection and chi-square detection functions of the random number generation function.

[0037] Failure detection unit B is used to continuously collect random source generation data from random source unit A, and determine the passage status of the detection signal based on whether the collected random source generation data is all 0 or all 1; and send the random source generation data that has passed the detection to chi-square detection unit C.

[0038] Chi-square detection unit C is used to calculate the proportion of values ​​appearing in the random source-generated data detected by failure detection unit B using the chi-square detection algorithm, and to determine the passing status of the detection signal based on the value; and to send the passing detection signal to XOR operation unit D;

[0039] The XOR operation unit D is used to continuously collect random source generated data detected by the chi-square detection unit C, perform XOR operation on the specified random source generated data, and output the operation result.

[0040] The hash operation unit E is used to continuously collect the XOR operation output results, process the XOR operation output result data using a hash algorithm, and output the processed result.

[0041] The output result unit F is used to store the result data processed by the hash operation unit E;

[0042] The status control unit G is used to receive user commands, configure the random source reset or enable switch, record the detection results of each failure detection and chi-square detection unit, configure the random source selection sequence number of the XOR operation unit, configure the enable switch and random number generation command of the hash operation unit, and record the reading status of the output results.

[0043] For example, random source unit A is a random number generator, which can be a true random number generator (i.e., a physical random source) or a pseudo random number generator. When the random source unit is enabled, the random number generation function is enabled, and the corresponding failure detection and chi-square detection functions are enabled; when the random source unit is disabled, the random number generation function is disabled, and the corresponding failure detection and chi-square detection functions are disabled.

[0044] Failure detection unit B collects 32-bit data generated continuously by the corresponding random source as a set. If the collected set of data is all 0 or all 1, it outputs a high-level signal to the status control unit G, indicating that the detection has failed; if the collected set of data is not all 0 and not all 1 (i.e., not a detection failure), it outputs a low-level signal to the status control unit G, indicating that the detection has passed.

[0045] The chi-square detection unit C calculates the proportion of values ​​appearing in random data using the chi-square detection algorithm. The specific operation employed in this invention is as follows: continuously collect generated data from the corresponding random source, grouping them into sets of 512 bits. Record the values ​​of every consecutive 4 bits (i.e., 0 to 15) in each set, and statistically analyze the frequency of each value using the formula T = (fr(i) - Ei). 2 / Ei calculates T, where i is 0 to 15, fr(i) is the frequency of the corresponding value, and Ei is the expected value (8 in this example). If the T value of two consecutive sets of data is greater than 65, a detection failure signal is output; if the T value of two consecutive sets of data is greater than 65 in only one set, a warning signal is output; if the T value of two consecutive sets of data is not greater than 65, a detection pass signal is output.

[0046] The XOR operation unit D continuously collects data generated by a specified random source. The data generated by the random source is grouped into 32-bit sets, and the XOR operation is performed on each group of 32-bit data, and the result is output. If the number of random sources selected is 0, the XOR operation unit does not work; if the number of random sources selected is 1, the XOR operation unit directly outputs the generated data from that random source.

[0047] The hash operation unit E continuously collects the XOR operation output results and processes the collected data using a hash algorithm. Specifically, the operation in this invention is as follows: 128 bits of the XOR operation output results are continuously collected, and the SM3 hash algorithm is used to perform the operation, outputting a 256-bit result. When the hash operation unit is enabled, the SM3 operation result is output; when the hash operation unit is disabled, the XOR operation output result is directly output.

[0048] The output result unit F contains the result data after storage and processing. This invention uses a storage structure of 16 32-bit registers and uses a 16-bit one-hot code (0 indicates that the data has been read, and 1 indicates that the data has been newly generated) to mark the state of each register (for example, when all data is newly generated, it is marked as 16'b11111111111111111, and when the first group of data is read, it is marked as 16'b11111111111111110).

[0049] Example 2, as Figure 2 As shown, the random number post-processing method for SoC chips provided in this embodiment of the invention includes:

[0050] S1: After the SoC chip is powered on or reset, the random source unit and hash operation unit are enabled by default, and the XOR operation unit selects all random sources by default. After that, the status control unit reconfigures the enable switch and random source selection sequence number of the random source unit and hash operation unit according to the user command.

[0051] S2: The failure detection unit and the chi-square detection unit collect and detect the random numbers generated by the corresponding random sources, and report the detection results to the status control unit. When the failure detection result is a failure, the status control unit disables the corresponding random source. When the chi-square detection result is a warning, the status control unit resets the corresponding random source.

[0052] S3: The XOR operation unit selects the data generated by the corresponding random source according to the random source selection number configured by the state control unit (random sources in the closed state cannot be selected), and performs the operation on the selected random source data and outputs it.

[0053] S4: The hash operation unit continuously collects the output results of the XOR operation unit and performs the operation output; when the hash operation unit is enabled, it is in a stopped working state after completing each round of operation, and starts the next round of operation only after the random number generation command is valid;

[0054] S5: The output result unit collects the output data of the hash operation unit and updates 512 bits each time. At this time, the 16-bit status register is all 1s. After the user reads a 32-bit data, the corresponding status register bit is 0. When the status register is all 0 or the user configures a random number generation command, the status control unit configures the hash operation unit to generate a new random number.

[0055] In step S5, the 512 bits are 16 32-bit data registers. At this time, the status register is marked as 16'b1111111111111111. When the first group of data is read, the corresponding status register bit is marked as 0, that is, 16'b11111111111111110. When the status register is all 0 or the user configures a random number generation command, the status control unit configures the hash operation unit to generate a new random number.

[0056] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0057] The information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0058] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this invention. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments.

[0059] This invention also provides a computer device comprising: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the above-described random number post-processing system function applicable to SoC chips.

[0060] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the above-described random number post-processing system function applicable to SoC chips.

[0061] This invention also provides an information data processing terminal, which, when executed on an electronic device, provides a user input interface to implement the random number post-processing system function applicable to SoC chips as described above. The information data processing terminal is not limited to mobile phones, computers, or switches.

[0062] This invention also provides a server that, when executed on an electronic device, provides a user input interface to implement the random number post-processing system functions applicable to SoC chips as described above.

[0063] This invention provides a computer program product that, when run on an electronic device, enables the electronic device to implement the above-mentioned random number post-processing system function applicable to SoC chips.

[0064] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0065] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by those skilled in the art within the scope of the technology disclosed in the present invention and within the spirit and principles of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A random number post-processing system suitable for a SoC chip, characterized by, The system includes: When the random source unit (A) is enabled or disabled, the random number generation function is enabled or disabled, and the corresponding failure detection and chi-square detection functions are enabled or disabled. The failure detection unit (B) is used to continuously collect random source generation data from the random source unit (A), determine the passage status of the detection signal based on the collected random source generation data, and send the random source generation data to the chi-square detection unit (C). The chi-square detection unit (C) uses the chi-square detection algorithm to calculate the proportion of values ​​appearing in the random source generated data detected by the failure detection unit (B), judges the passing status of the detection signal based on the proportion, and sends the passing detection signal to the XOR operation unit (D). The XOR operation unit (D) is used to continuously collect random source generated data detected by the chi-square detection unit (C), perform XOR operation on the collected random source generated data, and output the operation result. The hash unit (E) is used to continuously collect the XOR operation output results, process the XOR operation output result data using a hash algorithm, and output the processed result. The output result unit (F) is used to store the result data processed by the hash operation unit (E); The status control unit (G) is used to receive user commands, configure the random source reset or enable switch, record the detection results of each failure detection and chi-square detection unit, configure the random source selection sequence number of the XOR operation unit, configure the enable switch and random number generation command of the hash operation unit, and record the reading status of the output results. 2.The random number post-processing system suitable for a SoC chip according to claim 1, wherein, The random source unit (A) employs a random number generator, which may include a true random number generator or a pseudo random number generator. 3.The random number post-processing system suitable for a SoC chip according to claim 1, wherein, The failure detection unit (B) collects 32 bits of data continuously generated by the corresponding random source as a set; if the collected set of data is all 0 or all 1, it outputs a high-level signal to the status control unit (G) to indicate that the detection has failed; if the collected set of data is not all 0 and not all 1, it indicates that the detection has not failed, and it outputs a low-level signal to the status control unit (G) to indicate that the detection has passed. 4.The random number post-processing system suitable for a SoC chip according to claim 1, wherein, In the chi-square detection unit (C), the calculation of the proportion of the values appearing in the random source generated data of the random source unit (A) using the chi-square detection algorithm comprises: recording the values of each continuous 4 bits in each group of the collected random source generated data of the random source unit (A) for each group of 512 bits, counting the frequency of each value, and calculating T using the formula T=(fr(i)-Ei) 2 / Ei, wherein i is 0-15, fr(i) is the frequency of the corresponding value, and Ei is the expected value; if the T values of two consecutive groups of data are both greater than 65, a detection failure signal is output; if the T values of two consecutive groups of data are only one group greater than 65, a warning signal is output; and if the T values of two consecutive groups of data are both not greater than 65, a detection pass signal is output. 5.The random number post-processing system suitable for a SoC chip according to claim 1, wherein, In the XOR operation unit (D), if the number of random sources selected is 0, the XOR operation unit does not work; if the number of random sources selected is 1, the XOR operation unit directly outputs the generated data of the random source. 6.The random number post-processing system suitable for a SoC chip according to claim 1, wherein, In the hash operation unit (E), the process of processing the XOR operation output result data using the hash algorithm includes: continuously collecting 128 bits of the XOR operation output result, performing the operation using the hash algorithm SM3, and outputting a 256-bit operation result.

7. The random number post-processing system suitable for a SoC chip according to claim 6, wherein, When the hash operation unit is enabled, the result of the SM3 operation is output; when the hash operation unit is disabled, the result of the XOR operation is directly output.

8. The random number post-processing system suitable for a SoC chip according to claim 1, wherein, The output result unit (F) uses a storage structure of 16 32-bit registers, and uses a 16-bit one-hot code to mark the status of each register. 0 indicates that the data has been read, and 1 indicates that the data has been newly generated.

9. A random number post-processing method suitable for a SoC chip, characterized by, This method processes the random number post-processing system for SoC chips according to any one of claims 1-8, and the method includes: S1: After the SoC chip is powered on or reset, the random source unit and hash operation unit are enabled by default, and the XOR operation unit selects all random sources by default. After that, the status control unit reconfigures the enable switch and random source selection sequence number of the random source unit and hash operation unit according to the user command. S2: The failure detection unit and the chi-square detection unit collect and detect the random numbers generated by the corresponding random source, and report the detection results to the status control unit; when the failure detection result is a failure, the status control unit disables the corresponding random source; when the chi-square detection result is a warning, the status control unit resets the corresponding random source; when the chi-square detection result is a failure, the status control unit disables the corresponding random source. S3: The XOR operation unit selects the data generated by the corresponding random source according to the random source selection number configured by the state control unit, and performs the operation on the selected random source data and outputs it. S4: The hash operation unit continuously collects the output results of the XOR operation unit, performs the operation and outputs the result; when the hash operation unit is enabled, it stops working after each round of operation and starts the next round of operation only after the random number generation command is valid. S5: The output result unit collects the output data of the hash operation unit and updates 512 bits each time. At this time, the 16-bit status register is all 1s. After the user reads a 32-bit data, the corresponding status register bit is 0. When the status register is all 0 or the user configures a random number generation command, the status control unit configures the hash operation unit to generate a new random number.

10. The random number post-processing method suitable for a SoC chip according to claim 9, characterized by, In step S5, the 512 bits are 16 32-bit data registers. At this time, the status register is marked as 16'b1111111111111111. When the first group of data is read, the corresponding status register bit is marked as 0, i.e., 16'b1111111111111110.

Images