Drive stage circuit, linear voltage regulator and power supply device

Abstract

The application discloses a driving stage circuit, a linear voltage stabilizer and a power supply device, comprising: an NMOS source follower connected between an error amplifier and a control end of a power tube, used for outputting a first driving current to the power tube when turned on; a PMOS source follower connected between the error amplifier and the control end of the power tube, used for outputting a second driving current to the power tube when turned on; and a switching circuit used for comparing a voltage difference between the control end voltage of the power tube and a reference ground with a set threshold value, and complementarily turning on the PMOS source follower and the NMOS source follower according to a comparison result, no matter a load state of the LDO, the driving stage circuit can always select an optimal driving type to drive the power tube, thereby improving a problem that loop stability of a driving stage circuit in the prior art is easily limited by a working voltage range.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, specifically to a driver stage circuit, a linear regulator, and a power supply device. Background Technology

[0002] A low dropout linear regulator (LDO), often simply called a linear regulator, is a power management module widely used in various handheld devices and portable electronic products. The core of an LDO consists of three basic modules: an error amplifier, a driver stage circuit, and a power transistor. The driver stage circuit drives the power transistor and plays a crucial role in improving the LDO's transient response performance and enhancing the overall loop stability.

[0003] Figure 1 A schematic diagram of a driver stage circuit according to the prior art is shown. Figure 1 As shown, in the prior art, the NMOS source follower, consisting of the NMOS transistor Ms and the current source I1, provides drive current to the power transistor. The loop stability of the prior art drive stage circuit is easily limited by the operating voltage range. For example, when the LDO is under light load or the supply voltage Vcc is large, this drive stage circuit may cause the preceding error amplifier to enter the linear region, leading to overall loop abnormalities and affecting loop stability. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a driver stage circuit, a linear regulator, and a power supply device, which improves upon the problem that the capacity of the driver stage circuit in the prior art is easily limited by the operating voltage range, causing the error amplifier in the preceding stage to enter the linear region and resulting in overall loop abnormalities.

[0005] According to one aspect of the present invention, a drive stage circuit for a linear regulator is provided, the drive stage circuit being connected between an error amplifier and a power transistor, comprising: an NMOS source follower connected between the control terminals of the error amplifier and the power transistor, for outputting a first drive current to the power transistor when turned on; a PMOS source follower connected between the control terminals of the error amplifier and the power transistor, for outputting a second drive current to the power transistor when turned on; and a switching circuit connected to the control terminals of the NMOS source follower, the PMOS source follower, and the power transistor respectively, for comparing the voltage difference between the control terminal voltage of the power transistor and a reference ground with a set threshold, and complementaryly turning on the PMOS source follower and the NMOS source follower according to the comparison result.

[0006] Optionally, when the voltage difference is greater than the set threshold, the switching circuit turns on the PMOS source follower and turns off the NMOS source follower; when the voltage difference is less than the set threshold, the switching circuit turns on the NMOS source follower and turns off the PMOS source follower.

[0007] Optionally, the NMOS source follower includes: an NMOS source follower transistor and a first current source connected in series between the power supply voltage and the reference ground, wherein the control terminal of the NMOS source follower transistor is connected to the error amplifier, and the common terminal of the NMOS source follower transistor and the first current source is connected to the control terminal of the power transistor.

[0008] Optionally, the PMOS source follower includes: a second current source and a PMOS source follower transistor connected in series between the switching circuit and the reference ground, the control terminal of the PMOS source follower transistor being connected to the error amplifier, and the common terminal of the second current source and the PMOS source follower transistor being connected to the control terminal of the power transistor.

[0009] Optionally, the switching circuit includes: a first transistor connected between the power supply voltage and the second current source; a third current source connected between the power supply voltage and the control terminal of the first transistor; and a second transistor, a third transistor connected as a MOS diode, and a first resistor located on a first branch between the common terminal of the first transistor and the third current source and the reference ground, wherein the control terminal of the second transistor is connected to the control terminal of the power transistor.

[0010] Optionally, the current provided by the second current source is greater than the current provided by the first current source.

[0011] Optionally, the switching circuit controls the quiescent current of the PMOS source follower transistor and the NMOS source follower transistor by controlling the turn-on or turn-off of the first transistor based on the comparison result of the voltage difference and the preset threshold, so as to complementary turn on the PMOS source follower and the NMOS source follower.

[0012] Optionally, the first transistor and the third transistor are PMOS transistors, and the second transistor is an NMOS transistor.

[0013] According to another aspect of the present invention, a linear regulator is provided, comprising: a power transistor having a current conduction path connected between a power supply voltage and an output voltage; an error amplifier for comparing a feedback voltage of the output voltage with a reference voltage; and a drive stage circuit as described above, the drive stage circuit being connected between the error amplifier and the power transistor, and driving the power transistor according to the output of the error amplifier.

[0014] According to another aspect of the present invention, a power supply device is provided, comprising: the linear regulator described above, the linear regulator being used to convert a power supply voltage into a stable output voltage.

[0015] In summary, the driver stage circuit for a linear regulator in this embodiment includes a PMOS source follower, an NMOS source follower, and a switching circuit. This switching circuit complementaryly switches between the PMOS and NMOS source followers by detecting the voltage margin between the output voltage of the driver stage circuit and the reference ground. Regardless of the LDO's load condition, the driver stage circuit can always select the optimal drive type to drive the power transistor, thereby improving the problem in existing driver stage circuits where the capacity is easily limited by the operating voltage range, causing the preceding error amplifier to enter the linear region and resulting in overall loop abnormalities. Attached Figure Description

[0016] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0017] Figure 1 A schematic structural diagram of a driver stage circuit according to the prior art is shown.

[0018] Figure 2 A schematic circuit diagram of a drive stage circuit for a linear regulator provided according to a first embodiment of the present invention is shown.

[0019] Figure 3 A schematic circuit diagram of a linear regulator provided according to a second embodiment of the present invention is shown. Detailed Implementation

[0020] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0022] In this application, the power transistor is a transistor operating in linear mode to provide a current path, including a type selected from bipolar transistors or field-effect transistors. The first and second terminals of the power transistor are respectively a high-potential terminal and a low-potential terminal on the current path, and the control terminal is used to receive a control signal to control the voltage drop of the power transistor. The power transistor can be a PMOS transistor or an NMOS transistor. For a PMOS transistor, the first, second, and control terminals are the source, drain, and gate, respectively; for an NMOS transistor, the first, second, and control terminals are the drain, source, and gate, respectively.

[0023] The present invention will now be described in detail with reference to the accompanying drawings.

[0024] Figure 2 A schematic circuit diagram of a drive stage circuit 100 for a linear regulator according to a first embodiment of the present invention is shown. Figure 2 As shown, the driver stage circuit 100 is connected between the output of the error amplifier and the control terminal of the power transistor. It provides a drive current to the power transistor based on the output of the error amplifier to drive the power transistor. The driver stage circuit 100 includes an NMOS source follower 110, a PMOS source follower 120, and a switching circuit 130. The NMOS source follower 110 is connected between the power supply voltage Vcc and a reference ground. Its input terminal is connected to the output of the error amplifier at node A, and its output terminal is connected to the control terminal of the power transistor at node B. The NMOS source follower 110 provides a first drive current to the power transistor when it is turned on. The PMOS source follower 120 is connected between the switching circuit 130 and the reference ground. Its input terminal is connected to the output of the error amplifier at node A, and its output terminal is connected to the control terminal of the power transistor at node B. The PMOS source follower 120 provides a second drive current to the power transistor when it is turned on. The switching circuit 130 is connected to the NMOS source follower 110, the PMOS source follower 120 and the control terminal of the power transistor, respectively, and is used to compare the voltage difference between the control terminal voltage of the power transistor (that is, the voltage at node B) and the reference ground with a set threshold, and complementaryly turn on the PMOS source follower 120 and the NMOS source follower 110 according to the comparison result.

[0025] Furthermore, the switching circuit 130 is configured to turn on the PMOS source follower 120 and turn off the NMOS source follower 110 when the margin between node B and the reference ground is sufficient, i.e., the voltage difference between them is greater than the set threshold. The switching circuit 130 is also configured to turn on the NMOS source follower 110 and turn off the PMOS source follower 120 when the margin between node B and the reference ground is insufficient, i.e., the voltage difference between them is less than the set threshold.

[0026] Furthermore, the switching circuit 130 is configured to control the quiescent operating current of the NMOS source follower 110 and the PMOS source follower 120 by comparing the difference between the node B and the reference ground with the set threshold, so as to complementary turn on the NMOS source follower 110 and the PMOS source follower 120.

[0027] Furthermore, the NMOS source follower 110 includes an NMOS source follower transistor Mn1 and a current source I1. The NMOS source follower transistor Mn1 and the current source I1 are connected in series between the power supply voltage Vcc and the reference ground. The gate of the NMOS source follower transistor Mn1 serves as the input terminal of the NMOS source follower 110 and is connected to node A. The common terminal of the source of the NMOS source follower transistor Mn1 and the current source I1 serves as the output terminal of the NMOS source follower 110 and is connected to node B.

[0028] The PMOS source follower 120 includes a PMOS source follower transistor Mp1 and a current source I2. The current source I2 and the PMOS source follower transistor Mp1 are connected in series between the switching circuit 130 and the reference ground. The gate of the PMOS source follower transistor Mp1 serves as the input terminal of the PMOS source follower 120 and is connected to node A. The common terminal of the current source I2 and the source of the PMOS source follower transistor Mp1 serves as the output terminal of the PMOS source follower 120 and is connected to node B.

[0029] The switching circuit 130 includes a PMOS transistor Mp2, a PMOS transistor Mp3, an NMOS transistor Mn2, a current source I3, and a resistor R3. The PMOS transistor Mp2 is connected between the power supply voltage Vcc and the current source I2. The source of the PMOS transistor Mp2 is connected to the power supply voltage Vcc, and the drain of the PMOS transistor Mp2 is connected to the current source I2. The first terminal of the current source I3 is connected to the power supply voltage Vcc, and the second terminal of the current source I3 is connected to the gate of the PMOS transistor Mp2. The NMOS transistor Mn2, the PMOS transistor Mp3, and the resistor R3 are located on a branch between the gate of the PMOS transistor Mp2, the common terminal of the current source I3, and the reference ground. The drain of the NMOS transistor Mn2 is connected to the common node D of the current source I3 and the PMOS transistor Mp2, the gate of the NMOS transistor Mn2 is connected to node B, and the source of the NMOS transistor Mn2 is connected to the source of the PMOS transistor Mp3. PMOS transistor Mp3 is configured as a MOS diode, meaning the gate and drain of PMOS transistor Mp3 are connected to each other. The first terminal of resistor R3 is connected to the gate and drain of PMOS transistor Mp3 at node C, and the second terminal of resistor R3 is connected to the reference ground.

[0030] The switching circuit 130 controls the static operating current of the PMOS source follower transistor Mp1 and the NMOS source follower transistor Mn1 by controlling the turn-on or turn-off of the PMOS transistor Mp2 based on the comparison result of the voltage difference between node B and the reference ground and a preset threshold, so as to complementary turn on the PMOS source follower 120 and the NMOS source follower 110.

[0031] In this embodiment, the current Ic on the branch between node D and the reference ground is V. C / R3, where V C Let R be the voltage at node C, and R3 be the resistance value of resistor R3. The voltage at node C can be obtained from node B, NMOS transistor Mn2, and PMOS transistor Mp3, that is:

[0032] V C =V B ―Vgs Mn2 ―Vgs Mp3 (1)

[0033] According to formula (1), when the voltage difference between node B and the reference ground is greater than the preset threshold, the current Ic on the branch between node D and the reference ground is greater than the current provided by current source I3, and the voltage V at node D is greater. DWhen Vcc < Vcc, PMOS transistor Mp2 is turned on. At this time, the static operating current of NMOS source follower transistor Mn1 is equal to I1-I2, and the static operating current of PMOS source follower transistor Mp1 is equal to I2-I1. Furthermore, in this embodiment, the current provided by current source I2 is set to be greater than the current provided by current source I1. Therefore, the static operating current of NMOS source follower transistor Mn1, I1-I2 < 0, meaning NMOS source follower 110 is turned off; the static operating current of PMOS source follower transistor Mp1, I2-I1 > 0, meaning PMOS source follower 120 is turned on.

[0034] When the voltage difference between node B and the reference ground is less than a preset threshold, the current Ic on the branch between node D and the reference ground is less than the current supplied by current source I3, and the voltage V at node D is less than the voltage V. D =Vcc, PMOS transistor Mp2 is turned off. At this time, the static operating current of PMOS source follower transistor Mp1 is equal to 0, that is, PMOS source follower 120 is turned off, while the static operating current of NMOS source follower transistor Mn1 is greater than 0, that is, NMOS source follower 110 is turned on.

[0035] Furthermore, in this embodiment, the current at node B is connected to node D via the common-source NMOS transistor Mn2, while the current at node D is fed back to node B via the common-source PMOS transistor Mp2, thus forming a small positive feedback loop between node B and node D. Therefore, in the driver stage circuit 100 of this embodiment, there is no situation where both the NMOS source follower 110 and the PMOS source follower 120 are not working. Regardless of the load state of the LDO, the switching circuit 130 can select an optimal driver type to drive the power transistor.

[0036] In this embodiment, compared with the NMOS source follower 110, the PMOS source follower 120 has a better transient response and will make the power supply rejection ratio (PSRR) of the system better. Therefore, in this embodiment, under the condition that the margin of node B allows, the PMOS source follower 120 is driven first and designed as the default drive type, so that the drive stage circuit 100 can achieve a better driving effect.

[0037] Figure 3 A schematic circuit diagram of a linear voltage regulator provided according to an embodiment of the present invention is shown. Figure 3 As shown, the linear regulator 200 in this embodiment includes a power transistor Mpwr, an error amplifier 210, a driver stage circuit 220, and a resistor divider network.

[0038] In this chip, the power transistor Mpwr is the main output transistor, having a current conduction path coupled between the power supply voltage Vcc and the output voltage Vout, as well as a control terminal that receives the gate drive signal GATE. In this embodiment, the power transistor Mpwr is a PMOS transistor, with its first terminal (where the first terminal is the source and the second terminal is the drain) coupled to the power supply voltage Vcc, and its second terminal coupled to the output terminal of the output voltage Vout. The control terminal of the power transistor Mpwr (e.g., the gate of the MOS transistor) is coupled to the gate drive signal GATE. The power transistor Mpwr is mainly used to provide the output voltage Vout to the downstream load according to the power supply voltage Vcc provided by the power supply terminal, thereby driving the load resistor and load capacitor outside the chip.

[0039] In other embodiments, the power transistor Mpwr can also be other types of transistors, such as NMOS transistors, NPN Darlington transistors, and NPN bipolar transistors.

[0040] A resistor divider network consisting of resistors R1 and R2 is coupled between the output terminal of the output voltage Vout and ground. This network samples and divides the output voltage Vout to obtain the feedback voltage VFB, which is provided by the node between resistors R1 and R2. Error amplifier 210 compares the feedback voltage VFB with the reference voltage VREF to obtain an output signal characterizing the difference between the two. This output signal is used to adjust the conduction level of the power transistor Mpwr, thereby stabilizing the output voltage Vout. Although Figure 3 The embodiment shown employs an error amplifier 210, but those skilled in the art will recognize that other suitable analog or digital circuits are equally applicable, as long as they can achieve the error amplification function. The driver stage circuit 220 is connected between the output of the error amplifier 210 and the control terminal of the power transistor Mpwr, and is used to generate the gate drive signal GATE based on the output of the error amplifier 210 to drive the power transistor Mpwr.

[0041] Furthermore, the driving stage circuit 220 can be implemented by the driving stage circuit 100 provided in the first embodiment of the present invention. The driving stage circuit 100 can adaptively select a PMOS source follower or an NMOS source follower to drive the power transistor according to the load state of the LDO. This improves the problem that the capacity of the driving stage circuit in the prior art is easily limited by the operating voltage range, causing the error amplifier of the front stage to enter the linear region and resulting in an abnormal overall loop.

[0042] The present invention also discloses a power supply device for providing a supply voltage. The power supply device includes a linear regulator as described above to achieve a stable output of the supply voltage.

[0043] In summary, the driver stage circuit for a linear regulator in this embodiment includes a PMOS source follower, an NMOS source follower, and a switching circuit. This switching circuit complementaryly switches between the PMOS and NMOS source followers by detecting the voltage margin between the output voltage of the driver stage circuit and the reference ground. Regardless of the LDO's load condition, the driver stage circuit can always select the optimal drive type to drive the power transistor, thereby improving the problem in existing driver stage circuits where the capacity is easily limited by the operating voltage range, causing the preceding error amplifier to enter the linear region and resulting in overall loop abnormalities.

[0044] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A driver stage circuit for a linear regulator, the driver stage circuit being connected between an error amplifier and a power transistor, comprising: An NMOS source follower is connected between the error amplifier and the control terminal of the power transistor, and is used to output a first drive current to the power transistor when it is turned on. A PMOS source follower is connected between the error amplifier and the control terminal of the power transistor, and is used to output a second drive current to the power transistor when it is turned on. as well as A switching circuit, connected to the control terminals of the NMOS source follower, the PMOS source follower, and the power transistor, compares the voltage difference between the control terminal voltage of the power transistor and the reference ground with a set threshold, and accordingly enables the PMOS and NMOS source followers. The NMOS source follower includes: an NMOS source follower transistor and a first current source connected in series between the power supply voltage and the reference ground; the control terminal of the NMOS source follower transistor is connected to the error amplifier; and the common terminal of the NMOS source follower transistor and the first current source is connected to the control terminal of the power transistor. The PMOS source follower includes: a second current source and a PMOS source follower transistor connected in series between the switching circuit and the reference ground; the control terminal of the PMOS source follower transistor is connected to the error amplifier; and the common terminal of the second current source and the PMOS source follower transistor is connected to the control terminal of the power transistor. The switching circuit includes: a first transistor connected between the power supply voltage and the second current source; a third current source connected between the power supply voltage and the control terminal of the first transistor; and a second transistor, a third transistor connected as a MOS diode, and a first resistor located on a first branch between the common terminal of the first transistor and the third current source and the reference ground, wherein the control terminal of the second transistor is connected to the control terminal of the power transistor.

2. The driving stage circuit according to claim 1, wherein, When the voltage difference exceeds the set threshold, the switching circuit activates the PMOS source follower and deactivates the NMOS source follower. When the differential pressure is less than the set threshold, the switching circuit turns on the NMOS source follower and turns off the PMOS source follower.

3. The driving stage circuit according to claim 2, wherein, The current provided by the second current source is greater than the current provided by the first current source.

4. The driving stage circuit according to claim 3, wherein, The switching circuit controls the quiescent current of the PMOS source follower transistor and the NMOS source follower transistor by controlling the turn-on or turn-off of the first transistor based on the comparison result of the voltage difference and the set threshold, so as to complementary turn on the PMOS source follower and the NMOS source follower.

5. The driver stage circuit according to claim 1, wherein, The first transistor and the third transistor are PMOS transistors, and the second transistor is an NMOS transistor.

6. A linear regulator, comprising: A power transistor has a current conduction path connecting the supply voltage and the output voltage; An error amplifier is used to compare the feedback voltage of the output voltage with a reference voltage; as well as The driver stage circuit according to any one of claims 1-5, wherein the driver stage circuit is connected between the error amplifier and the power transistor, and drives the power transistor according to the output of the error amplifier.

7. A power supply device, comprising: The linear regulator as described in claim 6 is used to convert a power supply voltage into a stable output voltage.

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