Display panel and display device

Abstract

A display panel includes a display area and a border area surrounding the display area. The display panel includes: a substrate; a plurality of edge sub-pixels (1) located on the substrate, the plurality of edge sub-pixels (1) being located at the edge of the display area and close to the border area, the edge sub-pixels (1) including an anode pattern (10); a first initialization signal bus (3) located on the substrate, at least a portion of the first initialization signal bus (3) being located in the display area; wherein the orthographic projection of the anode pattern (10) on the substrate and the orthographic projection of the first initialization signal bus (3) on the substrate have a first overlapping area.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and a display device. Background Technology

[0002] With the development of ultra-narrow bezels in AMOLED (Active-matrix Organic Light-emitting Diode) display panels, the market demand for the design of peripheral circuits for display panels is increasing. At the same time, the quality requirements for multi-angle color shift in displays are also growing. Summary of the Invention

[0003] The present invention provides a display panel and a display device that can avoid redundant pixels occupying space.

[0004] To address the aforementioned technical problems, embodiments of the present invention provide the following technical solutions:

[0005] A first aspect of the present invention provides a display panel including a display area and a border area located on one side of the display area. The display panel includes: a substrate; a plurality of edge sub-pixels located on the substrate, the plurality of edge sub-pixels being located at the edge of the display area and close to the border area, the edge sub-pixels including an anode pattern; a first initialization signal bus located on the substrate, at least a portion of the first initialization signal bus being located in the display area; wherein the orthographic projection of the anode pattern on the substrate and the orthographic projection of the first initialization signal bus on the substrate have a first overlapping area.

[0006] Optionally, the display panel further includes a first source / drain metal layer located between the substrate and the anode pattern, wherein the first initialization signal bus is fabricated using the first source / drain metal layer.

[0007] Optionally, the display panel further includes: a power signal line, at least one edge sub-pixel including an edge sub-pixel driving circuit, the power signal line being used to provide a power supply voltage to the edge sub-pixel driving circuit, the power signal line being fabricated using the first source / drain metal layer, and the orthographic projection of the anode pattern on the substrate and the orthographic projection of the power signal line on the substrate having a second overlapping area.

[0008] Optionally, the first overlapping region and the second overlapping region are located on opposite sides of the anode pattern.

[0009] Optionally, the ratio of the area of ​​the first overlapping region to the area of ​​the second overlapping region is 0.8-1.2.

[0010] Optionally, the display panel further includes a second initialization signal bus located on the substrate, the second initialization signal bus being located in the border area and on the side of the first initialization signal bus away from the edge sub-pixel.

[0011] Optionally, the edge sub-pixel driving circuit includes at least a first transistor and a seventh transistor, one of which is coupled to the first initialization signal bus; the other of which is coupled to the second initialization signal bus.

[0012] Optionally, the second initialization signal bus is disposed in the same layer and made of the same material as the first initialization signal bus.

[0013] Optionally, the edge sub-pixel further includes: a pixel definition opening located on the side of the anode pattern away from the substrate, the pixel definition opening corresponding to the anode pattern, and the area of ​​the pixel definition opening being smaller than the area of ​​the anode pattern.

[0014] Optionally, the orthographic projection of the pixel definition opening on the substrate and the orthographic projection of the first initialization signal bus on the substrate have a third overlapping region, the area of ​​the third overlapping region being smaller than the area of ​​the first overlapping region.

[0015] Optionally, the orthographic projection of the pixel definition opening on the substrate does not overlap with the orthographic projection of the first initialization signal bus on the substrate.

[0016] Optionally, the display panel further includes: a first data line, the first data line being used to provide data voltage to the edge sub-pixel driving circuit, the first data line being made using the first source-drain metal layer and located between the power signal line and the first initialization signal bus, the orthographic projection of the first data line on the substrate overlapping the orthographic projection of the anode pattern on the substrate.

[0017] Optionally, the display surface further includes: a virtual data line located between the first data line and the first initialization signal bus, wherein the orthographic projection of the virtual data line on the substrate overlaps with the orthographic projection of the anode pattern on the substrate.

[0018] Optionally, the spacing between the virtual data line and the first initialization signal bus is 3μm-7μm, and the spacing between the first initialization signal bus and the second initialization signal bus is 5μm-30μm.

[0019] Optionally, the line width of the first initialization signal bus is 30μm-40μm; the line width of the second initialization signal bus is 30μm-40μm.

[0020] Optionally, the anode pattern includes a main body portion and an auxiliary portion that are coupled to each other, wherein the center point of the pixel-defined opening coincides with the center point of the main body portion of the anode pattern.

[0021] Optionally, the first data line and the virtual data line are located on opposite sides of the center point of the anode pattern.

[0022] Optionally, the display panel further includes a second planarization layer located between the anode pattern and the first source / drain metal layer, the planarization layer serving to planarize the anode pattern and the first source / drain metal layer.

[0023] Optionally, the display panel includes a plurality of sub-pixels, the plurality of sub-pixels being arranged in an RGBG manner, and the edge sub-pixels being G pixels located at the edge of the display area and close to the border area.

[0024] Optionally, the arrangement of the plurality of sub-pixels may also include: GGRB, diamond, S-RGB, or Delta.

[0025] Optionally, the display panel further includes a second source / drain metal layer located on the substrate, wherein the first initialization signal bus is fabricated using the second source / drain metal layer.

[0026] Optionally, the display panel further includes a GOA circuit located in the bezel area, wherein the orthographic projection of the anode pattern on the substrate and the orthographic projection of the GOA circuit on the substrate have a fourth overlapping area.

[0027] A second aspect of the present invention provides a display device including the display panel described above.

[0028] The embodiments of the present invention have the following beneficial effects:

[0029] The embodiments of the present invention improve the flatness of the light-emitting area and enhance display uniformity while reducing the bezel size by using a first initialization signal bus to replace the power signal lines of redundant pixels to raise the anode pattern at the edge of the display area. Attached Figure Description

[0030] Figure 1 This is a schematic diagram illustrating how redundant sub-pixels are used to raise the anode of edge sub-pixels in related technologies.

[0031] Figure 2This is a schematic diagram of raising the anode using a first initialization signal bus, provided by an embodiment of the present invention.

[0032] Figure 3 This is a schematic diagram of the layout of the first source / drain metal layer provided in an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the layout of the anode pattern provided in an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the layout of pixel-defined openings provided in an embodiment of the present invention;

[0035] Figure 6 A circuit diagram of an edge sub-pixel driving circuit provided in an embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram showing the coverage area of ​​the vapor deposition mask for the organic light-emitting functional layer provided in an embodiment of the present invention.

[0037] Figure Labels

[0038] 1. Edge sub-pixel

[0039] 2 Redundant subpixels

[0040] 10. Anode Pattern

[0041] 20 pixels define the aperture

[0042] 3 First Initialization Signal Bus

[0043] 4 Second Initialization Signal Bus

[0044] 5 Power signal lines

[0045] 6 First data cable

[0046] 7. Virtual data cable

[0047] 1011 Main Body

[0048] 1021 Auxiliary Section

[0049] 10 - First scan line; 12 - Second scan line; 13 - Second initialization signal line

[0050] 14-First reset signal line; 15-First initialization signal line; 17-Light emission control signal line; 18-Second reset signal line

[0051] 1031 Conductive connection part

[0052] S1 - First dividing line

[0053] S2 - Second dividing line

[0054] S3 - Third Boundary Line

[0055] S4 - Fourth Boundary Line

[0056] 101 Anode Square Hole Detailed Implementation

[0057] To make the technical problems, technical solutions and advantages of the embodiments of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0058] As research into pixel stacking deepens, those skilled in the art have discovered a correlation between color shift specifications and the flatness of pixel apertures, primarily related to the flatness of the anode. The anode is located on the upper layers of the pixel stack, and while its shape follows a periodic pattern with the pixel circuit stack, it becomes uneven due to the fluctuations in the pixel circuitry. The thicker layers in the backplane circuitry have the greatest impact on this fluctuation. For example, in single-source-drain (SD) products, the SD film layer in the backplane circuitry is relatively thick, and its traces are located below the anode pixel aperture, thus affecting flatness. In dual-SD products, while the first flattening layer (PLN1) flattens the fluctuations generated by the first source-drain metal layer (SD1) to a certain extent, the main influencing factor is the second source-drain metal layer (SD2).

[0059] In particular, in related technologies, one or more columns of redundant subpixels are usually set at the edge of the display area to ensure the flatness of the edge subpixel anode. However, setting redundant subpixels occupies the space of the display panel, which is not conducive to narrow bezel design.

[0060] Embodiments of the present invention provide a display panel and a display device that, by eliminating redundant sub-pixels, can prevent redundant pixels from occupying space on the display panel.

[0061] An embodiment of the present invention provides a display panel including a display area and a border area surrounding the display area. The display panel includes: a substrate; a plurality of edge sub-pixels located on the substrate, the plurality of edge sub-pixels being located at the edge of the display area and close to the border area, the edge sub-pixels including an anode pattern; a first initialization signal bus located on the substrate, at least a portion of the first initialization signal bus being located in the display area; wherein the orthographic projection of the anode pattern on the substrate and the orthographic projection of the first initialization signal bus on the substrate have a first overlapping area.

[0062] The embodiments of the present invention improve the flatness of the light-emitting area by using a first initialization signal bus to replace the power signal lines of redundant pixels to raise the anode pattern at the edge of the display area, thereby improving the uniformity of the display and reducing the bezel size.

[0063] Figure 2 This is a schematic diagram illustrating the use of a first initialization signal bus to elevate the anode, as provided in an embodiment of the present invention. Figure 2 As shown, the display panel includes a display area and a border area located on one side of the display area. The display panel includes: a substrate; a plurality of edge sub-pixels 1 located on the substrate, the plurality of edge sub-pixels 1 being located at the edge of the display area and close to the border area, the edge sub-pixels 1 including an anode pattern 10; a first initialization signal bus 3 located on the substrate, at least a portion of the first initialization signal bus 3 being located in the display area; wherein, the orthographic projection of the anode pattern 10 on the substrate and the orthographic projection of the first initialization signal bus 3 on the substrate have a first overlapping area.

[0064] In some embodiments, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be one or more of glass and quartz, while the flexible substrate may be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, among others.

[0065] In some embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0066] In some embodiments, the display panel includes a rectangular display area and a border area surrounding the display area. The border area includes a top border area, a bottom border area, a left border area, a right border area, and four corner areas connecting the top border area, the bottom border area, the left border area, and the right border area. The wiring layout structures of the top border area, the bottom border area, the left border area, and the right border area are substantially the same. The wiring layout structures of the four corner areas are also substantially the same.

[0067] like Figure 1 , Figure 2 and Figure 6 As shown by the first dividing line S1, the boundary of the anode pattern defines the boundary of the display area.

[0068] In some embodiments, the display panel includes a plurality of sub-pixels, which are divided into multiple rows of sub-pixels and multiple columns of sub-pixels, wherein the plurality of edge sub-pixels are the sub-pixels included in the column of sub-pixels that is closest to the right edge or the left edge of the column of sub-pixels.

[0069] Each sub-pixel includes a corresponding sub-pixel driving circuit, and the multiple sub-pixel driving circuits are arranged in an array. The multiple sub-pixel driving circuits are divided into multi-row sub-pixel driving circuits and multi-column sub-pixel driving circuits.

[0070] As an example, Figure 2 The edge subpixels are located near the right frame area of ​​the display panel.

[0071] The anode pattern is located in the anode layer, which includes multiple anode patterns. The multiple anode patterns are spaced apart, and each anode pattern is located within a sub-pixel region.

[0072] In some embodiments, the anode layer comprises a first transparent conductive layer, a metal layer, and a second transparent conductive layer sequentially stacked in a direction away from the substrate. The transparent conductive layer may be indium tin oxide (ITO) or indium zinc oxide (IZO).

[0073] In some embodiments, the first initialization signal bus is coupled to the first initialization signal line or the second initialization signal line of the sub-pixel driving circuit, and is used to provide a first initialization signal or the second initialization signal to the sub-pixel driving circuit included in each sub-pixel of the display panel.

[0074] In related technologies, the first initialization signal bus is located in the border area and on the side of the redundant sub-pixel away from the edge sub-pixel.

[0075] pass Figure 1 and Figure 2 As can be seen, the embodiments of the present invention eliminate redundant sub-pixels and shift the first initialization signal bus to the position of the redundant sub-pixels.

[0076] like Figure 1 and Figure 2 As shown, the orthographic projection of the anode pattern 10 on the substrate and the orthographic projection of the first initialization signal bus 3 on the substrate have a first overlapping area. That is, the anode pattern 10 is raised by the first initialization signal bus to make the anode pattern flatter. If the anode pattern is not flat, the light-emitting area corresponding to the anode pattern will not be flat, which will lead to a certain degree of color shift, that is, the colors on the left and right sides of the same light-emitting area are different.

[0077] Optionally, the display panel further includes a first source / drain metal layer located between the substrate and the anode pattern, wherein the first initialization signal bus is fabricated using the first source / drain metal layer.

[0078] The first initialization signal bus provided in this embodiment of the invention is made of a first source-drain metal layer, which can reduce the number of film layers in the display panel and reduce the complexity of the process.

[0079] In some embodiments, the display panel further includes a first source / drain metal layer located between the substrate and the anode pattern 10, wherein the first initialization signal bus 3 is fabricated using the first source / drain metal layer.

[0080] In some embodiments, the first source / drain metal layer can be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. The first source / drain metal layer can be a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. The thickness of the first source / drain metal layer is approximately...

[0081] Optionally, the display panel further includes: a power signal line, at least one edge sub-pixel including an edge sub-pixel driving circuit, the power signal line being used to provide a power supply voltage to the edge sub-pixel driving circuit, the power signal line being fabricated using the first source / drain metal layer, and the orthographic projection of the anode pattern on the substrate and the orthographic projection of the power signal line on the substrate having a second overlapping area.

[0082] In this embodiment of the invention, by having a second overlapping area between the orthogonal projection of the anode pattern on the substrate and the orthogonal projection of the power signal line on the substrate, the anode pattern can be raised using the power signal line.

[0083] refer to Figure 2 and Figure 3 The power signal line 5 is fabricated using a first source / drain metal layer. At least a portion of the power signal line 5 extends along a second direction.

[0084] Optionally, the first overlapping region and the second overlapping region are located on opposite sides of the anode pattern.

[0085] In embodiments of the present invention, by positioning the first overlapping region and the second overlapping region on opposite sides of the anode pattern, the left and right corners of the anode pattern are raised, preventing asymmetrical raising of the anode pattern and different tilt angles on the left and right sides, which would lead to color shift.

[0086] Optionally, the ratio of the area of ​​the first overlapping region to the area of ​​the second overlapping region is 0.8-1.2.

[0087] In embodiments of the present invention, by making the ratio of the area of ​​the first overlapping region to the area of ​​the second overlapping region 0.8-1.2, the area of ​​the left and right corners of the anode pattern that is padded is approximately equal, so that the color deviation on the left and right sides of the anode pattern is consistent and the displayed color is more uniform.

[0088] Optionally, the display panel further includes a second initialization signal bus located on the substrate, the second initialization signal bus being located in the border area and on the side of the first initialization signal bus away from the edge sub-pixel.

[0089] In embodiments of the present invention, a second initialization signal bus is provided together with the first initialization signal bus to provide initialization signals for the edge sub-pixel driving circuit.

[0090] Optionally, the edge sub-pixel driving circuit includes at least a first transistor and a seventh transistor, one of which is coupled to the first initialization signal bus; the other of which is coupled to the second initialization signal bus.

[0091] The embodiments of the present invention can provide different initialization signals for the first transistor and the seventh transistor by setting a first initialization signal bus and a second initialization signal bus.

[0092] Optionally, the second initialization signal bus is disposed in the same layer and made of the same material as the first initialization signal bus.

[0093] The second initialization signal bus provided in this embodiment of the invention is set in the same layer and material as the first initialization signal bus, that is, the second initialization signal bus is also made of the first source and drain metal layer, which can reduce the number of film layers of the display panel and reduce the complexity of the process.

[0094] It should be noted that the term "same layer" refers to a layer structure formed by using the same film deposition process to create a film layer for forming a specific pattern, and then using the same photomask to form a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0095] Optionally, the edge sub-pixel further includes: a pixel definition opening located on the side of the anode pattern away from the substrate, the pixel definition opening corresponding to the anode pattern, and the area of ​​the pixel definition opening being smaller than the area of ​​the anode pattern.

[0096] The pixel definition opening in the embodiments of the present invention defines the effective light-emitting area of ​​the pixel.

[0097] Optionally, the orthographic projection of the pixel definition opening on the substrate and the orthographic projection of the first initialization signal bus on the substrate have a third overlapping region, the area of ​​the third overlapping region being smaller than the area of ​​the first overlapping region.

[0098] Optionally, the orthographic projection of the pixel definition opening on the substrate does not overlap with the orthographic projection of the first initialization signal bus on the substrate.

[0099] In embodiments of the present invention, the pixel definition opening may or may not be raised by the first initialization signal bus.

[0100] Optionally, the display panel further includes: a first data line, the first data line being used to provide data voltage to the edge sub-pixel driving circuit, the first data line being made using the first source-drain metal layer and located between the power signal line and the first initialization signal bus, the orthographic projection of the first data line on the substrate overlapping the orthographic projection of the anode pattern on the substrate.

[0101] In embodiments of the present invention, by making the orthographic projection of the first data line on the substrate overlap with the orthographic projection of the anode pattern on the substrate, the first data line can be raised above the central portion of the anode pattern.

[0102] Optionally, the display panel further includes: a virtual data line located between the first data line and the first initialization signal bus, wherein the orthographic projection of the virtual data line on the substrate overlaps with the orthographic projection of the anode pattern on the substrate.

[0103] In embodiments of the present invention, by making the orthographic projection of the virtual data line on the substrate overlap with the orthographic projection of the anode pattern on the substrate, the virtual data line can be raised above the central portion of the anode pattern.

[0104] It should be noted that the virtual data line does not provide a data voltage signal and is not coupled to the sub-pixel driving circuit.

[0105] In embodiments of the present invention, by positioning the first data line 6 and the virtual data line 7 on opposite sides of the center point of the anode pattern, the height at which the first data line and the virtual data line are raised in the center portion of the anode pattern is symmetrical.

[0106] Both the first data line and the dummy data line are fabricated using a first source / drain metal layer, which is located on the side of the anode pattern closest to the substrate shown. Both the first data line and the dummy data line extend along the second direction D2.

[0107] Optionally, the spacing between the virtual data line and the first initialization signal bus is 3μm-7μm, and the spacing between the first initialization signal bus and the second initialization signal bus is 5μm-30μm.

[0108] The embodiments of the present invention set the spacing between the virtual data line and the first initialization signal bus to be 3μm-7μm, which is a significant reduction compared to the spacing between the virtual data line and the first initialization signal bus in the related art. That is, the first initialization signal bus, which was originally located in the border area, is shifted as a whole in the direction of the display area and occupies the original position of the redundant sub-pixel, which is beneficial to the realization of narrow bezel.

[0109] Optionally, the line width of the first initialization signal bus is 30μm-40μm; the line width of the second initialization signal bus is 30μm-40μm.

[0110] The embodiments of the present invention can ensure the routing on the first initialization signal bus and the second initialization signal bus by setting the line width of the first initialization signal bus and the line width of the second initialization signal bus.

[0111] Optionally, the anode pattern includes a main body portion and an auxiliary portion that are coupled to each other, and the center point of the pixel defining the opening coincides with the center point of the main body portion of the anode pattern.

[0112] The display panel provided in this embodiment of the invention has an auxiliary portion of the anode pattern that enables the main portion of the anode pattern to be coupled to the drain of the light-emitting control transistor.

[0113] In the embodiments of the present invention, the center point of the pixel definition opening of the display panel coincides with the center point of the main body of the anode pattern, so that the flatness of the anode pattern is consistent with the flatness of the pixel definition opening, which can ensure the flatness of the light-emitting area corresponding to the pixel definition opening and avoid color deviation.

[0114] Figure 4 A schematic diagram of the layout of the anode pattern provided in an embodiment of the present invention; as shown Figure 4 As shown, the anode pattern includes a main part 1011 and an auxiliary part 1021, wherein the area of ​​the main part of the B pixel is larger than the area of ​​the main part of the R pixel, and the area of ​​the main part of the R pixel is larger than the area of ​​the main part of the G pixel.

[0115] Figure 5This is a schematic diagram of the layout of pixel-defined openings provided in an embodiment of the present invention; as shown. Figure 5 As shown, the area of ​​the pixel definition opening of pixel B is larger than the area of ​​the pixel definition opening of pixel R, and the area of ​​the main pixel definition opening of pixel R is larger than the area of ​​the pixel definition opening of pixel G.

[0116] Optionally, the display panel further includes a planarization layer located between the anode pattern and the first source / drain metal layer, the planarization layer serving to planarize the area between the anode pattern and the first source / drain metal layer.

[0117] In some embodiments, the planarization layer may be made of organic materials.

[0118] The display panel provided in this embodiment of the invention flattens the first source / drain metal layer by using a planarization layer, making the anode pattern on the first source / drain metal layer flatter.

[0119] Optionally, the display panel includes a plurality of sub-pixels, the plurality of sub-pixels being arranged in an RGBG manner, and the edge sub-pixels being G pixels located at the edge of the display area and close to the border area.

[0120] The display panel provided in this embodiment of the invention has multiple sub-pixels arranged in an RGBG pattern, which can improve display contrast. Specifically, the anodized patterns of the R and B pixels are supported by large metal pads to ensure their flatness; the anodized pattern of the G pixel is supported by a power signal line at its left corner, a first initialization signal bus at its right corner, and a first data line and a virtual data line at its center, ensuring the flatness of the G pixel's anodized pattern.

[0121] Optionally, the arrangement of the plurality of sub-pixels may also include: GGRB, diamond, S-RGB, or Delta.

[0122] The display panel provided in this embodiment of the invention may also have multiple sub-pixels arranged in a manner such as GGRB, diamond, S-RGB or Delta.

[0123] It should be noted that edge sub-pixels are not limited to G pixels. If other pixel arrangements are used, edge sub-pixels can also be R pixels or B pixels.

[0124] The pixel definition aperture defines the effective light-emitting area of ​​the R pixel, B pixel, or G pixel, such as Figure 1 , Figure 2 , Figure 5 and Figure 6 As shown, the effective light-emitting area of ​​pixel B is larger than that of pixel R, and the effective light-emitting area of ​​pixel R is larger than that of pixel G.

[0125] Optionally, the display panel further includes a second source / drain metal layer located on the substrate, wherein the first initialization signal bus is fabricated using the second source / drain metal layer.

[0126] Optionally, the display panel further includes a second source / drain metal layer located on the substrate, wherein the second initialization signal bus is fabricated using the second source / drain metal layer.

[0127] The first initialization signal bus 3 and the second initialization signal bus 4 can be located in either the first source / drain metal layer or the second source / drain metal layer.

[0128] In addition, the orthographic projection of the anode pattern on the substrate can overlap with the orthographic projection of the data bus on the substrate, meaning that the anode pattern can also be raised using the data bus.

[0129] Furthermore, the anode pattern can also be raised using VSS lines.

[0130] Similarly, the first data line 6 and the virtual data line 7 can be located in either the first source-drain metal layer or the second source-drain metal layer. The power signal line 5 can also be located in either the first source-drain metal layer or the second source-drain metal layer.

[0131] In some embodiments, the second source / drain metal layer can be a metal such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or an alloy of these metals. The second source / drain metal layer can be a single-layer structure or a multi-layer structure, such as Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. The thickness of the second source / drain metal layer is approximately...

[0132] It should be noted that the first and second source / drain metal layers are relative concepts, distinguished based on whether the display panel is a dual-SD or single-SD product. In dual-SD products, the first planarization layer (PLN1) smooths out the undulations caused by the first source / drain metal layer (SD1) to a certain extent, and its main influencing factor is the second source / drain metal layer (SD2). In single-source / drain metal layer (SD) products, the SD film layer of the backplane circuit is thicker, and its traces are located below the Anode pixel openings, which has a certain impact on flatness.

[0133] Optionally, the display panel further includes a GOA circuit located in the bezel area, wherein the orthographic projection of the anode pattern on the substrate and the orthographic projection of the GOA circuit on the substrate have a fourth overlapping area.

[0134] The display panel provided in this embodiment of the invention uses a GOA circuit to raise the anode pattern. Since the GOA circuit is located far from the first initialization signal bus on the second initialization signal bus, the bezel can be further narrowed.

[0135] Figure 5 This is a circuit diagram of the edge sub-pixel driving circuit provided in an embodiment of the present invention.

[0136] Each edge sub-pixel includes an edge sub-pixel driving circuit, which includes at least a first transistor T1 and a driving transistor T3. The second terminal of the first transistor T1 is coupled to the gate of the driving transistor T3.

[0137] The display substrate further includes: multiple first reset signal lines 14, wherein the gate of the first transistor T1 is coupled to the first reset signal lines 14;

[0138] The initialization signal lines include a first initialization signal line 15 and a second initialization signal line 13;

[0139] The first terminal of the first transistor T1 is coupled to the first initialization signal line 15.

[0140] The display substrate also includes: multiple power signal lines 5, multiple light emission control signal lines 17, multiple first data lines 6, and multiple second reset signal lines 18;

[0141] The scan lines include a first scan line 10 and a second scan line 12;

[0142] The sub-pixel driving circuit also includes a compensation transistor T2, a data writing transistor T4, a first light-emitting control transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0143] The first terminal of the compensation transistor T2 is coupled to the second terminal of the driving transistor T3, the second terminal of the compensation transistor T2 is coupled to the gate of the driving transistor T3, and the gate of the compensation transistor T2 is coupled to the first scan line 10.

[0144] The first terminal of the data writing transistor T4 is coupled to the corresponding first data line 6, the second terminal of the data writing transistor T4 is coupled to the first terminal of the driving transistor T3, and the gate of the data writing transistor T4 is coupled to the second scan line 12.

[0145] The gate of the first light-emitting control transistor T5 is coupled to the corresponding light-emitting control signal line 17, the first terminal of the first light-emitting control transistor T5 is coupled to the power supply signal line 5, and the second terminal of the first light-emitting control transistor T5 is coupled to the first terminal of the driving transistor T3.

[0146] The gate of the sixth transistor T6 is coupled to the corresponding light-emitting control signal line 17, the first terminal of the sixth transistor T6 is coupled to the second terminal of the driving transistor T3, the second terminal of the sixth transistor T6 is coupled to the anode of the light-emitting element EL, and the cathode of the light-emitting element EL receives the negative power supply signal VSS.

[0147] The gate of the seventh transistor T7 is coupled to the second reset signal line 18, the second terminal of the seventh transistor T7 is coupled to the second terminal of the sixth transistor T6, and the first terminal S7 of the seventh transistor T7 is coupled to the second initialization signal line 13.

[0148] For example, the second reset signal line 18 coupled to the gate of the seventh transistor T7 in the current sub-pixel driving circuit is the same line as the first scan line 10 coupled to the gate of the data write transistor T4 in the adjacent sub-pixel driving circuit along the first direction.

[0149] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate T3-g of the driving transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line 5.

[0150] It should be noted that the second initialization signal line 13 can be coupled to the first initialization signal bus 3 or the second initialization signal bus 4.

[0151] The first initialization signal line 15 can be coupled to the first initialization signal bus 3 or the second initialization signal bus 4.

[0152] When the display panel is a dual SD product, the layout of each film layer corresponding to the sub-pixel is as follows when manufacturing the above sub-pixels:

[0153] It includes a light-shielding layer, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, a first interlayer insulating layer, an IGZO layer, a third gate insulating layer, a third gate metal layer, a second interlayer insulating layer, a second source / drain metal layer, a first protective layer, a first planarization layer, a first source / drain metal layer, a second planarization layer, an anode layer, a pixel defining layer, a spacer layer, an organic light-emitting functional layer, and a cathode layer, which are sequentially stacked in a direction away from the substrate.

[0154] like Figure 3 As shown, the first data line 6 and the power signal line 5 are fabricated using the second source-drain metal layer. In addition, Figure 3 The conductive connection portion 1031 is also illustrated, which is coupled to the anode of the light-emitting element through a via.

[0155] Figure 7 This is a schematic diagram illustrating the coverage area of ​​the vapor deposition mask for the organic light-emitting functional layer provided in an embodiment of the present invention. In AMOLED display panels, if the AMOLED device structure contains a patterned vapor deposition layer, especially when using a conventional mask, there is generally a non-film-forming guarantee area of ​​a certain width. To ensure good uniformity of the light-emitting device, this non-film-forming guarantee area usually extends outside the display area, meaning it occupies a certain amount of bezel space.

[0156] This invention employs a vapor deposition process to form an organic light-emitting functional layer, such as... Figure 7 As shown, the coverage area of ​​the vapor deposition mask for the organic light-emitting functional layer can extend to the position shown by the second boundary line S2, which is located between the first initialization signal bus 3 and the second initialization signal bus 4; further, the coverage area of ​​the vapor deposition mask for the organic light-emitting functional layer can extend to the position shown by the third boundary line S3, which is located on the side of the second initialization signal bus 4 away from the first initialization signal bus 3; further, the coverage area of ​​the vapor deposition mask for the organic light-emitting functional layer can extend to the position shown by the fourth boundary line S4, avoiding covering such as Figure 7 The anode square hole 101 is shown.

[0157] The display device includes, but is not limited to, components such as: a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will understand that the above-described structure of the display device does not constitute a limitation on the display device; the display device may include more or fewer of the aforementioned components, or combine certain components, or arrange different components. In embodiments of the present invention, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television set, a wearable electronic device, a navigation display device, etc.

[0158] The display device can be any product or component with display function, such as an LCD TV, LCD monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes a flexible circuit board, a printed circuit board, and a backplate.

[0159] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0160] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0161] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0162] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0163] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0164] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display panel, comprising a display area and a border area located on one side of the display area, the display panel comprising: Substrate; A plurality of edge sub-pixels are located on the substrate, the plurality of edge sub-pixels are located at the edge of the display area and close to the border area, and the edge sub-pixels include an anode pattern; A first initialization signal bus is located on the substrate, at least a portion of the first initialization signal bus is located in the display area, and at least a portion of the first initialization signal bus is also located in the border area; wherein, The orthographic projection of the anode pattern on the substrate and the orthographic projection of the first initialization signal bus on the substrate have a first overlapping area; The display panel also includes: Multiple sub-pixels, each sub-pixel including a corresponding sub-pixel driving circuit, and the first initialization signal bus is coupled to the first initialization signal line of the sub-pixel driving circuit; The display panel also includes: A second initialization signal bus is located on the substrate, the second initialization signal bus is located in the border area, and is located on the side of the first initialization signal bus away from the edge sub-pixel.

2. The display panel according to claim 1, wherein, The display panel also includes: A first source / drain metal layer is located between the substrate and the anode pattern, and the first initialization signal bus is fabricated using the first source / drain metal layer.

3. The display panel according to claim 2, wherein, The display panel also includes: A power signal line, at least one of the edge sub-pixels includes an edge sub-pixel driving circuit, the power signal line is used to provide a power supply voltage to the edge sub-pixel driving circuit, the power signal line is fabricated using the first source-drain metal layer, and the orthographic projection of the anode pattern on the substrate and the orthographic projection of the power signal line on the substrate have a second overlapping area.

4. The display panel according to claim 3, wherein, The first overlapping region and The second overlapping region is located on both sides of the anode pattern.

5. The display panel according to claim 3, wherein, The first overlapping region The ratio of the area to the area of ​​the second overlapping region is 0.8-1.

2.

6. The display panel according to claim 1, wherein, The edge sub-pixel driving circuit includes at least a first transistor and a seventh transistor, one of which is coupled to the first initialization signal bus; the other of which is coupled to the second initialization signal bus.

7. The display panel according to claim 1, wherein, The second initialization signal bus is set in the same layer and with the same material as the first initialization signal bus.

8. The display panel according to claim 1, wherein, The edge sub-pixel further includes: a pixel definition opening located on the side of the anode pattern away from the substrate, the pixel definition opening corresponding to the anode pattern, and the area of ​​the pixel definition opening being smaller than the area of ​​the anode pattern.

9. The display panel according to claim 8, wherein, The orthographic projection of the pixel definition opening on the substrate and the orthographic projection of the first initialization signal bus on the substrate have a third overlapping region, the area of ​​the third overlapping region being smaller than the area of ​​the first overlapping region.

10. The display panel according to claim 8, wherein, The orthographic projection of the pixel definition opening on the substrate does not overlap with the orthographic projection of the first initialization signal bus on the substrate.

11. The display panel according to claim 3, wherein, The display panel further includes: a first data line, which is used to provide data voltage to the edge sub-pixel driving circuit. The first data line is made of the first source-drain metal layer and is located between the power signal line and the first initialization signal bus. The orthographic projection of the first data line on the substrate overlaps with the orthographic projection of the anode pattern on the substrate.

12. The display panel according to claim 11, wherein, The display panel further includes a virtual data line located between the first data line and the first initialization signal bus, wherein the orthographic projection of the virtual data line on the substrate overlaps with the orthographic projection of the anode pattern on the substrate.

13. The display panel according to claim 12, wherein, The spacing between the virtual data line and the first initialization signal bus is 3μm-7μm, and the spacing between the first initialization signal bus and the second initialization signal bus is 5μm-30μm.

14. The display panel according to claim 12, wherein, The line width of the first initialization signal bus is 30μm-40μm; the line width of the second initialization signal bus is 30μm-40μm.

15. The display panel according to claim 8, wherein, The anode pattern includes a main body and an auxiliary body that are coupled to each other, and the center point of the pixel-defined opening coincides with the center point of the main body of the anode pattern.

16. The display panel according to claim 12, wherein, The first data line and the virtual data line are located on opposite sides of the center point of the anode pattern.

17. The display panel according to claim 2, wherein, The display panel also includes: A planarization layer located between the anode pattern and the first source / drain metal layer, the planarization layer serving to planarize the area between the anode pattern and the first source / drain metal layer.

18. The display panel according to claim 1, wherein, The display panel includes multiple sub-pixels, which are arranged in an RGBG pattern. The edge sub-pixels are G pixels located at the edge of the display area and close to the border area.

19. The display panel according to claim 18, wherein, The arrangement of the multiple sub-pixels also includes: GGRB, diamond, S-RGB, or Delta.

20. The display panel according to claim 1, wherein, The display panel also includes: The first initialization signal bus is fabricated using the second source / drain metal layer located on the substrate.

21. The display panel according to claim 1, wherein, The display panel further includes a GOA circuit located in the bezel area, wherein the orthographic projection of the anode pattern on the substrate and the orthographic projection of the GOA circuit on the substrate have a fourth overlapping area.

22. A display device comprising a display panel as described in any one of claims 1-21.

Images