Antifuse cell structure, antifuse array and method of operating same, and memory

Abstract

The embodiments of the present disclosure disclose a structure of an anti-fuse cell, an anti-fuse array and an operation method thereof, and a memory, wherein the structure of the anti-fuse cell comprises: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and an enable signal line being electrically connected to the first end of the first anti-fuse transistor, the enable signal line being used for programming operation of the first anti-fuse transistor.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an antifuse cell structure, an antifuse array and its operation method, and a memory. Background Technology

[0002] One-time programmable devices based on anti-fuse technology are widely used in DRAM, NAND, and other memory applications. An anti-fuse device is a semiconductor device consisting of two conductive layers and a dielectric layer between them. When unprogrammed, the conductive layers are separated by the dielectric layer, and the antifuse is open-circuited. During programming (with an applied high voltage), the dielectric layer is broken down by the high electric field, forming an electrical connection between the two conductive layers, and the antifuse is short-circuited (melted). This melting process is physically one-time, permanent, and irreversible. The states before and after the antifuse melts can represent logic "0" and logic "1," respectively. However, current antifuse cell structures and antifuse arrays composed of multiple antifuse cells have drawbacks, including the risk of selective transistor breakdown, large chip area occupation, and poor uniformity.

[0003] Therefore, optimizing the structure of the antifuse unit and the antifuse array is a technical problem that urgently needs to be solved at this stage. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an antifuse unit structure, an antifuse array, an operation method thereof, and a memory.

[0005] According to a first aspect of the present disclosure, an antifuse cell structure is provided, comprising: a first antifuse transistor having a first terminal and a second terminal; a first selection transistor having a first terminal and a second terminal, the first terminal of the first selection transistor being electrically connected to the second terminal of the first antifuse transistor; and an enable signal line electrically connected to the first terminal of the first antifuse transistor, the enable signal line being used to program the first antifuse transistor.

[0006] In some embodiments, the device further includes: an active region extending along a first direction; a first antifuse transistor gate line extending along a second direction and covering a portion of the active region to define a first antifuse transistor, wherein the first direction intersects the second direction; and a first select transistor gate line extending along the second direction and covering a portion of the active region to define a first select transistor.

[0007] In some embodiments, the system further includes: a bit line electrically connected to a second terminal of the first selection transistor, the bit line being located above the active region and extending along the first direction; and an enable signal line being located above one side of the active region, the enable signal line being arranged parallel to the active region and extending along the first direction.

[0008] In some embodiments, the system further includes: a first doped region and a first common doped region, respectively located in the active regions on both sides of the gate line of the first antifuse transistor; a first common doped region and a second common doped region, respectively located in the active regions on both sides of the gate line of the first select transistor; wherein the second common doped region is electrically connected to the bit line; and the first doped region is electrically connected to the enable signal line.

[0009] In some embodiments, the system further includes: a second select transistor gate line extending along the second direction and covering a portion of the active region to define a second select transistor; and a second antifuse transistor gate line extending along the second direction and covering a portion of the active region to define a second antifuse transistor.

[0010] In some embodiments, the system further includes: a second common doped region and a third common doped region, respectively located in the active regions on both sides of the gate line of the second select transistor; a third common doped region and a second doped region, respectively located in the active regions on both sides of the gate line of the second antifuse transistor; wherein the second doped region is electrically connected to the enable signal line.

[0011] In some embodiments, the width of the first antifuse transistor gate line along the first direction is less than or equal to the width of the first select transistor gate line along the first direction; the width of the second antifuse transistor gate line along the first direction is less than or equal to the width of the second select transistor gate line along the first direction.

[0012] In some embodiments, the width of the first antifuse transistor gate line along the first direction is equal to the width of the second antifuse transistor gate line along the first direction, and the width of the first select transistor gate line along the first direction is equal to the width of the second select transistor gate line along the first direction, wherein the combination of the first antifuse transistor gate line and the first select transistor gate line is axially symmetrically distributed with respect to the combination of the second select transistor gate line and the second antifuse transistor gate line.

[0013] In some embodiments, the device further includes: a first contact plug located on the first doped region; a first connector, wherein the enable signal line is electrically connected to the first contact plug via the first connector; a second contact plug located on the second common doped region; a second connector, wherein the bit line is electrically connected to the second contact plug via the second connector; a third contact plug located on the second doped region; and a third connector, wherein the enable signal line is electrically connected to the third contact plug via the third connector.

[0014] According to a second aspect of the present disclosure, an antifuse array is provided, comprising: a plurality of first antifuse transistors and a plurality of first select transistors arranged in an array, wherein each first antifuse transistor has a first terminal and a second terminal, and each first select transistor has a first terminal and a second terminal, wherein one first antifuse transistor corresponds to one first select transistor, and the first terminal of each first select transistor is electrically connected to the second terminal of its corresponding first antifuse transistor; a plurality of bit lines, each bit line being electrically connected to the second terminal of a column of first select transistors; and a plurality of enable signal lines, each enable signal line being electrically connected to the first terminal of a column of first antifuse transistors, wherein the enable signal lines are used to program the first antifuse transistors.

[0015] In some embodiments, the system further includes: a plurality of active regions, the plurality of active regions being arranged as a plurality of rows of active regions extending along a second direction and a plurality of columns of active regions extending along a first direction, the first direction being perpendicular to the second direction, and each of the active regions extending along the first direction; a plurality of first antifuse transistor gate lines, the plurality of first antifuse transistor gate lines being arranged parallel to each other and extending along the second direction, each of the first antifuse transistor gate lines corresponding to cover a plurality of active regions within one row of active regions, to define a plurality of first antifuse transistors arranged in an array; and a plurality of first select transistor gate lines, the plurality of first select transistor gate lines being arranged parallel to each other and extending along the second direction, each of the first select transistor gate lines corresponding to cover a plurality of active regions within one row of active regions, to define a plurality of first select transistors arranged in an array.

[0016] In some embodiments, the system further includes: a plurality of second select transistor gate lines, the plurality of second select transistor gate lines being arranged in parallel to each other and extending along a second direction, each second select transistor gate line corresponding to covering a plurality of active regions within one row of active regions, to define a plurality of second select transistors arranged in an array; and a plurality of second antifuse transistor gate lines, the plurality of second antifuse transistor gate lines being arranged in parallel to each other and extending along a second direction, each second antifuse transistor gate line corresponding to covering a plurality of active regions within one row of active regions, to define a plurality of second antifuse transistors arranged in an array.

[0017] In some embodiments, a plurality of enable signal lines are arranged along a second direction and extend along a first direction, wherein each enable signal line and each active region column are arranged alternately in the second direction; a plurality of bit lines are arranged parallel to each other and extend along the first direction, each bit line corresponds to an active region column, and each bit line is located above the corresponding active region column.

[0018] According to a third aspect of the present disclosure, a method for operating an antifuse array is provided, comprising:

[0019] Provide an antifuse array as described in any of the above embodiments; perform programming or reading operations on the antifuse array.

[0020] In some embodiments, the programming operation includes: selecting an antifuse transistor to be programmed; applying a first voltage to the gate line of the antifuse transistor to be programmed; leaving other antifuse transistor gate lines floating; leaving all selected transistor gate lines floating; and applying a second voltage to an enable signal line electrically connected to the antifuse transistor to be programmed; wherein the absolute value of the difference between the first voltage and the second voltage is greater than the breakdown voltage of the gate dielectric layer of the antifuse transistor.

[0021] In some embodiments, the read operation includes: selecting an antifuse transistor to be read; applying a third voltage to the gate line of the select transistor electrically connected to the antifuse transistor to be read, and leaving other select transistor gate lines floating; applying a fourth voltage to a bit line electrically connected to the antifuse transistor to be read, and leaving other bit lines floating; applying a fifth voltage to the gate line of the antifuse transistor to be read, and leaving other antifuse transistor gate lines floating; and leaving all enable signal lines floating; wherein the third voltage is the turn-on voltage of the select transistor, and the absolute value of the difference between the fourth voltage and the fifth voltage is less than the breakdown voltage of the gate dielectric layer of the antifuse transistor.

[0022] According to a fourth aspect of the present disclosure, a memory is provided, including an antifuse unit structure as described in any of the above embodiments.

[0023] The antifuse unit structure provided in this embodiment adds an enable signal line (BE, Blow enable) control terminal. The enable signal line is electrically connected to one end of the antifuse transistor, and the other end of the antifuse transistor is electrically connected to the select transistor. Thus, during programming of the antifuse transistor, the voltage difference between the enable signal line control terminal and the gate of the antifuse transistor causes the antifuse transistor to break down. There is no need to turn on the select transistor; the high voltage required to break down the antifuse transistor does not pass through the select transistor, thereby preventing damage to the select transistor. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A circuit diagram of an antifuse unit structure provided in an embodiment of this disclosure;

[0026] Figure 2 This is a schematic diagram of an antifuse unit structure provided in an embodiment of the present disclosure;

[0027] Figure 3 A circuit diagram of another antifuse array provided for an embodiment of this disclosure;

[0028] Figure 4 This is a schematic diagram of another antifuse array provided in an embodiment of the present disclosure;

[0029] Figure 5 This is a flowchart illustrating an operation method for an antifuse array provided in an embodiment of the present disclosure.

[0030] Figure label:

[0031] 11-First antifuse transistor; 12-First select transistor; 13-Second select transistor; 14-Second antifuse transistor; 15-Enable signal line; 16-Bit line; 17-Active region; 21-Gate line of the first antifuse transistor; 211-Fourth contact plug; 212-Fourth connector; 22-Gate line of the first select transistor; 221-Fifth contact plug; 222-Fifth connector; 23-Gate line of the second select transistor; 24-Gate line of the second antifuse transistor; 25-First doped region; 251-First contact plug; 252-First connector; 26-First common doped region; 27-Second common doped region; 271-Second contact plug; 272-Second connector; 273-Sixth contact plug; 28-Third common doped region; 29-Second doped region; 291-Third contact plug; 292-Third connector. Detailed Implementation

[0032] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0033] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0034] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0038] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0039] Currently, in typical antifuse cell structures, the antifuse transistor is electrically connected to the bit line via a select transistor. The voltage difference between the bit line (BL) and the gate of the antifuse transistor causes the thin gate oxide of the antifuse transistor to break down under high voltage, significantly reducing its resistance and achieving programming or writing. However, current architectures often suffer from the risk of failure and occupy a large chip area.

[0040] Based on this, the present disclosure provides an antifuse unit structure. Figure 1 This is a circuit diagram of the antifuse unit structure provided in the embodiments of this disclosure. Figure 2 This is a schematic diagram of the antifuse unit structure provided in an embodiment of this disclosure.

[0041] See appendix Figure 1 and attached Figure 2 The antifuse unit structure includes: a first antifuse transistor 11, which has a first terminal and a second terminal; a first selection transistor 12, which also has a first terminal and a second terminal, with the first terminal of the first selection transistor 12 electrically connected to the second terminal of the first antifuse transistor 11; and an enable signal line 15, which is electrically connected to the first terminal of the first antifuse transistor 11 and is used to program the first antifuse transistor 11. In practical applications, the second terminal of the first selection transistor 12 can be electrically connected to a bit line 16.

[0042] The antifuse unit structure provided in this embodiment adds an enable signal line (BE, Blow enable) control terminal. The enable signal line is electrically connected to one end of the antifuse transistor, and the other end of the antifuse transistor is electrically connected to the select transistor. Thus, during programming of the antifuse transistor, the voltage difference between the enable signal line control terminal and the gate of the antifuse transistor causes the antifuse transistor to break down. There is no need to turn on the select transistor; the high voltage required to break down the antifuse transistor does not pass through the select transistor, thereby preventing damage to the select transistor.

[0043] In this embodiment, the first and second terminals of the antifuse transistor 11 can be the first and second terminals of a transistor, respectively, wherein the first terminal can be the source and the second terminal can be the drain; or, the first terminal can be the drain and the second terminal can be the source. The first and second terminals of the first selection transistor 12 can be the first and second terminals of a selection transistor, respectively, wherein the first terminal can be the source and the second terminal can be the drain; or, the first terminal can be the drain and the second terminal can be the source. In practical applications, the first antifuse transistor and the first selection transistor can include metal-oxide-semiconductor transistors (MOS), such as P-type metal-oxide-semiconductor transistors (PMOS) or N-type metal-oxide-semiconductor transistors (NMOS).

[0044] In some embodiments, see Appendix Figure 1 and attached Figure 2 The antifuse unit structure further includes: an active region 17 extending along a first direction; a first antifuse transistor gate line 21 extending along a second direction and covering a portion of the active region 17 to define the first antifuse transistor, the first direction intersecting the second direction; and a first select transistor gate line 22 extending along the second direction and covering a portion of the active region 17 to define the first select transistor. In practical applications, the active region 17 is disposed on a substrate, which may be silicon, silicon-germanium, germanium, or other suitable semiconductors. The first active region can be formed into an N-type doped region by doping with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and can be formed into a P-type doped region by doping with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. In practical applications, the active region 17 may include source / drain doped regions. The materials of the first antifuse transistor gate line 21 and the first select transistor gate line 22 include, but are not limited to, polysilicon, titanium nitride, tungsten metal, or combinations thereof. The first direction can be perpendicular to the second direction, which can further improve the integration of the structure.

[0045] In some embodiments, see Appendix Figure 1 and attached Figure 2It also includes: a second selection transistor gate line 23, which extends along a second direction and covers a portion of the active region 17 to define a second selection transistor 13; and a second antifuse transistor gate line 24, which extends along the second direction and covers a portion of the active region 17 to define a second antifuse transistor 14. The materials of the second selection transistor gate line 23 and the second antifuse transistor gate line 24 include, but are not limited to, polysilicon, titanium nitride, tungsten metal, or combinations thereof.

[0046] In some embodiments, see Appendix Figure 1 and attached Figure 2 The antifuse unit structure further includes: a bit line 16 electrically connected to the second terminal of the first selection transistor 12, the bit line 16 being located above the active region 17 and extending along a first direction; and an enable signal line 15 located above one side of the active region 17, the enable signal line 15 being arranged parallel to the active region 17 and extending along the first direction. Here, the materials of the bit line 16 and the enable signal line 15 include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof. In practical applications, the active region can be located in the substrate, the enable signal line can be located in a metal layer on the substrate, and the bit line 16 can be located in another metal layer on the substrate, the other metal layer being located on the side of the first metal layer away from the substrate. The orthogonal projection of the bit line onto the substrate plane partially overlaps with the orthogonal projection of the active region onto the substrate plane, and the orthogonal projection of the enable signal line onto the substrate plane is located on one side of the orthogonal projection of the active region onto the substrate plane.

[0047] In some embodiments, see Appendix Figure 1 and attached Figure 2 The antifuse unit structure further includes: a first doped region 25 and a first common doped region 26, respectively located within the active regions 17 on both sides of the gate line 21 of the first antifuse transistor; a first common doped region 26 and a second common doped region 27, respectively located within the active regions 17 on both sides of the gate line 22 of the first select transistor; wherein, the second common doped region 27 is electrically connected to the bit line 16; and the first doped region 25 is electrically connected to the enable signal line 15. The first doped region 25 and the first common doped region 26 can be the first and second terminals of the first antifuse transistor 11, respectively. The first common doped region 26 and the second common doped region 27 can be the first and second terminals of the first select transistor 12, respectively. The second terminal of the first antifuse transistor 11 and the first terminal of the first select transistor 12 are electrically connected through the first common doped region 26, which reduces the doped region area and improves space utilization.

[0048] In some embodiments, see Appendix Figure 1 and attached Figure 2The antifuse unit structure further includes: a second common doped region 27 and a third common doped region 28, respectively located within the active regions 17 on both sides of the gate line 23 of the second select transistor; the third common doped region 28 and the second doped region 29, respectively located within the active regions 17 on both sides of the gate line 24 of the second antifuse transistor; wherein, the second doped region 29 is electrically connected to the enable signal line 15. The second common doped region 27 and the third common doped region 28 can be the first and second terminals of the second select transistor 13, respectively. The second terminal of the first select transistor and the first terminal of the second select transistor are electrically connected through the second common doped region 27, which can improve space utilization. The third common doped region 28 and the second doped region 29 can be the first and second terminals of the second antifuse transistor 14, respectively. The second terminal of the second select transistor and the first terminal of the second antifuse transistor are electrically connected through the third common doped region 28, which can improve space utilization.

[0049] In practical applications, the first doped region 25, the first common doped region 26, the second common doped region 27, the third common doped region 28, and the second doped region 29 can be heavily doped regions, formed by ion implantation into the active region 17. Each doped region can have the same doping concentration, and can be either N-type heavily doped or P-type heavily doped. The first common doped region 26 is the common drain / source of the first antifuse transistor 11 and the first select transistor 12, the second common doped region 27 is the common drain / source of the first select transistor 12 and the second select transistor 13, and the third common doped region 28 is the common drain / source of the second select transistor 13 and the second antifuse transistor 14.

[0050] In some embodiments, see Appendix Figure 1 and attached Figure 2 The width W1 of the first antifuse transistor gate line along the first direction is less than or equal to the width W2 of the first select transistor gate line along the first direction; the width W4 of the second antifuse transistor gate line along the first direction is less than or equal to the width W3 of the second select transistor gate line along the first direction. The first antifuse transistor gate line, the first select transistor gate line, the second select transistor gate line, and the second antifuse transistor gate line can be formed simultaneously, and the forming process includes, but is not limited to, various patterning processes. This facilitates mask fabrication and reduces the difficulty of the patterning process, while also improving the uniformity of the subsequent antifuse array formation.

[0051] It is understood that in the embodiments of this disclosure, both the first antifuse transistor 11 and the second antifuse transistor 14 may have a small channel length (for example, there is a large leakage current between the first end and the second end of the antifuse transistor, that is, the first end and the second end of the antifuse transistor can be regarded as being mutually conductive to a certain extent) to ensure that after the gate dielectric layer of the antifuse transistor is broken down, the gate of the antifuse transistor is conductive to both its first end and its second end.

[0052] In some embodiments, the width W1 of the first antifuse transistor gate line along the first direction can be equal to the width W4 of the second antifuse transistor gate line along the first direction, and the width W2 of the first select transistor gate line along the first direction can be equal to the width W3 of the second select transistor gate line along the first direction. The combination of the first antifuse transistor gate line and the first select transistor gate line is axially symmetrically distributed with respect to the combination of the second select transistor gate line and the second antifuse transistor gate line. This makes the first and second antifuse transistors and the first select transistor mirror images of each other, improving the uniformity of the subsequent formation of the antifuse array.

[0053] In some embodiments, see Appendix Figure 1 and attached Figure 2 The distance between the first antifuse transistor gate line and the first select transistor gate line is a first distance D1, and the distance between the second select transistor gate line and the second antifuse transistor gate line is a second distance D2, wherein the first distance D1 is equal to the second distance D2. This can further improve the uniformity of the subsequent formation of the antifuse array. In some other embodiments, the widths W1, W2, W3, and W4 of the first antifuse transistor gate line along the first direction, as well as the first distance D1 and the second distance D2, are all equal.

[0054] It should be understood that, currently, in typical antifuse cell structures, the select transistor is a thick oxide device with a relatively long gate length, requiring a large device width to ensure sufficient current drive capability. Furthermore, due to the presence of a reverse-biased junction (ND / PW) in the read current path, to reduce the series resistance during read operations, it is generally necessary to dope the substrate below the antifuse transistor gate line to form an ion-doped region for the antifuse transistor. Because the doping concentration of the antifuse transistor ion-doped region is extremely high, these dopant ions may diffuse to the vicinity of the select transistor channel during high-temperature processing, significantly reducing the select transistor's turn-on voltage and increasing leakage current. Therefore, the antifuse transistor gate line and the select transistor gate line must also maintain a large distance. This makes it difficult to further reduce the area of ​​the antifuse cell structure and antifuse array. However, the antifuse cell structure provided in this disclosure, without significantly reducing the length of the select transistor gate line (XG), can reduce the width of the select transistor gate line to be consistent with the width of the antifuse transistor gate line (FG). Simultaneously, by reducing the width of the antifuse transistor gate line, the source and drain doped regions on both sides of the gate line will significantly reduce the reverse bias junction barrier under the action of the depletion layer, thereby increasing the read current. Since there is no need to set up ion-doped regions for the antifuse transistor, the spacing between the antifuse transistor gate line and the select transistor gate line can be further reduced. Furthermore, the photomask used to fabricate the ion-doped regions of the antifuse transistor is omitted, reducing chip manufacturing costs.

[0055] In some embodiments, see Appendix Figure 1 and attached Figure 2 The antifuse unit structure further includes: a first contact plug 251 located on the first doped region 25; a first connector 252, through which the enable signal line 15 is electrically connected to the first contact plug 251; a second contact plug 271 located on the second common doped region 27; a second connector 272, through which the bit line 16 is electrically connected to the second contact plug 271; a third contact plug 291 located on the second doped region 29; and a third connector 292, through which the enable signal line 15 is electrically connected to the third contact plug 291. Here, the first connector 252, the second connector 272, and the third connector 292 can be the same film layer or different film layers. For example, they can be located in the same metal layer as the enable signal line 15. In some other embodiments, the antifuse unit structure further includes: a sixth contact plug 273, through which the bit line 16 is electrically connected to the second connector 272. In this way, bit line 16 and enable signal line 15 are located in different metal layers, avoiding signal crosstalk and increasing routing flexibility.

[0056] In some embodiments, the antifuse unit structure further includes: a fourth contact plug 211, through which the gate line 21 of the first antifuse transistor is electrically connected to the fourth connector 212; and a fifth contact plug 221, through which the gate line 22 of the first select transistor is electrically connected to the fifth connector 222. The fourth connector 212 and the fifth connector 222 may be the same film layer or different film layers.

[0057] This disclosure also provides an antifuse array. Figure 3 This is a circuit diagram of an antifuse array provided in an embodiment of the present disclosure. Figure 4 This is a schematic diagram of the structure of the antifuse array provided in an embodiment of this disclosure.

[0058] See appendix Figure 3 and attached Figure 4 The antifuse array includes: a plurality of first antifuse transistors 11 and a plurality of first select transistors 12 arranged in an array. Each first antifuse transistor 11 has a first terminal and a second terminal, and each first select transistor 12 has a first terminal and a second terminal. One first antifuse transistor 11 corresponds to one first select transistor 12, and the first terminal of each first select transistor 12 is electrically connected to the second terminal of its corresponding first antifuse transistor 11. Multiple bit lines 16 are provided, each bit line 16 being electrically connected to the second terminal of a column of first select transistors 12. Multiple enable signal lines 15 are provided, each enable signal line 15 being electrically connected to the first terminal of a column of first antifuse transistors 11. The enable signal lines 15 are used to program the first antifuse transistors 11. In this embodiment, the first terminal and the second terminal of the antifuse transistor 11 can be the first electrode and the second electrode of the transistor, respectively. The first electrode can be the source, and the second electrode can be the drain; or, the first electrode can be the drain, and the second electrode can be the source. The first terminal and the second terminal of the first selection transistor 12 can be the first electrode and the second electrode of the selection transistor, respectively, wherein the first electrode can be the source and the second electrode can be the drain; or, the first electrode can be the drain and the second electrode can be the source. In practical applications, the first antifuse transistor and the first selection transistor can include metal-oxide-semiconductor transistors (MOS), such as P-type metal-oxide-semiconductor transistors (PMOS) or N-type metal-oxide-semiconductor transistors (NMOS).

[0059] In some embodiments, see Appendix Figure 3 and attached Figure 4The antifuse array further includes: a plurality of active regions 17, arranged in a plurality of rows R extending along a second direction and a plurality of columns C extending along a first direction, the first direction being perpendicular to the second direction, each active region 17 extending along the first direction; a plurality of first antifuse transistor gate lines 21, arranged parallel to each other and extending along the second direction, each first antifuse transistor gate line 21 correspondingly covering a plurality of active regions 17 within an active region row R, to define a plurality of first antifuse transistors 11 arranged in the array; and a plurality of first select transistor gate lines 22, arranged parallel to each other and extending along the second direction, each first select transistor gate line 22 correspondingly covering a plurality of active regions 17 within an active region row R, to define a plurality of first select transistors 12 arranged in the array. In practical applications, the active regions 17 are disposed on a substrate, which may be silicon, silicon-germanium, germanium, or other suitable semiconductors. The first active region can be formed into an N-type doped region by doping with n-type dopants such as phosphorus, arsenic, other n-type dopants, or combinations thereof; and can be formed into a P-type doped region by doping with p-type dopants such as boron, indium, other p-type dopants, or combinations thereof. In practical applications, the active region 17 may include source / drain doped regions. The materials of the first antifuse transistor gate line 21 and the first select transistor gate line 22 include, but are not limited to, polysilicon, titanium nitride, tungsten, or combinations thereof. The first direction can be perpendicular to the second direction, which can further improve the integration density of the structure.

[0060] In some embodiments, see Appendix Figure 3 and attached Figure 4 The antifuse array further includes: a plurality of second select transistor gate lines 23, which are arranged parallel to each other and extend along a second direction. Each second select transistor gate line 23 covers a plurality of active regions 17 within an active region row R to define a plurality of second select transistors 13 arranged in the array; and a plurality of second antifuse transistor gate lines 24, which are arranged parallel to each other and extend along a second direction. Each second antifuse transistor gate line 24 covers a plurality of active regions 17 within an active region row R to define a plurality of second antifuse transistors 14 arranged in the array. The materials of the second select transistor gate lines 23 and the second antifuse transistor gate lines 24 include, but are not limited to, polysilicon, titanium nitride, tungsten metal, or combinations thereof.

[0061] In some embodiments, see Appendix Figure 3 and attached Figure 4Multiple enable signal lines 15 are arranged along a second direction and extend along a first direction, wherein each enable signal line 15 and each active region column C are arranged alternately in the second direction; multiple bit lines 16 are arranged parallel to each other and extend along the first direction, each bit line 16 corresponds to an active region column C, and each bit line 16 is located above its corresponding active region column C. Here, the materials of the bit lines 16 and enable signal lines 15 include, but are not limited to, tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), polycrystalline silicon, doped silicon, metal silicides, metal alloys, or any combination thereof. In practical applications, the active region can be located in the substrate, the enable signal line can be located in the M0 metal layer, and the bit line 16 can be located in the M1 metal layer. The orthographic projection of each bit line 16 onto the substrate plane partially overlaps with the orthographic projection of the active region column C onto the substrate plane.

[0062] In some embodiments, the antifuse array includes any of the antifuse unit structures described above.

[0063] In some embodiments, see Appendix Figure 1 To be continued Figure 4 The antifuse array further includes: a first doped region 25 and a first common doped region 26, which are located in the active regions 17 on both sides of the gate line 21 of the first antifuse transistor; a first common doped region 26 and a second common doped region 27, which are located in the active regions 17 on both sides of the gate line 22 of the first select transistor; wherein, the second common doped region 27 is electrically connected to the bit line 16; and the first doped region 25 is electrically connected to the enable signal line 15.

[0064] In some embodiments, see Appendix Figure 1 To be continued Figure 4 The antifuse array further includes: a second common doped region 27 and a third common doped region 28, which are located in the active regions 17 on both sides of the gate line 23 of the second select transistor, respectively; the third common doped region 28 and the second doped region 29, which are located in the active regions 17 on both sides of the gate line 24 of the second antifuse transistor, respectively; wherein the second doped region 29 is electrically connected to the enable signal line 15.

[0065] In some embodiments, see Appendix Figure 1 To be continued Figure 4 The width W1 of the gate line of the first antifuse transistor along the first direction is less than or equal to the width W2 of the gate line of the first select transistor along the first direction; the width W4 of the gate line of the second antifuse transistor along the first direction is less than or equal to the width W3 of the gate line of the second select transistor along the first direction. This facilitates mask fabrication and reduces the difficulty of patterning processes, while also improving the uniformity of the antifuse array.

[0066] In some embodiments, see Appendix Figure 1 To be continued Figure 4 The width W1 of the first antifuse transistor gate line along the first direction can be equal to the width W4 of the second antifuse transistor gate line along the first direction, and the width W2 of the first select transistor gate line along the first direction can be equal to the width W3 of the second select transistor gate line along the first direction. The combination of the first antifuse transistor gate line and the first select transistor gate line is axially symmetrically distributed with respect to the combination of the second select transistor gate line and the second antifuse transistor gate line. This makes the first and second antifuse transistors and the first select transistor mirror images of each other, improving the uniformity of the subsequent formation of the antifuse array.

[0067] In some embodiments, see Appendix Figure 1 To be continued Figure 4 The distance between the gate line of the first antifuse transistor and the gate line of the first select transistor is a first distance D1, and the distance between the gate line of the second select transistor and the gate line of the second antifuse transistor is a second distance D2, wherein the first distance D1 is equal to the second distance D2. This can further improve the uniformity of the antifuse array.

[0068] In some embodiments, see Appendix Figure 1 To be continued Figure 4 The antifuse array further includes: a first contact plug 251 located on the first doped region 25; a first connector 252, through which the enable signal line 15 is electrically connected to the first contact plug 251; a second contact plug 271 located on the second common doped region 27; a second connector 272, through which the bit line 16 is electrically connected to the second contact plug 271; a third contact plug 291 located on the second doped region 29; and a third connector 292, through which the enable signal line 15 is electrically connected to the third contact plug 291. Thus, the bit line 16 and the enable signal line 15 are located in different metal layers, avoiding signal crosstalk and increasing wiring flexibility.

[0069] This disclosure also provides an operation method for an antifuse array, as shown in the attached figure. Figure 5 As shown, it includes:

[0070] Step 501: Provide an antifuse array as described in any of the above embodiments;

[0071] Step 502: Perform programming or reading operations on the antifuse array.

[0072] The operation method of the antifuse array provided in this disclosure will be further described in detail below with reference to specific embodiments.

[0073] First, see appendix Figure 3 and attached Figure 4Step 501 is executed, providing an antifuse array as described in any of the above embodiments.

[0074] Next, step 502 is executed to perform a programming operation or a reading operation on the antifuse array.

[0075] In some embodiments, the programming operation includes: selecting an antifuse transistor to be programmed; applying a first voltage to the gate line of the antifuse transistor to be programmed; leaving the gate lines of other antifuse transistors floating; leaving all selected transistor gate lines floating; and applying a second voltage to an enable signal line electrically connected to the antifuse transistor to be programmed; wherein the absolute value of the difference between the first voltage and the second voltage is greater than or equal to the breakdown voltage of the gate dielectric layer of the antifuse transistor (i.e., the gate dielectric layer of the antifuse transistor can be broken down). Here, the gate dielectric layer may be, for example, an oxide layer.

[0076] For example, combined with appendix Figure 4 First, the antifuse transistor to be programmed is selected. For example, the antifuse transistor to be programmed may be located on the active region of the first column, first row. In some embodiments, the antifuse transistor to be programmed includes at least one of a first antifuse transistor and a second antifuse transistor, which can be fused during programming operations, allowing for individual or simultaneous programming of both.

[0077] Next, in conjunction with the appendix Figure 4 A first voltage is applied to the gate line of the antifuse transistor to be programmed, while other antifuse transistor gate lines are left floating or set to zero voltage. Simultaneously, a second voltage is applied to the enable signal line electrically connected to the antifuse transistor to be programmed. For example, the first voltage is applied to the antifuse transistor gate line covering the active region of the first column and first row, while other antifuse transistor gate lines are left floating or set to zero voltage. At the same time, the second voltage is applied to the enable signal line located on the active region side of the first column and first row. Taking a breakdown voltage of 6V for the gate dielectric layer of the antifuse transistor as an example, the first voltage can be, for example, 6V, and the second voltage can be, for example, 0V. The difference between the first voltage and the second voltage can break down the gate dielectric layer of the antifuse transistor, causing the antifuse transistor to break down. In some embodiments, the antifuse transistor gate line includes a first antifuse transistor gate line and a second antifuse transistor gate line. The first voltage can be applied to at least one of the first and second antifuse transistor gate lines. In this way, programming can be completed by blowing one or both of the first and second antifuse transistors.

[0078] During programming, leave all select transistor gate lines floating. (Combined with attached...) Figure 4 All the gate lines of the first select transistor and the second antifuse transistor are left floating. Thus, all select transistors are in the off state.

[0079] In some embodiments, one of the first voltage and the second voltage can be a positive voltage, and the other can be a negative voltage. The absolute value of the first voltage is less than the breakdown voltage of the gate dielectric layer of the antifuse transistor, and the absolute value of the second voltage is also less than the breakdown voltage of the gate dielectric layer of the antifuse transistor. Here, the absolute value of the voltage is also referred to as the voltage amplitude. For example, the breakdown voltage of the gate dielectric layer of the antifuse transistor is 6V, the first voltage can be, for example, 5V, and the second voltage can be, for example, -1V. The amplitude of the first voltage (5V) is less than the breakdown voltage of the gate dielectric layer of the antifuse transistor, and the amplitude of the second voltage (-1V) is less than the breakdown voltage of the gate dielectric layer of the antifuse transistor. The difference between the first voltage and the second voltage, with an amplitude of 6V, is sufficient to break down the gate dielectric layer of the antifuse transistor. This prevents the application of an excessively high amplitude of the first voltage to the gate line of the antifuse transistor to be programmed, as an excessively high first voltage could misprogram other antifuse transistors located in the same active region row as the antifuse transistor to be programmed. For example, the above-mentioned misprogramming operation refers to other antifuse transistors located in the same active region row as the antifuse transistor to be programmed, which may be damaged even when the enable signal line is floating due to the excessive amplitude of the first voltage.

[0080] In some embodiments, the read operation includes: selecting the antifuse transistor to be read; applying a third voltage to the gate line of the select transistor electrically connected to the antifuse transistor to be read, and leaving other select transistor gate lines floating; applying a fourth voltage to a bit line electrically connected to the antifuse transistor to be read, and leaving other bit lines floating; applying a fifth voltage to the gate line of the antifuse transistor to be read, and leaving other antifuse transistor gate lines floating; and leaving all enable signal lines floating; wherein the third voltage is the turn-on voltage of the select transistor, and the absolute value of the difference between the fourth and fifth voltages is less than the breakdown voltage of the gate dielectric layer of the antifuse transistor. It should be noted that the "turn-on voltage" here refers to the normal operating voltage of the select transistor.

[0081] For example, combined with appendix Figure 4 First, select the antifuse transistor to be read. For example, the antifuse transistor to be read may be located on the active region of the first column and first row.

[0082] Next, a third voltage is applied to the gate line of the select transistor electrically connected to the antifuse transistor to be read, while the other select transistor gate lines are left floating; a fourth voltage is applied to the bit line electrically connected to the antifuse transistor to be read, while the other bit lines are left floating; a fifth voltage is applied to the gate line of the antifuse transistor to be read, while the other antifuse transistor gate lines are left floating; simultaneously, all enable signal lines are left floating. For example, a third voltage is applied to the gate line of the antifuse transistor covering the active region of the first column and first row, while the other antifuse transistor gate lines are left floating; a fourth voltage, for example, 1V, is applied to the bit line above the active region of the first column and first row; a fifth voltage, for example, 0V, is applied to the gate line of the antifuse transistor covering the active region of the first column and first row. Here, the third voltage is the turn-on voltage of the select transistor. In this way, the current can be read at the bit line terminals, and the storage state can be determined by the magnitude of the current to realize the read operation.

[0083] This disclosure also provides a memory including an antifuse unit structure as described in any of the above embodiments.

[0084] In summary, the antifuse unit structure provided in this embodiment adds an enable signal line (BE, Blowenable) control terminal. The enable signal line is electrically connected to one end of the antifuse transistor, and the other end of the antifuse transistor is electrically connected to the select transistor. Thus, during programming of the antifuse transistor, the voltage difference between the enable signal line control terminal and the gate of the antifuse transistor causes the antifuse transistor to break down. There is no need to turn on the select transistor, and the high voltage required to break down the antifuse transistor does not pass through the select transistor, thereby preventing damage to the select transistor.

[0085] It should be noted that the antifuse unit structure, antifuse array, and operating method thereof, as well as the memory provided in the embodiments of this disclosure, can be applied to any integrated circuit including this structure. The technical features described in each embodiment can be arbitrarily combined without conflict. Those skilled in the art can change the order of the above-described forming method steps without departing from the protection scope of this disclosure. In the embodiments of this disclosure, some steps can be executed simultaneously or sequentially without conflict.

[0086] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An antifuse unit structure, characterized in that, include: An active region, which extends along a first direction; A first antifuse transistor gate line extends along a second direction and covers a portion of the active region to define a first antifuse transistor, the first antifuse transistor having a first terminal and a second terminal, the first direction intersecting the second direction; A first selection transistor gate line extends along the second direction and covers a portion of the active region to define a first selection transistor. The first selection transistor has a first terminal and a second terminal, and the first terminal of the first selection transistor is electrically connected to the second terminal of the first antifuse transistor. The bit line is electrically connected to the second terminal of the first selection transistor, the bit line is located above the active region and extends along the first direction; An enable signal line is electrically connected to the first terminal of the first antifuse transistor. The enable signal line is used to program the first antifuse transistor. The enable signal line is located above one side of the active region. The enable signal line is arranged parallel to the active region and extends along the first direction. The first doped region and the first common doped region are located in the active regions on both sides of the gate line of the first antifuse transistor, respectively. The first common doped region and the second common doped region are located in the active regions on both sides of the gate line of the first select transistor, respectively. The second common doped region is electrically connected to the bit line; the first doped region is electrically connected to the enable signal line.

2. The structure according to claim 1, characterized in that, Also includes: The second selection transistor gate line extends along the second direction and covers a portion of the active region to define the second selection transistor; The second antifuse transistor gate line extends along the second direction and covers a portion of the active region to define the second antifuse transistor.

3. The structure according to claim 2, characterized in that, Also includes: The second common doped region and the third common doped region are located in the active regions on both sides of the gate line of the second select transistor, respectively. The third common doped region and the second doped region are located in the active regions on both sides of the gate line of the second antifuse transistor, respectively; wherein, The second doped region is electrically connected to the enable signal line.

4. The structure according to claim 3, characterized in that, The width of the gate line of the first antifuse transistor along the first direction is less than or equal to the width of the gate line of the first select transistor along the first direction; The width of the gate line of the second antifuse transistor along the first direction is less than or equal to the width of the gate line of the second select transistor along the first direction.

5. The structure according to claim 4, characterized in that, The width of the first antifuse transistor gate line along the first direction is equal to the width of the second antifuse transistor gate line along the first direction, and the width of the first select transistor gate line along the first direction is equal to the width of the second select transistor gate line along the first direction. The combination of the first antifuse transistor gate line and the first select transistor gate line is axially symmetrically distributed with respect to the combination of the second select transistor gate line and the second antifuse transistor gate line.

6. The structure according to claim 3, characterized in that, Also includes: The first contact plug is located on the first doped region; The first connector, wherein the enable signal line is electrically connected to the first contact plug through the first connector; The second contact plug is located on the second common doped region; The second connector is used to electrically connect the bit line to the second contact plug. The third contact plug is located on the second doped region; The third connector, through which the enable signal line is electrically connected to the third contact plug.

7. An antifuse array, characterized in that, include: Multiple active regions are arranged as multiple rows of active regions extending along a second direction and multiple columns of active regions extending along a first direction, the first direction being perpendicular to the second direction, and each active region extending along the first direction. Multiple first antifuse transistor gate lines are arranged in parallel to each other and extend along a second direction. Each first antifuse transistor gate line covers multiple active regions within an active region row to define multiple first antifuse transistors arranged in an array. Each first antifuse transistor has a first terminal and a second terminal. Multiple first selection transistor gate lines are arranged in parallel to each other and extend along a second direction. Each first selection transistor gate line covers multiple active regions within an active region row to define multiple arrayed first selection transistors. Each first selection transistor has a first terminal and a second terminal. One first antifuse transistor corresponds to one first selection transistor. The first terminal of each first selection transistor is electrically connected to the second terminal of its corresponding first antifuse transistor. Multiple bit lines, each bit line is electrically connected to the second end of a column of first selection transistors, each bit line is located above multiple active regions in the corresponding column of active regions, and extends along the first direction; Multiple enable signal lines, each enable signal line is electrically connected to the first end of a column of first antifuse transistors. The enable signal lines are used to program the first antifuse transistors. Each enable signal line is located above one side of multiple active regions in the corresponding active region column. The enable signal lines are arranged parallel to the active regions in the active region column and extend along the first direction. The first doped region and the first common doped region are located in the active regions on both sides of the gate line of the first antifuse transistor, respectively. The first common doped region and the second common doped region are located in the active regions on both sides of the gate line of the first select transistor, respectively. The second common doped region is electrically connected to the corresponding bit line; the first doped region is electrically connected to the corresponding enable signal line.

8. The antifuse array according to claim 7, characterized in that, Also includes: Multiple second selection transistor gate lines are arranged in parallel to each other and extend along a second direction. Each second selection transistor gate line covers multiple active regions within one row of active regions to define multiple second selection transistors arranged in an array. Multiple second antifuse transistor gate lines are arranged in parallel to each other and extend along a second direction. Each second antifuse transistor gate line covers multiple active regions within one row of active regions to define multiple second antifuse transistors arranged in an array.

9. The antifuse array according to claim 8, characterized in that, The multiple enable signal lines are arranged along a second direction and extend along the first direction, wherein each enable signal line and each active region column are arranged alternately in the second direction; The multiple bit lines are arranged in parallel to each other and extend along the first direction. Each bit line corresponds to an active region column, and each bit line is located above each corresponding active region column.

10. A method for operating an antifuse array, characterized in that, include: Provide an antifuse array as described in any one of claims 7-9; Perform programming or reading operations on the antifuse array.

11. The operating method according to claim 10, characterized in that, The programming operations include: Select the antifuse transistor to be programmed, apply a first voltage to the gate line of the antifuse transistor to be programmed, and leave the gate lines of other antifuse transistors floating. Leave all select transistor gate lines floating; A second voltage is applied to the enable signal line electrically connected to the antifuse transistor to be programmed; wherein, The absolute value of the difference between the first voltage and the second voltage is greater than the breakdown voltage of the gate dielectric layer of the antifuse transistor.

12. The operating method according to claim 10, characterized in that, The read operation includes: Select the antifuse transistor to be read, apply a third voltage to the gate line of the selected transistor that is electrically connected to the antifuse transistor to be read, and leave the gate lines of other selected transistors floating. A fourth voltage is applied to the bit line electrically connected to the antifuse transistor to be read, while the other bit lines are left floating. A fifth voltage is applied to the gate line of the antifuse transistor to be read, while the gate lines of other antifuse transistors are left floating. Leave all enable signal lines floating; among them, The third voltage is the turn-on voltage of the selection transistor, and the absolute value of the difference between the fourth voltage and the fifth voltage is less than the breakdown voltage of the gate dielectric layer of the antifuse transistor.

13. A memory, characterized in that, Includes the antifuse unit structure as described in any one of claims 1-6.

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