A dual-processor communication system

Abstract

The present invention provides a dual-processor communication system, including a main controller, an auxiliary controller, and a read-write memory. The auxiliary controller is configured to execute an internally stored program to implement the following steps: receiving a UART data packet sent by the main controller via a UART; reading the value of the corresponding address of the read-write memory via an I2C bus interface to determine whether the value of the corresponding address of the read-write memory matches the address of the read-write memory; if not, returning an error code to the main controller via the UART; if so, performing data acquisition according to control instructions to obtain acquired data; reporting the acquired data to the main controller based on the read-write memory data, and adjusting the current state based on the read-write memory data. This system aims to address the problems of existing dual-processor devices, such as frequent communication that occupies processor resources; data exchange that is prone to anomalies due to interference; and the need to reinitialize the original MCU control and state changes after a CPU failure restart.

Description

Technical Field

[0001] The present invention relates to the technical field of dual-processor communication, and in particular to a dual-processor communication system. Background Art

[0002] A dual-processor device contains two independent processors, each handling different tasks. This reduces the burden on a single processor, expands resources, and improves processing efficiency. Currently, the most common dual-processor devices on the market use UART communication. The CPU serves as the primary processor, primarily responsible for data processing and reporting, while the MCU serves as the secondary processor, primarily responsible for data acquisition and control.

[0003] Although dual-processor devices can expand resources and improve processing efficiency, existing dual-processor devices have problems such as frequent communication, which occupies processor resources; data interaction is prone to abnormalities due to interference; and the original MCU control needs to be reinitialized after the CPU fails and restarts, resulting in state changes.

[0004] In view of this, this application is filed. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a dual-processor communication system that can effectively solve the problems in the prior art of dual-processor devices, such as frequent communication, occupying processor resources; being easily disturbed and abnormal data interaction; and the need to reinitialize the original MCU control and state changes after the CPU fails and restarts.

[0006] The present invention discloses a dual-processor communication system, comprising: a main controller, an auxiliary controller, and a read-write memory, wherein the main controller and the auxiliary controller are electrically connected to the read-write memory via an I2C bus interface, and the main controller is electrically connected to the auxiliary controller via a UART communication protocol;

[0007] The auxiliary controller is configured to implement the following steps by executing a computer program stored therein:

[0008] Receiving a UART data packet sent by the main controller via UART, wherein the UART data packet includes a control instruction, a read-write memory address, and a read-write memory data;

[0009] Reading the value of the corresponding address of the read-write memory through the I2C bus interface, and determining whether the value of the corresponding address of the read-write memory matches the address of the read-write memory;

[0010] If not, an error code is returned to the main controller via UART;

[0011] If so, perform data collection according to the control instruction to obtain the collected data;

[0012] The collected data is reported to the main controller according to the read-write memory data, and the current state is adjusted according to the read-write memory data.

[0013] Preferably, the read-write memory is an EEPROM read-write memory.

[0014] Preferably, it also includes: a filter capacitor, a first pull-up resistor, and a second pull-up resistor, wherein the first end of the filter capacitor, the first end of the first pull-up resistor, and the first end of the second pull-up resistor are connected to a power supply, the clock interface of the main controller, the clock interface of the auxiliary controller, and the second end of the first pull-up resistor are electrically connected to the clock interface of the read-write memory, the data interface of the main controller, the data interface of the auxiliary controller, and the second end of the second pull-up resistor are electrically connected to the data interface of the read-write memory, and the second end of the filter capacitor is electrically connected to the control end of the read-write memory.

[0015] Preferably, the read-write memory data includes an active reporting flag, a reporting frequency parameter, and a control state holding flag.

[0016] Preferably, the collected data is reported to the main controller according to the read-write memory data, specifically:

[0017] When it is determined that the active reporting flag is 1, the collected data is reported to the main controller via UART according to the reporting frequency requirement of the reporting frequency parameter;

[0018] When it is determined that the active reporting flag is 0, wait for obtaining the acquisition command sent by the main controller.

[0019] Preferably, adjusting the current state according to the read-write memory data is specifically as follows:

[0020] When it is determined that the control state holding flag is 1, determining whether the main controller currently issues a control command;

[0021] If so, control is performed according to the control command currently issued by the main controller;

[0022] If not, maintain the current control status;

[0023] When it is determined that the control state holding flag is 0, the control state is held disabled.

[0024] Preferably, adjusting the current state according to the read-write memory data further includes:

[0025] When it is determined that the control state holding flag is 1 and the auxiliary controller is restarted, the previous control state of the auxiliary controller is maintained;

[0026] When it is determined that the control state holding flag is 0 and the auxiliary controller is restarted, the initial control state is restored and the control command sent by the main controller is waited for.

[0027] In summary, this embodiment provides a dual-processor communication system in which the main controller writes to the EEPROM via the I2C bus and transmits control acquisition / control instructions to the auxiliary controller via the UART. The auxiliary controller receives the instructions from the main controller via the UART and reads the value of the corresponding address in the EEPROM via the I2C interface to determine whether the instruction matches the EEPROM value. If so, the auxiliary controller executes the acquisition / control command; if not, the auxiliary controller does not execute the acquisition / control command. This solves the problems of conventional dual-processor devices, such as frequent communication that occupies processor resources; data exchange anomalies due to interference; and the need to reinitialize the original MCU control and state changes after a CPU failure restart. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic structural diagram of a dual-processor communication system provided by an embodiment of the present invention.

[0029] Figure 2 The present invention provides a dual-processor communication system. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention for which protection is sought, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0031] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] See also Figures 1 to 2A first embodiment of the present invention provides a dual-processor communication system, comprising: a main controller U2, an auxiliary controller U3, and a read-write memory U1, wherein the main controller U2 and the auxiliary controller U3 are electrically connected to the read-write memory U1 via an I2C bus interface, and the main controller U2 is electrically connected to the auxiliary controller U3 via a UART communication protocol;

[0033] Specifically, in this embodiment, the read-write memory U1 may be an EEPROM read-write memory.

[0034] Specifically, in this embodiment, it also includes: a filter capacitor C1, a first pull-up resistor R1, and a second pull-up resistor R2, wherein the first end of the filter capacitor C1, the first end of the first pull-up resistor R1, and the first end of the second pull-up resistor R2 are connected to a power supply, the clock interface of the main controller U2, the clock interface of the auxiliary controller U3, and the second end of the first pull-up resistor R1 are electrically connected to the clock interface of the read-write memory U1, the data interface of the main controller U2, the data interface of the auxiliary controller U3, and the second end of the second pull-up resistor R2 are electrically connected to the data interface of the read-write memory U1, and the second end of the filter capacitor C1 is electrically connected to the control end of the read-write memory U1.

[0035] Although dual-processor devices can expand resources and improve processing efficiency, existing dual-processor devices have problems such as frequent communication, which occupies processor resources; data interaction is prone to abnormalities due to interference; and the original MCU control needs to be reinitialized after the CPU fails and restarts, resulting in state changes.

[0036] In this embodiment, EEPROM (Electrically Erasable Programmable Read-Only Memory) refers to an electrically erasable programmable read-only memory (EPROM), a memory chip that maintains data even after a power outage. EEPROM can be erased and reprogrammed on a computer or dedicated device. It should be noted that other read-write memory structures of other types may be employed in other embodiments, and these are not specifically limited here, but all such solutions fall within the scope of protection of the present invention.

[0037] In this embodiment, a filter capacitor is an energy storage device installed at both ends of a rectifier circuit to reduce the AC ripple coefficient and improve efficient and smooth DC output. A filter capacitor has electrical polarity and is also called an electrolytic capacitor. The larger the capacitance, the better the filtering performance. The function of a pull-up resistor is to provide a current channel for the output of an open-drain output circuit. Pull-up clamps an uncertain signal to a high level through a resistor, which also acts as a current limiter.

[0038] The auxiliary controller U3 is configured to implement the following steps by executing a computer program stored therein:

[0039] S101, receiving a UART data packet sent by the main controller U2 via UART, wherein the UART data packet includes a control instruction, a read / write memory address, and a read / write memory data;

[0040] S102, reading the value of the address corresponding to the read-write memory U1 through the I2C bus interface, and determining whether the value of the address corresponding to the read-write memory U1 matches the read-write memory address;

[0041] S103, if not, return an error code to the main controller U2 via UART;

[0042] S104, if yes, perform data collection according to the control instruction to obtain collected data;

[0043] S105 , reporting the collected data to the main controller U2 according to the read-write memory data U1 , and adjusting the current state according to the read-write memory data.

[0044] Specifically, in this embodiment, the read-write memory data includes an active reporting flag, a reporting frequency parameter, and a control state holding flag.

[0045] In this embodiment, a storage area is set up at the EEPROM address to store configuration parameters. The active reporting flag bit is set to 1, indicating that active reporting is enabled. The auxiliary controller U3 collects data and then actively reports. A 0 indicates that active reporting is disabled. The auxiliary controller U3 waits for the main controller U2 to send a collection instruction via the serial port before reporting. The reporting frequency parameter is set to 1 only when the active reporting flag bit is set to 1.

[0046] In this embodiment, the control status retention flag is: 1 indicates that the control status is enabled. If the main controller U2 does not issue a control command, the auxiliary controller U3 maintains the last control status. If the auxiliary controller U3 is restarted, it also maintains the last control status; 0 indicates that the control status is not enabled. If the auxiliary controller U3 is restarted, it restores the initial control status and waits for the main controller U2 to issue a control command.

[0047] Specifically, step S105 includes: when it is determined that the active reporting flag is 1, reporting the collected data to the main controller U2 via UART according to the reporting frequency requirement of the reporting frequency parameter;

[0048] When it is determined that the active reporting flag is 0, wait for obtaining the acquisition command sent by the main controller U2.

[0049] When it is determined that the control state holding flag is 1, it is determined whether the main controller U2 currently issues a control command;

[0050] If yes, control is performed according to the control command currently issued by the main controller U2;

[0051] If not, maintain the current control status;

[0052] When it is determined that the control state holding flag is 0, the control state is held disabled.

[0053] When it is determined that the control state holding flag is 1 and the auxiliary controller U3 is restarted, the previous control state of the auxiliary controller U3 is maintained;

[0054] When it is determined that the control state holding flag is 0 and the auxiliary controller U3 is restarted, the initial control state is restored and the control command sent by the main controller U2 is waited for.

[0055] Specifically, in this embodiment, the main controller U2 writes to the EEPROM through the I2C bus, and transmits the acquisition / control instructions to the auxiliary controller U3 through the UART. The UART data sent by the main controller U2 contains control instructions and EEPROM address and data. The auxiliary controller U3 receives the instructions of the main controller U2 through the UART, and reads the value of the corresponding address of the EEPROM through the I2C interface for judgment. If it matches the EEPROM value, the auxiliary controller U3 executes the acquisition / control command. If it does not match the EEPROM value, the auxiliary controller U3 does not execute the acquisition / control command and returns an error code to the main controller U2 through the UART.

[0056] The auxiliary controller U3 reads the EEPROM active reporting flag. If it is 1, it sends it to the main controller U2 via UART according to the reporting frequency requirement. If it is 0, it waits for the main controller U2 to send a collection command. If the main controller U2 changes the EEPROM active reporting flag, it will synchronously notify the auxiliary controller U3 via UART to re-acquire the active reporting flag.

[0057] The auxiliary controller U3 reads the EEPROM control status hold flag. When it is 1, it controls according to the control command issued by the main controller U2. If the main controller U2 does not issue a control command, it maintains the existing control status. If the auxiliary controller U3 is restarted, the control status before the restart is maintained after the restart.

[0058] In summary, the dual-processor communication system improves communication reliability and stability through UART and EEPROM; reduces UART interaction data, reduces processor resource occupation; and reduces control state changes caused by processor anomalies.

[0059] The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention.

Claims

1. A dual-processor communication system, characterized in that include: A main controller, an auxiliary controller, and a read-write memory, wherein the main controller and the auxiliary controller are electrically connected to the read-write memory via an I2C bus interface, and the main controller is electrically connected to the auxiliary controller via a UART communication protocol; The auxiliary controller is configured to implement the following steps by executing a computer program stored therein: Receiving a UART data packet sent by the main controller via UART, wherein the UART data packet includes a control instruction, a read-write memory address, and a read-write memory data; The read-write memory data includes an active reporting flag, a reporting frequency parameter, and a control state holding flag; Reading the value of the corresponding address of the read-write memory through the I2C bus interface, and determining whether the value of the corresponding address of the read-write memory matches the address of the read-write memory; If not, an error code is returned to the main controller via UART; If so, perform data collection according to the control instruction to obtain the collected data; Reporting the collected data to the main controller according to the read-write memory data, and adjusting the current state according to the read-write memory data, specifically: When it is determined that the active reporting flag is 1, the collected data is reported to the main controller via UART according to the reporting frequency requirement of the reporting frequency parameter; When it is determined that the active reporting flag is 0, waiting to obtain the acquisition command sent by the main controller; When it is determined that the control state holding flag is 1, determining whether the main controller currently issues a control command; If so, control is performed according to the control command currently issued by the main controller; If not, maintain the current control status; When it is determined that the control state holding flag is 0, the control state is held disabled; When it is determined that the control state holding flag is 1 and the auxiliary controller is restarted, the previous control state of the auxiliary controller is maintained; When it is determined that the control state holding flag is 0 and the auxiliary controller is restarted, the initial control state is restored and the control command sent by the main controller is waited for.

2. A dual-processor communication system according to claim 1, characterized in that The read-write memory is an EEPROM read-write memory.

3. A dual-processor communication system according to claim 1, characterized in that: It also includes: a filter capacitor, a first pull-up resistor, and a second pull-up resistor, wherein the first end of the filter capacitor, the first end of the first pull-up resistor, and the first end of the second pull-up resistor are connected to a power supply, the clock interface of the main controller, the clock interface of the auxiliary controller, and the second end of the first pull-up resistor are electrically connected to the clock interface of the read-write memory, the data interface of the main controller, the data interface of the auxiliary controller, and the second end of the second pull-up resistor are electrically connected to the data interface of the read-write memory, and the second end of the filter capacitor is electrically connected to the control end of the read-write memory.

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