Buffer allocation for reducing block transfer loss

Abstract

The present disclosure relates to buffer allocation for reducing block shift loss. Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of a memory including a first block and a second block. A buffer for performing the write command is allocated to the first block. The buffer includes a plurality of buffer tiers and the buffer holds the user data written to the first block. User data is programmed into the first block up to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. The buffer tiers are invalidated in response to programming the first block to the threshold percentage. The buffer tiers are reallocated to a second block for programming the user data into the second block. The buffer tiers hold user data written to the second block.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to buffer allocation, and more specifically, to buffer allocation for reducing block transfer loss. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store and retrieve data at the memory devices. SUMMARY

[0003] In one aspect, the present disclosure provides a method comprising: receiving a write command including user data, wherein the write command is directed to a portion of a memory including a first block and a second block; allocating a buffer for performing the write command to the first block, the buffer comprising a plurality of buffer tiers, wherein the buffer holds the user data written to the first block; programming the user data into the first block up to a threshold percentage, wherein the threshold percentage is less than one hundred percent of the first block; invalidating a buffer tier of the plurality of buffer tiers in response to programming the first block to the threshold percentage; and reallocating the buffer tier to the second block for programming the user data into the second block, wherein the buffer tier holds the user data written to the second block.

[0004] In another aspect, the present disclosure provides a non-transitory computer- readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive a write command including user data, wherein the write command is directed to a portion of a memory including a first block and a second block; allocate a buffer for performing the write command to the first block, the buffer comprising a plurality of buffer tiers, wherein the buffer holds the user data written to the first block; program the user data into the first block up to a threshold percentage, wherein the threshold percentage is less than one hundred percent of the first block; invalidate a buffer tier of the plurality of buffer tiers in response to programming the first block to the threshold percentage; and reallocate the buffer tier to the second block for programming the user data into the second block, wherein the buffer tier holds the user data written to the second block.

[0005] In another aspect, the disclosure provides a system comprising: a plurality of memory devices; and a processing device operably coupled with the plurality of memory devices to: receive a write command including user data, wherein the write command is directed to a portion of a memory including a first block and a second block; allocate a buffer for performing the write command to the first block, the buffer comprising a plurality of buffer tiers, wherein the buffer holds the user data written to the first block, and wherein the first block and the second block are first type non-volatile memory elements and the buffer is a second type non-volatile memory element; program the user data into the first block up to a threshold percentage, wherein the threshold percentage is less than one hundred percent of the first block; and in response to programming the first block to the threshold percentage, invalidate a buffer tier of the plurality of buffer tiers; and reallocate the buffer tier to the second block for programming the user data into the second block, wherein the buffer tier holds the user data written to the second block. BRIEF DESCRIPTION OF DRAWINGS

[0006] The disclosure can be more completely understood in consideration of the following detailed description and the accompanying drawings, in which various embodiments of the disclosure are illustrated. However, the drawings are not intended to limit the disclosure to a specific embodiment, but are included simply to explain and understand.

[0007] Figure 1 An example computing system including a memory sub-system according to some embodiments of the disclosure is illustrated.

[0008] Figure 2 A block diagram of an example system including a buffer allocation component is illustrated.

[0009] Figure 3 Another block diagram of an example system including a buffer allocation component is illustrated.

[0010] Figure 4 A flow diagram of an example method to allocate buffers to reduce block transfer loss according to some embodiments of the disclosure is illustrated.

[0011] Figure 5 A flow diagram of another example method to allocate buffers to reduce block transfer loss according to some embodiments of the disclosure is illustrated.

[0012] Figure 6 A block diagram of an example computer system in which embodiments of the disclosure can operate is illustrated. DETAILED DESCRIPTION

[0013] Aspects of the disclosure relate to buffer allocation for reducing block transfer loss in a memory sub-system. The memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following description is made in connection withFigure 1 Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory sub-system that includes one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0014] A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. One example of a non-volatile memory device is a NAND memory device. The following description is made in connection with NAND memory devices, but is not limited to NAND memory devices. Figure 1 Other examples of non-volatile memory devices are described. A die in a package can be assigned to one or more channels for communication with a memory sub-system controller. Each die can be composed of one or more planes. Planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a group of physical blocks, which are groups of memory cells to store data. A cell is an electronic circuit that stores information.

[0015] Depending on the type of cell, a cell can store one or more bits of binary information and have various logical states related to the number of bits stored. The logical states can be represented by binary values (e.g., “0” and “1”) or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, an SLC can store one bit of information and have two logical states.

[0016] In conventional memory systems, defects introduced during manufacturing and operation can hinder a memory block from being properly programmed. In cases where a memory block containing a defect is attempted to be programmed, user data being written to the memory block is lost upon programming failure. To prevent data loss due to defects, user data being programmed into a memory block is saved in a buffer at the same time it is being programmed. Additionally, in cases where a consecutive memory block is programmed, an extra buffer is used to store the beginning of the consecutive block while the current block is not yet complete. For example, data programmed to a QLC block can be buffered in four SLC blocks. In consideration of programming consecutive blocks, a buffer of at least five SLC blocks (four SLC blocks to cover a current QLC block and one SLC block for the beginning of a consecutive QLC block) can be used when programming multiple QLC blocks to ensure no data loss due to defects. If there is no full coverage of a memory block to be programmed, defects in the memory block can cause programming failure and an increase in uncorrectable bit error rate (UBER). However, for QLC blocks that do not contain defects, a buffer of four SLC blocks is over-provisioned. Thus, there is a trade-off between UBER and over-provisioning to provide full buffer coverage of consecutive memory blocks.

[0017] Aspects of the disclosure address the above and other deficiencies by allocating a portion of a buffer to a consecutive block when programming of a current block has met a threshold percentage using buffer allocation. This eliminates the need for temporary buffers when programming consecutive memory blocks, thereby reducing over-provisioning. Because the portion of the buffer allocated to the consecutive block is selected based on a threshold percentage, the reallocated portion of the buffer has been fully programmed. Thus, there is no increase in UBER that would normally accompany a smaller buffer size. In other words, this buffer allocation scheme minimizes buffer space and corresponding over-provisioning loss while still providing sufficient defect coverage when programming consecutive memory blocks.

[0018] Figure 1 An example computing system 100 including a memory sub-system 110 in accordance with some embodiments of the disclosure is illustrated. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0019] The memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include a solid state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a Secure Digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMM).

[0020] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) capable device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including a memory and a processing device.

[0021] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1 One example of a host system 120 coupled to one memory sub-system 110 is described. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0022] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0023] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a small computer system interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports double data rate (DDR)), an open NAND flash interface (ONFI), double data rate (DDR), low power double data rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1 The memory sub-system 110 is illustrated. In general, a host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0024] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0025] Some examples of non-volatile memory devices (e.g., the memory devices 130) include negative-and (NAND) type flash memories and in-place writeable memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory can perform bit storage based on changes in bulk resistance in conjunction with stackable cross-grid data access arrays. Additionally, cross-point non-volatile memory can perform in-place write operations, where a non-volatile memory cell can be programmed without first erasing the non-volatile memory cell, as compared to many flash-based memories. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0026] Although non-volatile memory devices such as NAND-type memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells are described, the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-volatile (NOR) flash memory and electrically erasable programmable read-only memory (EEPROM).

[0027] The memory sub-system controller 115 (or simply the controller 115) can communicate with the memory devices 130 to perform operations at the memory devices 130 such as reading data, writing data, or erasing data, and other such operations (e.g., in response to commands scheduled by the controller 115 on a command bus). The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0028] The memory sub-system controller 115 can include a processing device 117 (processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0029] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetch data, etc. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 in Figure 1 In another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but instead relies upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system 110).

[0030] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or memory devices 140. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access memory devices 130 and / or memory devices 140 and convert responses associated with memory devices 130 and / or memory devices 140 into information for host system 120.

[0031] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0032] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory devices 130 are managed memory devices, which are raw memory devices combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0033] Memory sub-system 110 includes a buffer allocation component 113 that can allocate buffers to reduce block transfer loss. In some embodiments, controller 115 includes at least a portion of buffer allocation component 113. For example, controller 115 can include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, buffer allocation component 113 is part of host system 120, an application, or an operating system.

[0034] In programming the current block to the threshold percentage, the buffer allocation component 113 can allocate a portion of the buffer to the subsequent block. Further details regarding the operation of the buffer allocation component 113 are described below.

[0035] Figure 2 A block diagram illustrating an example system including the buffer allocation component 113 is shown. The buffer allocation component 113 programs the current memory block 205 with user data while concurrently storing the user data in a buffer including a first buffer block 210, a second buffer block 215, a third buffer block 220, and a fourth buffer block 225. Each of the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 includes a top tier and a bottom tier, such that the first buffer block 210 includes a first block top tier 235 and a bottom tier 240, the second buffer block 215 includes a second block top tier 245 and a bottom tier 250, the third buffer block 220 includes a third block top tier 255 and a bottom tier 260, and the fourth buffer block 225 includes a fourth block top tier 265 and a bottom tier 270.

[0036] In some embodiments, although only two tiers (top and bottom) of each buffer block are illustrated, each of the buffer blocks 210, 215, 220, and 225 can be divided into more than two tiers. For the purposes of this disclosure, the term tier refers to a subdivision of a memory block that can be independently programmed or erased. Thus, for a given size of block, the more tiers in a buffer block, the smaller the size of the tiers. In some embodiments, a tier can not be the smallest subdivision of a memory block and a tier can contain subdivisions within itself. It should be noted that each of the first block top tier 235 and bottom tier 240, the second block top tier 245 and bottom tier 250, the third block top tier 255 and bottom tier 260, and the fourth block top tier 265 and bottom tier 270 are subdivisions of their respective buffer blocks 210, 215, 220, and 225 and are illustrated for clarity.

[0037] In some embodiments, the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 are part of a local memory (e.g., the local memory 119 of the memory sub-system 100 Figure 1 In other embodiments, the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 are part of the buffer allocation component 113. Likewise, in some embodiments, the current memory block 205 is part of a memory device (e.g., the memory device 140 or 130 of the memory sub-system 100 Figure 1

[0038] ​In some embodiments, the current memory block 205 is composed of QLC. In such embodiments, each of the buffer blocks 210, 215, 220, and 225 holds an amount of data equal to one quarter of a QLC block (e.g., an SLC block). Thus, each of the first block top and bottom faces 235 and 240, the second block top and bottom faces 245 and 250, the third block top and bottom faces 255 and 260, and the fourth block top and bottom faces 265 and 270 hold an amount of data equal to one eighth of a QLC block or one half of an SLC block.

[0039] In other embodiments, the current memory block 205 is composed of another cell type (e.g., MLC or TLC) that lacks a data protection mechanism (e.g., independent NAND Redundancy Array (RAIN)). In such embodiments, the number of buffer blocks varies based on the cell type. For example, when the current memory block 205 is composed of TLC, three SLC blocks 210, 215, and 220 can provide sufficient buffer space. Likewise, when the current memory block 205 is composed of MLC, two SLC buffer blocks 210 and 215 would be sufficient. In these embodiments, each of the buffer block's faces holds an amount of data equal to the corresponding portion of the entire MLC or TLC block. For example, the memory block is composed of TLC and each buffer block is one third of the current memory block 205, holds an equal amount of data as an SLC. Thus, each of the buffer block's faces holds an amount of data equal to one sixth of a TLC block (e.g., the amount of data held in one half of an SLC block). In an alternative example, the memory block is composed of MLC and each buffer block is one half of the current memory block 205, holds an equal amount of data as an SLC. Thus, each of the faces holds an amount of data equal to one quarter of an MLC block (e.g., the amount of data held in one half of an SLC block).

[0040] The first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 serve as a defective backup in the event that the current memory block 205 fails to program. Thus, the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 are a cell / memory type with high reliability and low error potential. In some embodiments, the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 are SLC blocks and thus do not require multiple pass programming.

[0041] In some embodiments, the buffer allocation component 113 programs the current memory block 205 in multiple passes. For example, the buffer allocation component 113 can program the current memory block 205 in two passes, a first pass referred to as a coarse programming pass and a second pass referred to as a fine programming pass. The coarse programming pass does not contain all of the information needed to read the user data and thus the user data is stored elsewhere until the fine programming pass is complete. In contrast, after the buffer allocation component 113 performs the fine programming pass on the user data in the current memory block 205, there is enough information to read the user data.

[0042] In embodiments in which the buffer allocation component 113 programs the current memory block 205 using multiple pass programming, the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 have a dual function: (1) to prevent programming block failure of the current memory block 205 and (2) to provide a readable copy of the user data during the coarse programming pass. For example, the current memory block 205 is programmed in multiple passes, but the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 are not programmed. Thus, the buffer allocation component 113 programs a portion of the user data into the current memory block 205 through the coarse programming pass, while storing the portion of the user data in the first buffer block 210. Thus, the first buffer block 210 contains a fully programmed version of the portion of the user data for fine programming of the current memory block 205.

[0043] The firmware cursor 230 is a cursor that indicates the progress of the buffer allocation component 113 programming the current memory block 205. In some embodiments, the firmware cursor 230 indicates the progress of the buffer allocation component 113 performing the coarse programming pass. In such embodiments, Figure 2 The progress indicated by the firmware cursor 230 and the shaded portion of the current memory block 205 indicates the progress of the coarse programming pass on the current memory block 205.

[0044] The position of the firmware cursor 230 indicates that the buffer allocation component 113 has not yet completed the coarse programming pass of the entirety of the current memory block 205. Thus, the buffer allocation component 113 has also not yet completed programming the data also stored in the fourth buffer block 225. Furthermore, because the firmware cursor 230 has not reached the threshold percentage 275, the buffer allocation component 113 has not yet allocated any portion of the first buffer block 210, the second buffer block 215, the third buffer block 220, and the fourth buffer block 225 to the next memory block to be programmed.

[0045] Buffer allocation component 113 programs user data into current memory block 205 and stores the user data in first buffer block 210, second buffer block 215, third buffer block 220, and fourth buffer block 225. In some embodiments, buffer allocation component 113 stores user data in buffer blocks 210, 215, 220, and 225 and then programs the user data into current memory block 205. In other embodiments, buffer allocation component 113 concurrently programs user data into current memory block 205 while storing the user data in buffer blocks 210, 215, 220, and 225.

[0046] Each of first buffer block 210, second buffer block 215, third buffer block 220, and fourth buffer block 225 stores user data for a corresponding portion of current memory block 205. For example, first buffer block 210 stores user data for the first quarter (0 to 25%) of current memory block 205, second buffer block 215 stores user data for the second quarter (25 to 50%) of current memory block 205, third buffer block 220 stores user data for the third quarter (50 to 75%) of current memory block 205, and fourth buffer block 225 stores user data for the fourth quarter (75 to 100%) of current memory block 205.

[0047] Although threshold percentage 275 is shown at a certain point in current memory block 205, this illustration is for representative purposes only and different threshold percentages can be used for current memory block 205 depending on several variables including the time it takes for the controller (e.g., memory subsystem controller 115) to perform operations, the time it takes to queue future pages in memory, the speed of the controller / controller firmware, the efficiency of the controller / controller firmware, the size of the independent erasable / programmable layers, and the like. For example, threshold percentage 275 can be selected such that it is the highest percentage possible without causing latency issues in the firmware when switching from current memory block 205 to a subsequent memory block.

[0048] In some embodiments, first buffer block 210, second buffer block 215, third buffer block 220, and fourth buffer block 225 store related data for preventing defects in user data stored in current memory block 205, rather than storing user data. For example, first buffer block 210, second buffer block 215, third buffer block 220, and fourth buffer block 225 can store parity data associated with user data stored in current memory block 205.

[0049] Figure 3 A block diagram of an example system including buffer allocation component 113 is illustrated. As shown, buffer allocation component 113 is included in a memory subsystem 100.Figure 3 As shown in the middle, buffer allocation component 113 programs the current memory block 205 and the next memory block 310 with user data. Buffer allocation component 113 buffers the data in the first block top tier 235 and bottom tier 240, the second block top tier 245 and bottom tier 250, the third block top tier 255 and bottom tier 260, and the fourth block top tier 265 and bottom tier 270. In some embodiments, the current memory block 205 and the next memory block 310 are part of a memory device (e.g., memory device 140 or 130) of FIG. 1. Figure 1

[0050] In response to buffer allocation component 113 reaching the threshold percentage 275, as indicated by the progress of the firmware cursor 230, buffer allocation component 113 will allocate a portion of the buffer blocks 210, 215, 220, and 225 to the next memory block 310 to be programmed after the current memory block 205.

[0051] In some embodiments, the threshold percentage 275 is set to ensure that buffer allocation component 113 completes a fine programming pass of the portion of the current memory block 205 protected by the portion of the buffer blocks 210, 215, 220, and 225 allocated to the next memory block 310. For example, when buffer allocation component 113 has reached the threshold percentage 275, buffer allocation component 113 will have completed a fine programming pass of at least that portion of the current memory block 205 protected by the first block top tier 235. When multiple pass programming is used, for any given tier, a fine programming pass of that tier can begin before a coarse programming pass of the same tier is completed. Similarly, a fine programming pass of one tier can continue while a coarse programming pass of a subsequent tier is in progress.

[0052] Although the first block top tier 235 is shown as being allocated to the next memory block 310, different portions of the buffer can be allocated to the next memory block 310 depending on several variables including the time required for the controller (e.g., memory subsystem controller 115) of FIG. 1 to perform operations, the time required to queue future pages in memory, the speed of the controller / controller firmware, the efficiency of the controller / controller firmware, the size of the independently erasable / programmable tiers, and the like. Figure 1 For example, if a portion less than the first block top tier 235 is independently programmable and of a size such that no further portion will be required before the current memory block 205 is verified and the remainder of the buffer portion is freed for allocation to the next memory block 310, then that portion can be allocated to the next memory block 310.

[0053] ​In some embodiments, in response to the buffer allocation component 113 satisfying the threshold percentage 275 while programming the current memory block 205, the buffer allocation component 113 invalidates the data in the first block top tier 235 so that the data can be overwritten. In other embodiments, the buffer allocation component 113 clears the current block data in the first block top tier 235.

[0054] Once the firmware cursor 230 has exceeded the threshold percentage 275, there is a possibility that a programming block failure will cause the entire current memory block 205 to become unreadable. Even if there is a defect that causes a programming failure after the firmware cursor 230 exceeds the threshold percentage 275, a portion of the user data intended for the current memory block 205 will remain buffered in, for example, the first block bottom tier 240, the second block top tier 245 and bottom tier 250, the third block top tier 255 and bottom tier 260, and the fourth block top tier 265 and bottom tier 270. However, the portion of the data in the current memory block 205 that was buffered by the first block top tier 235 before the firmware cursor 230 reached the threshold percentage 275 can be lost. However, the additional seven-eighths of the buffered user data will still be recoverable from the buffer, reducing the likelihood of an increase to the UBER or at least maintaining the UBER within acceptable limits.

[0055] In some embodiments, once the buffer allocation component 113 completes programming the current memory block 205, the buffer allocation component 113 scans the current memory block 205 to verify correct programming. Once the buffer allocation component 113 has programmed and verified the current memory block 205, the buffer allocation component 113 allocates the remainder of the buffer (i.e., the first block bottom tier 240, the second block top tier 245 and bottom tier 250, the third block top tier 255 and bottom tier 260, and the fourth block top tier 265 and bottom tier 270) to the next memory block 310.

[0056] In some embodiments, in response to the buffer allocation component 113 allocating the first block bottom tier 240, the second block top tier 245 and bottom tier 250, the third block top tier 255 and bottom tier 260, and the fourth block top tier 265 and bottom tier 270 to the next memory block 310, the buffer allocation component 113 clears the data in the first block bottom tier 240, the second block top tier 245 and bottom tier 250, the third block top tier 255 and bottom tier 260, and the fourth block top tier 265 and bottom tier 270. In other embodiments, the buffer allocation component 113 invalidates the data in the first block bottom tier 240, the second block top tier 245 and bottom tier 250, the third block top tier 255 and bottom tier 260, and the fourth block top tier 265 and bottom tier 270 so that the data can be overwritten.

[0057] Figure 4is a flow diagram of an example method 400 to allocate a buffer to reduce block transfer loss according to some embodiments of the present disclosure. The method 400 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by the buffer allocation component 113 of the memory system 100. Figure 1 The order of the processes can be modified unless otherwise specifically specified. Accordingly, the illustrated embodiments should be understood that they are examples only and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

[0058] At operation 405, the processing device receives user data. For example, the processing device can receive a write command from a host system (e.g., the host system 120). The write command can include user data and a logical address. The processing device can translate the logical address to a physical address to determine a location to program the user data. For example, the processing device can translate the logical address to a physical address that points to a memory block (e.g., the current memory block 205).

[0059] At operation 410, the processing device stores the user data in a buffer. For example, the processing device programs the user data received at operation 405 into a buffer associated with the memory block (e.g., the current memory block 205). The buffer is composed of blocks, each of which includes a tier that can be independently programmed / erased. In some embodiments, the memory block is also composed of tiers that can be independently programmed / erased.

[0060] At operation 415, the processing device programs the current memory block. For example, the processing device programs the user data received at operation 405 into the memory block.

[0061] At operation 420, the processing device determines whether the programming of the current memory block has satisfied a threshold percentage. For example, the processing device determines whether the memory block has been programmed to or beyond the threshold percentage. If the processing device determines that the programming has satisfied the threshold percentage, the method 400 proceeds to operation 425. Otherwise, the method 400 returns to operation 415. In other words, the processing device continues to program the current memory block with user data until the processing device reaches the threshold percentage.

[0062] At operation 425, the processing device invalidates or otherwise frees the first buffer level for use as a buffer for a subsequent memory block. For example, the processing device can invalidate the data stored in the first buffer level, thereby allowing the contents of the first buffer level to be overwritten with data for a subsequent memory block. In some embodiments, the processing device deletes the data stored in the first buffer level as an alternative or in addition to invalidating the data. In some embodiments, the first level of the buffer is a level or similar subdivision of the block that is the smallest subdivision that can be independently programmed / erased.

[0063] At operation 430, the processing device stores the next block of user data in the first buffer level. For example, the processing device begins preparing to program the user data of the next block by allocating the first buffer level to the next block and loading a portion of the user data of the next block into the first buffer level.

[0064] At operation 435, the processing device determines whether the current block has completed programming. For example, because the threshold percentage is less than one hundred percent, the current memory block is still being programmed. When the current block has completed programming, the processing device proceeds to operation 440. Otherwise, the method 400 returns to operation 435.

[0065] At operation 440, the processing device changes the next block to the current block. In some embodiments, in response to determining that the current memory block has completed programming, the processing device scans the current memory block to verify the success of the programming operation. In response to the processing device determining that there were no failures in the programming operation (e.g., due to a defect in the current memory block), the processing device invalidates the user data stored in the remaining levels of the buffer and allocates the remaining levels of the buffer to the next memory block. In response to the processing device determining that there was a defect in the current memory block, the processing device uses the data stored in the buffer to correct the defect in the current memory block before invalidating the data stored in the remaining levels of the buffer and allocating the remaining levels of the buffer to the next memory block.

[0066] Figure 5is a flowchart of an example method 500 to allocate a buffer to reduce block transfer loss according to some embodiments of the present disclosure. The method 500 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by the buffer allocation component 113. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0067] At operation 505, the processing device receives a write command. For example, the processing device can receive a write command from a host system, such as the host system 120. The write command can include user data and a logical address. The processing device can translate the logical address to a physical address to determine a location to program the user data. For example, the processing device can translate the logical address to a physical address that points to a memory block, such as the current memory block 205.

[0068] At operation 510, the processing device allocates a buffer to the first block. For example, the processing device allocates a plurality of memory blocks, such as a plurality of memory blocks from the local memory 119, to use as a buffer while programming user data into a memory block, such as the current memory block 205. In some embodiments, in response to the processing device allocating the buffer to the first block, the processing device begins programming user data into the buffer.

[0069] At operation 515, the processing device programs the first block to a threshold percentage. For example, the processing device programs the user data received at operation 505 into the buffer allocated in operation 510. The processing device also programs the user data received at operation 405 into a memory block, such as the current memory block 205. In some embodiments, the processing device programs the user data in the buffer allocated at operation 510 and the current block concurrently. While the processing device programs the first memory block, the processing device determines when the programming of the first block satisfies the threshold percentage.

[0070] At operation 520, the processing device invalidates or otherwise frees the first buffer level for use as a buffer for a subsequent memory block. For example, in response to determining that the programming of the first block has satisfied the threshold percentage, the processing device can invalidate the data stored in the first buffer level, thereby allowing the contents of the first buffer level to be overwritten with data for a subsequent memory block. In some embodiments, the processing device deletes the data stored in the first buffer level instead of or in addition to invalidating the data. In some embodiments, the first level of the buffer is a level or similar subdivision of a block, which is the smallest subdivision that can be independently programmed / erased.

[0071] At operation 525, the processing device allocates the invalidated buffer level to a second block. For example, the processing device begins preparing to program user data for a next block by allocating the first buffer level to the next block and loading a portion of the user data of the next block into the first buffer level. In some embodiments, the first level of the buffer is a level or similar subdivision of a block, which is the smallest subdivision that can be independently programmed / erased.

[0072] Figure 6 An example machine of computer system 600 is illustrated in FIG. 6. The example machine is capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, the example machine can be a special-purpose machine or a general-purpose machine. The example machine can operate as a standalone device or can be coupled (e.g., networked) to other machines in a networked environment. Figure 1 Figure 1 In some embodiments, computer system 600 can correspond to a host system (e.g., host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., memory sub-system 110 of FIG. 1), or can be used to perform operations of a controller (e.g., to execute an operating system to perform operations corresponding to buffer allocation component 113 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in a cloud computing infrastructure or environment. Figure 1

[0073] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0074] ​​The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0075] Processing device 602 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or

[0076] Data storage system 618 can include a machine-readable storage medium 624 (also known as computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 can also reside, completely or at least partially, within the main memory 604 and / or processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, data storage system 618, and / or main memory 604 can correspond to memory subsystem 110 of FIG. 1. Figure 1

[0077] In one embodiment, the instructions 626 include instructions to implement functionality corresponding to a buffer allocation component (e.g., buffer allocation component 113 of FIG. 1). While the machine-readable storage medium 624 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. Figure 1

[0078] ​​Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0079] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0080] The disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system (e.g., controller 115) can perform the computer-implemented methods 400 and 500 in response to processor executing one or more sequences of instructions contained in memory or other non-transitory machine-readable storage medium. This computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0081] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0082] The present disclosure can be provided as a computer program product or software, which can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0083] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples thereof. It will be evident that various modifications can be made to the application without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method comprising: receiving a write command including user data, wherein the write command is directed to a portion of memory including a first block and a second block and wherein the user data comprises a first segment and a second segment; allocating a buffer for performing the write command to program the first segment of the user data to the first block, the buffer comprising a plurality of buffer tiers; programming a first portion of the first segment of the user data to a first buffer tier of the plurality of buffer tiers; programming the first block to a threshold percentage, wherein the threshold percentage is less than one hundred percent of the first block; deactivating the first buffer tier in response to programming the first block to the threshold percentage; re-allocating the first buffer tier to the second block for programming the second segment of the user data to the second block; and programming a second portion of the second segment of the user data to the first buffer tier.

2. The method of claim 1, wherein the threshold percentage is determined based on controller speed and controller efficiency.

3. The method of claim 1, wherein the first block and the second block are first type of non-volatile memory elements and the buffer is a second type of non-volatile memory element.

4. The method of claim 3, wherein the second type of non-volatile memory element is capable of being programmed in a single pass.

5. The method of claim 4, wherein the first type of non-volatile memory element is a four-level cell.

6. The method of claim 1, wherein the first portion of the first segment of the user data is programmed before other portions of the first segment of the user data are programmed into the first block.

7. The method of claim 1, wherein the buffer simultaneously holds portions of the first segment of the user data and the second segment of the user data.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive a write command including user data, wherein the write command is directed to a portion of memory including a first block and a second block and wherein the user data comprises a first segment and a second segment; allocate a buffer for performing the write command to program the first segment of the user data to the first block, the buffer comprising a plurality of buffer tiers; program a first portion of the first segment of the user data to a first buffer tier of the plurality of buffer tiers; program the first block to a threshold percentage, wherein the threshold percentage is less than one hundred percent of the first block; deactivate the first buffer tier in response to programming the first block to the threshold percentage; re-allocate the first buffer tier to the second block for programming the second segment of the user data to the second block; and program a second portion of the second segment of the user data to the first buffer tier.

9. The method of claim 1, wherein the buffer is a first buffer tier of a plurality of buffer tiers. ​ 9. The non-transitory computer readable storage medium of claim 8, wherein the threshold percentage is determined based on a controller speed and a controller efficiency.

10. The non-transitory computer readable storage medium of claim 8, wherein the first block and the second block are a first type of non-volatile memory element and the buffer is a second type of non-volatile memory element.

11. The non-transitory computer readable storage medium of claim 10, wherein the second type of non-volatile memory element is capable of being programmed in a single pass.

12. The non-transitory computer readable storage medium of claim 11, wherein the first type of non-volatile memory element is a four-level cell.

13. The non-transitory computer readable storage medium of claim 8, wherein the first portion of the first segment of user data is programmed prior to other portions of the first segment of user data being programmed into the first block.

14. The non-transitory computer readable storage medium of claim 8, wherein the buffer holds portions of the first segment of user data and the second segment of user data simultaneously.

15. A system comprising: a plurality of memory devices; and a processing device operably coupled with the plurality of memory devices to: receive a write command including user data, wherein the write command is directed to a portion of memory including a first block and a second block and wherein the user data comprises a first segment and a second segment; allocate a buffer for performing the write command to program the first segment of user data to the first block, the buffer comprising a plurality of buffer tiers and wherein the first block and the second block are a first type of non-volatile memory element and the buffer is a second type of non-volatile memory element; program a first portion of the first segment of user data to a first buffer tier of the plurality of buffer tiers; program the first block to a threshold percentage, wherein the threshold percentage is less than one hundred percent of the first block; de-allocate the first buffer tier in response to programming the first block to the threshold percentage; re-allocate the first buffer tier to the second block for programming a second segment of user data to the second block; and program a second portion of the second segment of user data to the first buffer tier.

16. The system of claim 15, wherein the threshold percentage is determined based on a controller speed and a controller efficiency.

17. The system of claim 15, wherein the second type of non-volatile memory element is capable of being programmed in a single pass.

18. The system of claim 17, wherein the first type of non-volatile memory element is a four-level cell.

19. The system of claim 15, wherein the first portion of the first segment of user data is programmed prior to other portions of the first segment of user data being programmed into the first block. ​ 20. The system of claim 15, wherein the buffer concurrently holds portions of the first segment of the user data and the second segment of the user data.

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