Simulation method, device and storage medium

Abstract

Provided are an emulation method, device, and storage medium. The method includes creating a first analog circuit, the first analog circuit including a plurality of sub-circuits, the circuit structures of the plurality of sub-circuits being identical to the circuit structure of a to-be-optimized circuit, and the plurality of sub-circuits corresponding to a plurality of design parameters of the to-be-optimized circuit one-to-one, the first analog circuit having a shared end of the plurality of sub-circuits and a plurality of output ends corresponding to the plurality of sub-circuits one-to-one; performing emulation on the first analog circuit to obtain a plurality of emulation results corresponding to the plurality of sub-circuits; and selecting a target design parameter from the plurality of design parameters as an optimization result of the to-be-optimized circuit according to the plurality of emulation results. Embodiments of the application combine a plurality of sub-circuits corresponding to a plurality of design parameters of a to-be-optimized circuit into one analog circuit, obtain a plurality of emulation results of the to-be-optimized circuit through one emulation on the analog circuit, and help reduce the optimization time.

Description

Technical Field

[0001] This application relates to the field of simulation technology, and more specifically, to a simulation method, apparatus, and storage medium. Background Technology

[0002] When performing simulation-based circuit optimization on a circuit to be optimized, the optimization result is determined by evaluating multiple design parameters of the circuit. To evaluate these multiple design parameters, multiple simulation operations are required. The iterative simulation process consumes a significant amount of time, resulting in low optimization efficiency. Summary of the Invention

[0003] This application provides a simulation method, apparatus, and storage medium. The various aspects involved in this application's embodiments are described below.

[0004] In a first aspect, a simulation method is provided, the method comprising: creating a first analog circuit, the first analog circuit comprising multiple sub-circuits, the circuit structure of each of the multiple sub-circuits being identical to the circuit structure of a circuit to be optimized, and each of the multiple sub-circuits corresponding one-to-one with multiple design parameters of the circuit to be optimized, the first analog circuit having a shared terminal of the multiple sub-circuits and multiple output terminals corresponding one-to-one with the multiple sub-circuits; simulating the first analog circuit to obtain multiple simulation results corresponding one-to-one with the multiple sub-circuits; and selecting a target design parameter from the multiple design parameters based on the multiple simulation results as the optimization result of the circuit to be optimized.

[0005] Secondly, a simulation apparatus is provided, comprising: a creation unit for creating a first analog circuit, the first analog circuit including multiple sub-circuits, the circuit structures of the multiple sub-circuits being identical to the circuit structure of the circuit to be optimized, and the multiple sub-circuits corresponding one-to-one with multiple design parameters of the circuit to be optimized, the first analog circuit having a shared terminal of the multiple sub-circuits and multiple output terminals corresponding one-to-one with the multiple sub-circuits; a simulation unit for simulating the first analog circuit to obtain multiple simulation results corresponding one-to-one with the multiple sub-circuits; and a determination unit for selecting target design parameters from the multiple design parameters based on the multiple simulation results, as the optimization result of the circuit to be optimized.

[0006] Thirdly, a simulation apparatus is provided, including a memory and a processor, wherein the memory stores executable code and the processor is configured to execute the executable code to implement the method as described in the first aspect.

[0007] Fourthly, a computer-readable storage medium is provided having executable code stored thereon, which, when executed, enables the implementation of the method described in the first aspect.

[0008] Fifthly, a computer program product is provided, including executable code, which, when executed, enables the implementation of the method described in the first aspect.

[0009] This application embodiment connects multiple circuits to be optimized with different design parameters into a first analog circuit, and obtains multiple optimization results for the circuit to be optimized by simulating the first analog circuit. Therefore, for the multiple design parameters of the circuit to be optimized, this application embodiment does not directly perform multiple simulations of the circuit to be optimized, but instead writes these design parameters into a combinational circuit and performs the simulation of the combinational circuit only once. Thus, the number of operations for some processes in the simulation calculation is reduced from multiple times to one, which helps to reduce the optimization time and improve the optimization efficiency. Attached Figure Description

[0010] Figure 1 The diagram shown is a flowchart of a certain iteration in simulation-based circuit optimization in related technologies.

[0011] Figure 2 The diagram shown is a flowchart of a simulation method provided in an embodiment of this application.

[0012] Figure 3 As shown Figure 2 The method shown is a flowchart illustrating a certain iteration in simulation-based circuit optimization.

[0013] Figure 4 As shown Figure 2 A schematic diagram of an example of the circuit to be optimized in the method shown.

[0014] Figure 5 As shown Figure 4 The circuit structure diagram shown is pieced together. Figure 2 A schematic diagram of the structure of the first analog circuit.

[0015] Figure 6 The diagram shown is a schematic flowchart of the simulation-based circuit optimization provided in an embodiment of this application.

[0016] Figure 7 The diagram shown is a structural schematic of a simulation device provided in an embodiment of this application.

[0017] Figure 8 The diagram shown is a structural schematic of a simulation device provided in another embodiment of this application. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0019] In the design and development of analog circuits, simulation software can be used to accurately evaluate circuit performance. Examples of simulation software include simulation programs with integrated circuit emphasis (SPICE). Automated analog circuit design is a simulation-based circuit optimization method. In some embodiments, automated analog circuit design is an optimization method utilizing a SPICE simulator.

[0020] Simulation-based circuit optimization methods typically rely on optimization algorithms to iterate through the circuit to be optimized. In some embodiments, these algorithms can be intelligent algorithms such as genetic algorithms, ant colony optimization, and particle swarm optimization. These intelligent algorithms operate on a population. During iteration, the size of each generation of the population is often fixed, for example, a fixed number n. Each individual in the population corresponds to the circuit to be optimized under a set of design parameters. Through iteration, the population can be continuously updated towards optimization.

[0021] In the process of circuit optimization, the basic circuit structure of the circuit to be optimized remains unchanged; what usually changes are some design parameters. These design parameters include, for example, transistor length, resistance, and capacitance. Through continuous iteration, the design parameters of the circuit to be optimized are constantly updated until design parameters that meet the requirements are found.

[0022] During each iteration, the circuit to be optimized needs to be simulated based on the design parameters of the current generation. In some embodiments, each update requires simulation of each design parameter of the circuit to be optimized in the current generation. For example, when the current generation population size is 5, the circuit to be optimized has 5 sets of design parameters. When optimizing the current generation population of size 5, 5 simulations of the 5 sets of design parameters of the circuit to be optimized need to be performed separately.

[0023] For ease of understanding, let's take a population size of n as an example, combined with... Figure 1 The iterative process of a simulation-based circuit optimization method is described.

[0024] See Figure 1 In step S110, the size of the current generation population is determined to be n. The current generation of the circuit to be optimized has n sets of design parameters, corresponding to n individuals in the population.

[0025] In step S120, the design parameters of the i-th individual in the population are written into the circuit netlist. The initial value of i is 1, and i≤n.

[0026] In step S130, the i-th population individual from step S120 is simulated.

[0027] In step S140, the individual fitness evaluation function value is calculated. The fitness of the i-th population individual is evaluated based on the simulation results, and individuals that meet the fitness requirements are selected. This selection determines the optimization direction of the population.

[0028] In step S150, determine whether i is equal to n. If i = n, proceed to step S170. If i ≠ n, proceed to step S160.

[0029] In step S160, i is incremented by 1 to obtain a new value, and steps S120 to S150 are repeated until i = n. Therefore, the number of times steps S120 to S150 are executed is the same as the number of elements in the current generation population. In other words, the number of operations in the circuit netlist writing, simulation, and other processes is equal to the number of elements in the current generation population.

[0030] In step S170, the current generation optimization ends.

[0031] Depend on Figure 1 It is known that when the iteration of the circuit to be optimized reaches the current generation, each of the n individuals in the population needs to be optimized individually. Therefore, a population size of n means that the circuit to be optimized needs to be simulated n times. For a complete optimization, assuming that the population size of each generation is n and the number of iterations is m, then m×n simulations are required. Thus, while simulation-based optimization methods have advantages such as data accuracy, the multiple simulations during iterations significantly increase the optimization time. Furthermore, this impacts the optimization efficiency of the circuit. In other words, the simulation process consumes a significant amount of time, making it unsuitable for projects with tight timelines.

[0032] Specifically, during each simulation, the simulation software needs to execute all steps of the simulation process. Taking the SPICE simulator as an example, the simulation operation process mainly includes: initializing the SPICE simulator, writing the optimization parameters into the circuit netlist (circuit netlist update), simulation, result output, and result parsing.

[0033] For a complete optimization, the aforementioned m×n simulations require repeating the SPICE simulator initialization, circuit netlist update, simulation, result output, and parsing operations m×n times. Therefore, for typical analog circuits, this time consumption significantly increases the total optimization time and impacts project schedule.

[0034] Specifically, in a single iteration, if an iteration requires n simulations of the circuit to be optimized, it necessitates initializing the SPICE simulator n times, writing the optimization parameters into the circuit netlist n times, and outputting and parsing the results n times. This repetitive simulation process significantly increases the optimization time of the current iteration and reduces optimization efficiency.

[0035] To address some or all of the aforementioned problems, this application proposes a simulation method. This simulation method reduces the simulation time for each iteration of the circuit to be optimized by improving the circuit and algorithm. Furthermore, by reducing the simulation time for each iteration, the optimization time can be effectively reduced. The following is a detailed explanation... Figure 2 The simulation method proposed in the embodiments of this application will be described in detail.

[0036] See Figure 2 In step S210, the first analog circuit is created.

[0037] The first analog circuit comprises multiple sub-circuits. These sub-circuits are connected in a predetermined manner to form the first analog circuit. The circuit structures of all the sub-circuits are identical to those of the circuit to be optimized, thus enabling the simulation calculations of the circuit to be optimized to be performed through the first analog circuit.

[0038] Sub-circuits can be implemented in various ways. In some embodiments, sub-circuits can be obtained by copying the circuit to be optimized. Multiple sub-circuits can be obtained by copying the circuit to be optimized multiple times. In other embodiments, sub-circuits can be obtained by simplifying the circuit to be optimized without changing the circuit structure.

[0039] The circuit to be optimized can be a relatively simple, small analog circuit, such as a MOS transistor amplifier. Alternatively, it can be a general-scale analog circuit.

[0040] The circuit to be optimized has different design parameters. In each iteration, the circuit to be optimized needs to simulate multiple design parameters, or multiple sets of design parameters, which are not limited here.

[0041] Multiple sub-circuits can be one-to-one corresponded to multiple design parameters of the circuit to be optimized. Multiple sub-circuits can also be one-to-one corresponded to multiple sets of design parameters of the circuit to be optimized through combinations of different design parameters.

[0042] The number of sub-circuits can be the same as the number or groups of design parameters that need to be simulated in the circuit to be optimized. For example, in a population optimization algorithm, the number of sub-circuits can be the same as the size of the current generation of the population. That is, multiple sub-circuits correspond one-to-one with multiple individuals in the population through multiple design parameters.

[0043] Multiple design parameters corresponding to multiple sub-circuits can constitute all the design parameters of the first analog circuit. In the first analog circuit, each sub-circuit can have a set of design parameter variable values. Each sub-circuit can correspond to a single design parameter or a set of design parameters. In some embodiments, a single design parameter can be a parameter such as transistor length and width, resistance, or capacitance. For example, in a sub-circuit after splicing MOS transistor amplifiers, only the transistor length of MOS transistor T1 is different from that of other sub-circuits. In other embodiments, a set of design parameters can be different combinations of circuit parameters such as transistor length and width, resistance, and capacitance. For example, in a sub-circuit after splicing MOS transistor amplifiers, both the resistance and capacitance are different from those of other sub-circuits.

[0044] The first analog circuit can be created from multiple sub-circuits according to certain rules. Since the multiple sub-circuits have the same circuit structure, their external ports are identical. In some embodiments, the first analog circuit can define a shared terminal for the multiple sub-circuits. Through this shared terminal, some external ports of the multiple sub-circuits can be directly connected. In other embodiments, the multiple sub-circuits can be assembled into the first analog circuit according to other rules.

[0045] The shared terminals of the first analog circuit can be determined according to the circuit structure. In some embodiments, the shared terminals of the first analog circuit include one or more of the following: a power supply voltage terminal, positive and negative input terminals, and a ground terminal.

[0046] The first analog circuit may have one input terminal or multiple input terminals. In some embodiments, the first analog circuit can input the same input parameter to multiple sub-circuits through a shared input terminal. In other embodiments, the first analog circuit can input different or the same input parameters to multiple sub-circuits through multiple input terminals.

[0047] The first analog circuit can have multiple output terminals. These output terminals can correspond one-to-one with the output terminals of multiple sub-circuits. Through the multiple output terminals of the multiple sub-circuits, multiple operating results of the circuit to be optimized under different design parameters can be obtained.

[0048] Compared to a single circuit to be optimized, the first analog circuit is a large circuit that combines multiple circuits to be optimized. For ease of understanding, this will be discussed later in conjunction with... Figure 4 and Figure 5 A detailed comparison and description of the circuit to be optimized and the first analog circuit will not be repeated here.

[0049] In step S220, the first analog circuit is simulated to obtain multiple simulation results corresponding to multiple sub-circuits.

[0050] The design parameters of the first analog circuit consist of multiple design parameters of multiple sub-circuits, and the first analog circuit can be simulated based on multiple design parameters.

[0051] For the first analog circuit, simulation can be performed according to the procedures of different simulators. Taking the SPICE simulator as an example, multiple design parameters can be written into the circuit netlist of the first analog circuit at once, and then the SPICE simulator can be used to simulate the first analog circuit once.

[0052] Simulating the first analog circuit yields multiple simulation results. As mentioned earlier, the first analog circuit has multiple output terminals, and the simulation results can also be referred to as output results. During the simulation process, multiple output terminals can output multiple simulation results. These multiple simulation results can be correlated one-to-one with the multiple sub-circuits of the first analog circuit.

[0053] In step S230, based on multiple simulation results, target design parameters are selected from multiple design parameters as the optimization result of the circuit to be optimized.

[0054] Multiple simulation results are mapped one-to-one with multiple design parameters through multiple sub-circuits. By evaluating multiple simulation results, the target design parameters can be selected from among the various design parameters.

[0055] To make a selection, multiple simulation results can be evaluated directly, or the simulation results can be calculated and then evaluated. In some embodiments, multiple design parameters correspond to multiple individuals in the current population. Individual fitness evaluations can be performed on multiple simulation results to obtain evaluation results corresponding to multiple individuals. Then, based on the evaluation results corresponding to multiple individuals, the target design parameter is selected from the multiple design parameters.

[0056] The target design parameters can be one or more design parameters, depending on the optimization requirements. As the optimization result of each iteration, the target design parameters can be continuously updated until the predetermined design requirements are met.

[0057] Combined with the preceding text Figure 2 The simulation method of this application embodiment has been described. When this simulation method is used for simulation-based circuit optimization, simulation can be performed only once per iteration.

[0058] To facilitate understanding, the following will be combined with Figure 3 still Figure 1 Taking a population size of n as an example, for Figure 2 The first analog circuit is used for a detailed description of the simulation-based circuit optimization process.

[0059] See Figure 3 Step S310 and Figure 1 The steps are the same as in step S110. However, Figure 3 The population size corresponds to the number of sub-circuits in the first analog circuit, therefore the first analog circuit includes n sub-circuits.

[0060] In step S320, the design parameters of all individuals in the current generation are written into the circuit netlist. The design parameters of the n sub-circuits of the first analog circuit correspond to the n individuals in the current generation. Therefore, the design parameters of the n individuals need to be written into the circuit netlist of the first analog circuit all at once. Figure 1 Step S120 involves writing the design parameters to each individual in the population; n individuals require n writes.

[0061] In step S330, the first analog circuit is simulated using a simulator. Figure 1 Step S130 also involves simulating each individual in the population; n individuals require n simulations.

[0062] In step S340, the simulation results of the first analog circuit are output. The n output terminals of the first analog circuit can output the simulation results of n individuals in the population.

[0063] Step S350 and Figure 1 The process is the same as step S140, calculating the fitness evaluation function value for each individual in the population. Based on the fitness evaluation function value, the target design parameters can be selected as the optimization result for the current generation.

[0064] Step S360 and Figure 1 The process is the same as step S170, ending the current generation optimization.

[0065] contrast Figure 1 and Figure 3 It can be seen that, Figure 3 Steps S320 to S340 completed the updating, simulation, and output of the circuit netlist for all individuals in the population. Therefore, Figure 3 No need to repeat execution Figure 1 Steps S120 to S160 are shown. In other words, the embodiments of this application improve the optimization of a single sub-circuit into the optimization of a large circuit after splicing, which greatly reduces the time consumption of unnecessary steps in the automated design process of analog circuits.

[0066] To describe more clearly Figure 2 The application of the method shown below will be combined with... Figure 4 and Figure 5 Examples are given to illustrate the creation of the circuit to be optimized and the first analog circuit.

[0067] Figure 4 The diagram shows a circuit diagram of a MOS transistor-level amplifier to be optimized. Given a fixed circuit structure, it is necessary to find a set of circuit design parameters that meet the predetermined design requirements for this MOS transistor-level amplifier.

[0068] like Figure 4 As shown, the external interfaces of the MOSFET amplifier 40 mainly include the power supply voltage terminal (VDD), positive input terminal (IN+), negative input terminal (IN-), ground terminal (VSS), and output terminal (OUT). The MOSFET amplifier 40 also includes several components, MOSFETs T1 to T8, resistor R1, and capacitors.

[0069] right Figure 4 The MOS transistor amplifier 40 shown is replicated. Assuming the population size in each generation of the iterative optimization is n, and the number of replications is n, n sub-circuits are obtained. These n sub-circuits are then combined into a larger circuit to obtain... Figure 5 The first analog circuit 50 shown.

[0070] like Figure 5 As shown, the first analog circuit 50 includes n sub-circuits, namely sub-circuit 51, sub-circuit 52, ..., sub-circuit 5n. The circuit structure of each sub-circuit is the same as that of the MOS transistor amplifier 40. Therefore, the number of components in the first analog circuit 50 is n times that of the MOS transistor amplifier 40. For example, the MOS transistor amplifier 40 includes one resistor R1, and the first analog circuit 50 includes n resistors, namely R11, R21, ..., Rn1.

[0071] Each sub-circuit corresponds to a set of design parameter variables for the MOS transistor amplifier 40, such as transistor length, resistance, and capacitance. Therefore, the large netlist of the first analog circuit 50 contains the design parameters for all sub-circuits.

[0072] The first analog circuit 50 has multiple shared terminals. Specifically, each sub-circuit shares the power supply voltage terminal (VDD), positive and negative input terminals (IN+, IN-), and ground terminal (VSS). However, each sub-circuit of the first analog circuit 50 has its own output terminals OUT1, OUT2, ..., OUTn.

[0073] Compared to the MOS transistor amplifier 40 to be optimized, the first analog circuit 50 is essentially a miniature MOS transistor amplifier 40 copied n times and then combined. Because the MOS transistor amplifier 40 is assembled according to certain rules, the only difference between the external interfaces of the first analog circuit 50 and the MOS transistor amplifier 40 is the number of its output terminals, which is n times the number of the output terminals. In other words, if the circuit to be optimized is a single-input single-output circuit, the first analog circuit can be a single-input multiple-output circuit.

[0074] The above text is based on Figure 4 and Figure 5 For example, for Figure 2 Step S210 in the method shown is described in detail. It should be understood that... Figure 4 The analog circuit of the MOS transistor amplifier shown is merely an example; the simulation method proposed in this application is applicable to all analog circuits. The following examples illustrate this. Figure 4 , Figure 5 Taking population algorithms as an example, combined with Figure 6 The simulation method provided in this application is described in detail as a complete simulation-based circuit optimization process.

[0075] See Figure 6 In step S610, the current circuit to be optimized is copied n times and spliced ​​together to form a large circuit. The current circuit to be optimized is a MOS transistor amplifier 40. After copying n times and splicing them together, a first analog circuit 50 including n sub-circuits is obtained.

[0076] In step S620, the design parameters of all individuals in the current population are written into the circuit netlist, simulation is performed, and n output results are obtained. All design parameters of the current population are written into the large netlist of the first analog circuit 50 at once. The first analog circuit 50 is simulated once using a simulator. The simulator can be a SPICE simulator.

[0077] Simulation results were obtained by simulating the first analog circuit 50. As mentioned earlier, the first analog circuit 50 has n output terminals, and simulation results with n outputs can be obtained.

[0078] In step S630, the fitness evaluation function value of each of the n output results is calculated.

[0079] In step S640, based on the population fitness function evaluation value, the superior and inferior populations are classified and a progeny population is generated. Classifying the superior and inferior populations is equivalent to selecting the target design parameters for the current MOS transistor amplifier 40. These target design parameters become the progeny population.

[0080] In step S650, determine whether the predetermined number of iterations has been reached. If yes, proceed to step S660. If no, return to step S620, begin the next iteration, and repeat steps S620 to S650.

[0081] In step S660, the simulation-based circuit optimization ends.

[0082] Depend on Figure 6 It can be seen that for a complete optimization, the number of simulations can be the same as the number of iterations. Taking the SPICE simulator as an example, Figure 6 Each iteration in the process only requires one initialization of the SPICE simulator, updating of the circuit netlist, simulation, result output, and parsing. Figure 1 The related technologies shown repeat the simulation operation n times in each iteration, so the embodiments of this application can greatly improve the optimization efficiency of analog circuits.

[0083] It should be understood that all intelligent algorithms based on iterative optimization are applicable to the automated analog circuit design scheme proposed in the embodiments of this application. The population algorithm described above is only an example and is not intended to limit the automated analog circuit design scheme.

[0084] The above text combined Figures 2 to 6 The method embodiments of this application are described in detail below, in conjunction with... Figure 7 and Figure 8 The present application provides a detailed description of the apparatus embodiments. It should be understood that the descriptions of the method embodiments correspond to the descriptions of the apparatus embodiments; therefore, any parts not described in detail can be found in the foregoing method embodiments.

[0085] Figure 7 This is a schematic diagram of the structure of a simulation device provided in an embodiment of this application. Figure 7 The simulation device 700 shown includes a creation unit 710, a simulation unit 720, and a determination unit 730.

[0086] The creation unit 710 can be used to create a first analog circuit. The first analog circuit includes multiple sub-circuits, the circuit structures of which are the same as those of the circuit to be optimized, and each of the multiple sub-circuits corresponds to a multiple design parameter of the circuit to be optimized. The first analog circuit has a shared terminal of the multiple sub-circuits and multiple output terminals that correspond to each of the multiple sub-circuits.

[0087] The simulation unit 720 can be used to simulate the first analog circuit and obtain multiple simulation results corresponding to multiple sub-circuits.

[0088] The determination unit 730 can be used to select target design parameters from multiple design parameters based on multiple simulation results, as the optimization result of the circuit to be optimized.

[0089] Optionally, as one possible implementation, the shared terminal includes one or more of the following: a power supply voltage terminal, positive and negative input terminals, and a ground terminal.

[0090] Optionally, as a possible implementation, the creation unit is also used to copy the circuit to be optimized multiple times to obtain multiple sub-circuits; and to splice the multiple sub-circuits to obtain the first analog circuit.

[0091] Optionally, as a possible implementation, multiple design parameters correspond one-to-one with multiple individuals in the current population, and the determining unit is also used to evaluate the individual fitness of multiple simulation results to obtain evaluation results corresponding to multiple individuals; based on the evaluation results corresponding to multiple individuals, the target design parameter is selected from multiple design parameters.

[0092] Optionally, as a possible implementation, the simulation unit is also used to write multiple design parameters into the circuit netlist of the first analog circuit; and to perform a simulation of the first analog circuit using a SPICE simulator to obtain multiple simulation results.

[0093] Figure 8 The diagram shown is a structural schematic of a simulation device provided in another embodiment of this application.

[0094] Figure 8 The simulation device 800 shown can be any network node capable of performing power consumption analysis. The device 800 can be, for example, a computing device with computational capabilities. For instance, the device 800 can be a mobile terminal or a server. The device 800 may include a memory 810 and a processor 820. The memory 810 can be used to store executable code. The processor 820 can be used to execute the executable code stored in the memory 810 to implement the steps in the various methods described above. In some embodiments, the device 800 may further include a network interface 830 through which the processor 820 exchanges data with external devices.

[0095] This application also provides a computer-readable storage medium storing a computer program that, when executed, implements the steps of the aforementioned method.

[0096] This application also provides a computer program product, including computer program code, which, when run on a computer, causes the computer to perform the steps of the aforementioned method.

[0097] It should be understood that in the embodiments of this application, the processor can be a central processing unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0098] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0100] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0101] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0102] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can read or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs, DVDs) or semiconductor media (e.g., solid-state disks, SSDs), etc.

[0103] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A simulation method, characterized in that, include: A first analog circuit is created, which includes multiple sub-circuits. The circuit structure of each sub-circuit is the same as that of the circuit to be optimized, and each sub-circuit corresponds to multiple design parameters of the circuit to be optimized. The first analog circuit has a shared terminal of the multiple sub-circuits and multiple output terminals that correspond to each of the multiple sub-circuits. The first analog circuit is simulated to obtain multiple simulation results corresponding to the multiple sub-circuits; Based on the multiple simulation results, target design parameters are selected from the multiple design parameters as the optimization result of the circuit to be optimized; The shared terminal includes one or more of the following: a power supply voltage terminal, positive and negative input terminals, and a ground terminal; The creation of the first analog circuit includes: copying the circuit to be optimized multiple times to obtain the multiple sub-circuits; and splicing the multiple sub-circuits to obtain the first analog circuit.

2. The method according to claim 1, characterized in that, The multiple design parameters each correspond to multiple individuals in the current population. The selection of target design parameters from the multiple design parameters based on the multiple simulation results includes: Individual fitness evaluation is performed on the multiple simulation results to obtain the evaluation results corresponding to the multiple individuals; Based on the evaluation results corresponding to the multiple individuals, the target design parameter is selected from the multiple design parameters.

3. The method according to claim 1, characterized in that, The simulation of the first analog circuit includes: Write the plurality of design parameters into the circuit netlist of the first analog circuit; The first analog circuit is simulated once using the SPICE simulator to obtain the multiple simulation results.

4. A simulation device, characterized in that, include: A creation unit is used to create a first analog circuit. The first analog circuit includes multiple sub-circuits. The circuit structure of each of the multiple sub-circuits is the same as that of the circuit to be optimized. Each of the multiple sub-circuits corresponds to a multiple design parameter of the circuit to be optimized. The first analog circuit has a shared terminal of the multiple sub-circuits and multiple output terminals that correspond to each of the multiple sub-circuits. The simulation unit is used to simulate the first analog circuit and obtain multiple simulation results corresponding to the multiple sub-circuits. The determining unit is used to select target design parameters from the multiple design parameters based on the multiple simulation results, as the optimization result of the circuit to be optimized; The shared terminal includes one or more of the following: a power supply voltage terminal, positive and negative input terminals, and a ground terminal; The creation unit is also used to copy the circuit to be optimized multiple times to obtain the multiple sub-circuits, and to splice the multiple sub-circuits to obtain the first analog circuit.

5. A simulation apparatus comprising a memory and a processor, the memory storing executable code, the processor being configured to execute the executable code to implement the method of any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the method as claimed in any one of claims 1-3.

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