Pixel driving circuit and driving method thereof, display panel

Abstract

This application provides a pixel driving circuit and its driving method, as well as a display panel. The circuit includes a light-emitting module, a pulse amplitude modulation module, and a pulse width modulation module. The pulse amplitude modulation module includes a driving transistor, one end of which is connected to the light-emitting module. The pulse width modulation module is connected to the pulse amplitude modulation module and includes a fourth transistor. The gate of the fourth transistor is used to receive an input driving signal during the light-emitting phase of each frame driving cycle. The pulse width modulation module controls the light-emitting duration of the light-emitting module according to the driving signal via the driving transistor. The voltage value of the driving signal increases in a stepwise manner until the fourth transistor turns on. This application improves the uniformity of panel light emission and the stability of the driving architecture.

Description

Technical Field

[0001] This application generally relates to the field of communication technology, and specifically to a pixel driving circuit and its driving method, and a display panel. Background Technology

[0002] Currently, there are two common pixel driving methods for display panels: Pulse Amplitude Modulation (PAM) driving and Pulse Width Modulation (PWM) driving. PAM driving achieves different brightness levels by controlling the driving signal magnitude of the light-emitting module in each pixel unit. However, PAM driving suffers from color drift at low grayscale levels, affecting the display effect. PWM driving achieves different brightness levels by controlling the emission time of the light-emitting module in each pixel unit. However, PWM driving places higher demands on the gate driver chip (Gate IC).

[0003] To address this, combining the advantages of PWM and PAM driving methods, those skilled in the art have developed a hybrid driving circuit that integrates both. PWM driving is used for low grayscale levels, while PAM driving is used for high grayscale levels. In this hybrid driving circuit, the PWM module determines the on-time of the driving transistors, which in turn determines the emission time of the light-emitting module. When the on-times of multiple driving transistors in the display panel differ, the emission time of the light-emitting module is significantly affected, thus impacting the uniformity of the displayed image. Summary of the Invention

[0004] To address the above-mentioned or other problems, this application provides the following technical solutions.

[0005] In a first aspect, this application provides a pixel driving circuit, including:

[0006] Light-emitting module;

[0007] A pulse amplitude modulation module includes a driving transistor, one end of which is connected to the light-emitting module;

[0008] A pulse width modulation module is connected to the pulse amplitude modulation module. The pulse width modulation module includes a fourth transistor. The gate of the fourth transistor is used to receive an input driving signal during the light emission phase of each frame driving cycle. The pulse width modulation module controls the light emission duration of the light emission module through the driving transistor according to the driving signal.

[0009] The voltage value of the driving signal increases in a stepwise manner until the fourth transistor is turned on.

[0010] In some embodiments, the drive cycle further includes a write phase, which includes a first write period and a second write period; wherein...

[0011] During the first write operation, the pulse width modulation module receives a drive signal, and the level of the drive signal is a first preset voltage value.

[0012] During the second write operation, the pulse width modulation module is connected to a second preset voltage value, which is less than the first preset voltage value.

[0013] During the light emission stage, the driving signal received by the pulse width modulation module increases continuously in a stepwise manner from the second preset voltage value to the first preset voltage value.

[0014] In some embodiments, a sum is obtained based on the pulse width modulation voltage connected to the pulse width modulation module and the increment of the driving signal; a calculation result is obtained by calculating the difference between the sum and the reference voltage connected to the pulse amplitude modulation module; wherein,

[0015] When the calculation result does not reach the threshold voltage of the fourth transistor, the step-like increase in the voltage value of the driving signal is positively correlated with the drift amplitude of the threshold voltage of the fourth transistor.

[0016] When the calculation result reaches the threshold voltage of the fourth transistor, the step-like increment of the voltage value of the driving signal is equal to the increment when the calculation result reaches the threshold voltage.

[0017] In some embodiments, the pulse amplitude modulation module further includes: a first transistor, a first capacitor, and a third transistor;

[0018] The gate of the driving transistor is connected to a first node, one of the source and drain of the driving transistor is connected to a first supply voltage, and the other of the source and drain of the driving transistor is connected to a second node.

[0019] The gate of the first transistor is connected to a pulse amplitude modulation control signal line to receive a pulse amplitude modulation voltage. One of the source and drain of the first transistor is connected to a data signal line, and the other of the source and drain of the first transistor is connected to the first node.

[0020] The first capacitor is coupled between the first node and the second node;

[0021] The gate of the third transistor is connected to the pulse amplitude modulation external compensation control signal line, one of the source and drain of the third transistor is connected to the second node, and the other of the source and drain of the third transistor is connected to the reference signal line to access the reference voltage.

[0022] In some embodiments, the pulse width modulation module further includes a fifth transistor and a second capacitor;

[0023] The gate of the fourth transistor is connected to the third node, one of the source and drain of the fourth transistor is connected to the first node, and the other of the source and drain of the fourth transistor is connected to the reference signal line to access the reference voltage.

[0024] The gate of the fifth transistor is connected to the pulse width modulation control signal line to receive the pulse width modulation voltage. One of the source and drain of the fifth transistor is connected to the data signal line, and the other of the source and drain of the fifth transistor is connected to the third node.

[0025] The second capacitor is coupled between the sweep frequency signal line and the third node to access the drive signal.

[0026] In some embodiments, when the reference signal line controls the driving transistor to turn off via the fourth transistor, the threshold voltage of the fourth transistor is obtained by detecting the potential of the third node.

[0027] In some embodiments, if the fourth transistor is an N-type thin-film transistor, when the driving signal changes from a first preset voltage value to a second preset voltage value, the change in the driving signal from the first preset voltage value to the second preset voltage value is coupled to the third node through the second capacitor, so that the fourth transistor changes from the on state to the off state.

[0028] Secondly, this application also provides a display panel including a plurality of sub-pixel units arranged in an array, each of the sub-pixel units including a pixel driving circuit as described in the first aspect.

[0029] Thirdly, this application also provides a driving method applied to the pixel driving circuit described in the first aspect, the method comprising the steps of:

[0030] A drive signal is input to the gate of the fourth transistor during the light-emitting phase of each frame drive cycle.

[0031] The duration of light emission of the light-emitting module is controlled by the driving transistor according to the driving signal;

[0032] The voltage value of the driving signal increases in a stepwise manner until the fourth transistor is turned on.

[0033] In some embodiments, the stepwise increase in the voltage value of the driving signal includes:

[0034] The sum is obtained by combining the pulse width modulation voltage connected to the pulse width modulation module and the incremental magnitude of the driving signal. The difference between the sum and the reference voltage connected to the pulse amplitude modulation module is then calculated to obtain the final result.

[0035] When the calculation result does not reach the threshold voltage of the fourth transistor, the step-like increase in the voltage value of the driving signal is positively correlated with the drift amplitude of the threshold voltage of the fourth transistor.

[0036] When the calculation result reaches the threshold voltage of the fourth transistor, the step-wise increase in the voltage value of the driving signal is equal to the increase in the calculation result when it reaches the threshold voltage.

[0037] The beneficial effects of this application are as follows: The pixel driving circuit and driving method of this application, and the display panel, compensate the threshold voltage of the fourth transistor by connecting a driving signal during the light-emitting stage of each frame driving cycle. The voltage value of the driving signal increases in a stepwise manner until the fourth transistor is turned on. The stepwise increase of the voltage value of the driving signal can ensure that the threshold voltage of the fourth transistor fluctuates within a certain range, so that the light-emitting time of the light-emitting module remains stable, thereby achieving the stability of the panel display brightness. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of this application, the drawings used in the description of the various embodiments made according to this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the pixel driving circuit provided according to an embodiment of this application.

[0040] Figure 2 This is a timing diagram of the pixel driving circuit provided according to an embodiment of this application.

[0041] Figure 3 This is a timing diagram of the driving signals provided according to an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0043] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0046] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0047] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0048] The display panel in this application embodiment can be used in mobile phones, tablets, desktop computers, laptops, e-readers, handheld computers, electronic display screens, laptops, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0049] In the circuit structure provided by the embodiments of this application, nodes such as the first node q and the second node s do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0050] This application provides a pixel driving circuit, the operation of which includes a writing stage and a light-emitting stage, such as... Figure 1 As shown, the pixel driving circuit includes:

[0051] Light-emitting module 10;

[0052] The pulse amplitude modulation module 20 includes a driving transistor T2, one end of which is connected to the light-emitting module 10;

[0053] A pulse width modulation module 30 is connected to the pulse amplitude modulation module 20. The pulse width modulation module 30 includes a fourth transistor T4. The gate of the fourth transistor T4 is used to receive an input driving signal Sweep during the light emission phase of each frame driving cycle. The pulse width modulation module 30 controls the light emission duration of the light emission module 10 according to the driving signal Sweep via the driving transistor T2.

[0054] The voltage value of the drive signal Sweep increases in a stepwise manner until the fourth transistor T4 is turned on.

[0055] Specifically, since the switching on and off of a transistor is controlled by the signal connected to the gate, when a transistor is in a prolonged operating state, the gate bias voltage can cause instability in the transistor's electrical characteristics, such as threshold voltage drift. This instability in the threshold voltage increases on-resistance, affects junction temperature, and ultimately leads to device failure.

[0056] like Figure 1 As shown, the light-emitting module 10 may include at least one light-emitting device, wherein the light-emitting device D1 may be one of an organic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, or a mini light-emitting diode. Figure 1 The number of light-emitting devices included in the illustrated light-emitting module 10 is merely an example; a greater number of light-emitting devices may be included. Figure 1 As shown, the driving transistor T2 can drive the light-emitting module 10 in the sub-pixel unit of the display panel to emit light, and the pulse amplitude modulation module 20 is connected to the driving transistor T2 and the pulse width modulation module 30 respectively.

[0057] The pulse amplitude modulation module 20 controls the pulse amplitude of the driving signal Sweep flowing through the light-emitting module 10 via the driving transistor T2, and the pulse width modulation module 30 controls the pulse width of the driving signal Sweep flowing through the light-emitting module 10 via the driving transistor T2. That is, this pixel driving circuit improves low grayscale color shift by using pulse width modulation (PWM) via the pulse width modulation module 30 at low grayscale levels, and ensures high brightness by using pulse amplitude modulation (PAM) via the pulse width modulation module 30 at high grayscale levels.

[0058] The pulse width modulation module 30 may include a fourth transistor T4. The gate of the fourth transistor T4 is connected to the drive signal Sweep during the light emission phase of each frame driving cycle. The drive signal Sweep is continuous, and the voltage value of the drive signal Sweep increases or rises in a stepwise manner. The increase or rise of the voltage value of the drive signal Sweep continues until the fourth transistor T4 is turned on during the light emission phase. In this stepwise manner, the potential at the third node p connected to the gate of the fourth transistor T4 is gradually raised or raised, which allows the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4 connected to the third node p to fluctuate within a certain range, so that the light emission time of the light emission module 10 remains stable, thereby improving the uniformity of light emission and driving stability of the display panel.

[0059] Since the threshold voltage of the fourth transistor T4 drifts, causing fluctuations in the current output to the gate of the driving transistor T2 connected to the first node q, this application introduces a driving signal Sweep during the light-emitting phase of each frame driving cycle to progressively raise or increase the potential at the third node p connected to the gate of the fourth transistor T4. The voltage value of the driving signal Sweep increases in a stepwise manner to the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4, so that the threshold voltage Vth4 of the fourth transistor T4 fluctuates within a certain range. This keeps the driving current output to the light-emitting module 10 after the driving transistor T2 is turned on stable, thereby keeping the light-emitting time of the light-emitting module 10 stable and achieving stability of the panel display brightness.

[0060] In some embodiments, the drive cycle further includes a write phase, which includes a first write period and a second write period; wherein...

[0061] During the first write operation, the pulse width modulation module 30 receives the drive signal Sweep, and the level of the drive signal is a first preset voltage value.

[0062] During the second write operation, the pulse width modulation module 30 is connected to a second preset voltage value, which is less than the first preset voltage value.

[0063] During the light emission stage, the drive signal Sweep received by the pulse width modulation module 30 increases continuously in a stepwise manner from the second preset voltage value to the first preset voltage value.

[0064] Specifically, such as Figure 2 and Figure 3 As shown, the driving cycle of the pixel driving circuit includes a writing phase and a light-emitting phase. The writing phase includes a first writing period and a second writing period. The first writing period is used to write the pulse width modulation voltage Vpwm through the data signal line Data, and the second writing period is used to write the pulse width modulation voltage Vpam through the data signal line Data. In the first writing period, the pulse width modulation module 30 receives a driving signal Sweep with a voltage value of a first preset voltage value, causing the fourth transistor T4 to switch to the on state or the conducting state. In the second writing period, the pulse width modulation module 30 receives a driving signal Sweep with a voltage value of a second preset voltage value (which can be 0 or less than the threshold voltage of the fourth transistor), causing the fourth transistor T4 to switch to the off state or the cutoff state. Then, in the light-emitting phase, the driving signal Sweep received by the pulse width modulation module 30 increases continuously in a stepwise manner from the second preset voltage value to the first preset voltage value, causing the fourth transistor T4 to switch to the on state or the conducting state.

[0065] This application utilizes a pulse width modulation module 30 that receives a drive signal Sweep at the first preset voltage value during the first writing period and a drive signal Sweep at the second preset voltage value during the second writing period. During the light-emitting phase, the drive signal Sweep supplied to the pulse width modulation module 30 increases continuously in a stepwise manner from the second preset voltage value to the first preset voltage value. This controls the off or on state of the fourth transistor T4 in the pulse width modulation module 30, thereby progressively raising or lowering the potential at the third node p connected to the gate of the fourth transistor T4. This allows the voltage of the third node p to fluctuate within a certain range, ensuring a stable light-emitting time for the light-emitting module 10, and thus achieving stable panel display brightness.

[0066] In some embodiments, a sum is obtained based on the pulse width modulation voltage Vpwm input to the pulse width modulation module 30 and the increment ΔVsweep of the drive signal Sweep. The sum is then used in conjunction with the reference voltage V input to the pulse amplitude modulation module 20. REF The difference is calculated to obtain the result; where,

[0067] When the calculation result does not reach the threshold voltage Vth4 of the fourth transistor T4, the step-like increase in the voltage value of the drive signal Sweep, ΔVsweep, is positively correlated with the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4.

[0068] When the calculation result reaches the threshold voltage Vth4 of the fourth transistor T4, the step-like increase in the voltage value of the drive signal Sweep, ΔVsweep, is equal to the increase when the calculation result reaches the threshold voltage Vth4.

[0069] Specifically, by changing the timing of the driving signal Sweep, the voltage value of the driving signal Sweep is continuously increased in a step-by-step manner during the light-emitting stage. The step-by-step increase in the voltage value of the driving signal Sweep is set considering the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4 in the display panel. For example, assuming the drift amplitude of the threshold voltage Vth4 of all fourth transistors T4 in the display panel is < ±0.5V, the increase amplitude or the step-by-step increase amplitude of the driving signal Sweep voltage value can be set between 0.1V and 0.5V. This application allows the voltage of the third node to fluctuate within a certain range by setting the increase amplitude or the step-by-step increase amplitude of the driving signal Sweep voltage value based on the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4, thus keeping the light-emitting time of the light-emitting module 10 stable and improving the uniformity of light emission and driving stability of the display panel.

[0070] The calculation result obtained by substituting the pulse width modulation voltage Vpwm connected to the pulse width modulation module 30, the increment ΔVsweep of the drive signal Sweep, and the pulse amplitude modulation module 20 into the following formula (1) is as follows:

[0071] (Vpwm+△Vsweep)-V REF (1)

[0072] If the calculated result does not reach the threshold voltage Vth4 of the fourth transistor T4, i.e. (Vpwm + ΔVsweep) - V REF When ≤Vth4, for example, as Figure 3 As shown, before time t1, the step-like increase in the voltage value of the driving signal Sweep, ΔVsweep, is positively correlated with the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4. At this time, the step-like increase in the voltage value of two adjacent driving signals Sweep in chronological order can be the same or different. The larger the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4, the larger the step-like increase in the voltage value of the driving signal Sweep, ΔVsweep. This results in fewer steps in the driving signal Sweep, leading to coarser grayscale division and faster panel luminous compensation efficiency. Conversely, the smaller the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4, the smaller the step-like increase in the voltage value of the driving signal Sweep, ΔVsweep. Thus, the smaller the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4, the smaller the increment ΔVsweep of the drive signal Sweep becomes. In fact, the number of steps in the drive signal Sweep is greater, resulting in finer grayscale division, better panel light emission uniformity, and higher light emission stability.

[0073] If the calculation result reaches the threshold voltage Vth4 of the fourth transistor T4, i.e. (Vpwm + ΔVsweep) - V REF When >Vth4, for example, as Figure 3 As shown, after time t1, the step-like increase in the voltage value of the drive signal Sweep, ΔVsweep, is a fixed value. That is, the step-like increase in the voltage value of the drive signal Sweep, ΔVsweep, is a stable and unchanging value. At this time, the voltage values ​​of two adjacent drive signals Sweep, in chronological order, have the same step-like increase. In other words, the voltage value of the drive signal Sweep increases in a continuous step-like arithmetic progression (i.e., equal value) until it reaches the first preset voltage value and then the fourth transistor T4 is turned on. This compensation method is simple and easy to control. Furthermore, the step-like equal value increase reduces the drift of the threshold voltage Vth4 of the fourth transistor T4 and allows the voltage of the third node p to fluctuate within a certain range, keeping the light-emitting time of the light-emitting module 10 stable, thereby improving the uniformity of light emission and the driving stability of the display panel.

[0074] In some embodiments, the pulse amplitude modulation module 20 further includes: a first transistor T1, a first capacitor C1, and a third transistor T3;

[0075] The gate of the driving transistor T2 is connected to the first node q, one of the source and drain of the driving transistor T2 is connected to the first supply voltage VDD, and the other of the source and drain of the driving transistor T2 is connected to the second node s.

[0076] The gate of the first transistor T1 is connected to the pulse amplitude modulation control signal line SPAM to receive the pulse width modulation voltage Vpam. One of the source and drain of the first transistor T1 is connected to the data signal line Data, and the other of the source and drain of the first transistor T1 is connected to the first node q.

[0077] The first capacitor C1 is coupled between the first node q and the second node s;

[0078] The gate of the third transistor T3 is connected to the pulse amplitude modulation external compensation control signal line Sense. One of the source and drain of the third transistor T3 is connected to the second node s, and the other of the source and drain of the third transistor T3 is connected to the reference signal line Vref to access the reference voltage VREF.

[0079] In some embodiments, when the reference signal line Vref controls the drive transistor T2 to turn off via the fourth transistor T4, the threshold voltage Vth4 of the fourth transistor T4 is obtained by detecting the potential of the third node p.

[0080] That is, the gate-source potential difference of the fourth transistor T4 is the potential difference between the third node p and the reference signal line Vref. When the reference signal line Vref is a known potential, the threshold voltage Vth4 of the fourth transistor T4 can be obtained through the potential of the third node p.

[0081] In some embodiments, the pulse width modulation module 30 further includes a fifth transistor T5 and a second capacitor C2;

[0082] The gate of the fourth transistor T4 is connected to the third node p, one of the source and drain of the fourth transistor T4 is connected to the first node q, and the other of the source and drain of the fourth transistor T4 is connected to the reference signal line Vref to access the reference voltage VREF.

[0083] The gate of the fifth transistor T5 is connected to the pulse width modulation control signal line SPWM, one of the source and drain of the fifth transistor T5 is connected to the data signal line, and the other of the source and drain of the fifth transistor T5 is connected to the third node p.

[0084] The second capacitor C2 is coupled between the sweep frequency signal line Sweep and the third node p to connect to the drive signal Sweep.

[0085] It should be noted that if the fourth transistor T4 is an N-type thin-film transistor, the voltage difference between the pulse width modulation voltage Vpwm and the reference voltage VREF is greater than the threshold voltage Vth4 of the fourth transistor T4. The sweep signal line Sweep increases the potential of the third node p through the second capacitor C2 until the fourth transistor T4 turns on, thereby pulling down the potential of the first node q through the reference signal line Vref.

[0086] Specifically, Pulse Width Modulation (PWM) is based on Pulse Amplitude Modulation (PAM). The initial potential of the third node p is set to the pulse width modulation voltage Vpwm via the data signal line Data. Then, when the drive signal Sweep changes from a first preset voltage value to a second preset voltage value, the voltage change of the drive signal Sweep is coupled to the third node p via the second capacitor C2. This causes the potential of the third node p to change from the pulse width modulation voltage Vpwm to the sum of the difference between the second and first preset voltage values ​​and the pulse width modulation voltage Vpwm. Afterward, as the voltage value of the drive signal Sweep increases in a stepwise manner... The voltage fluctuation of the drive signal Sweep is coupled to the third node p through the second capacitor C2, causing the potential of the third node p to gradually rise, thereby turning on the fourth transistor T4. Then, through the reference signal line Vref, the first node q is pulled down through the fourth transistor T4 to turn off the drive transistor T2 connected to the light-emitting element D1. Different pulse width modulation voltages Vpwm will cause the fourth transistor T4 to be turned on for different times, thus causing the first node q to be pulled down for different times, thereby adjusting the duration of the drive signal Sweep flowing through the light-emitting element D1, that is, adjusting the pulse width of the drive signal Sweep flowing through the light-emitting element D1.

[0087] In some embodiments, if the fourth transistor T4 is an N-type thin-film transistor, the voltage difference between the pulse width modulation voltage Vpwm and the reference voltage VREF is greater than the threshold voltage Vth4 of the fourth transistor T4, so that when the initial potential of the third node p is set to the pulse width modulation voltage Vpwm, the fourth transistor T4 is initially in the on state. When the drive signal Sweep changes from the first preset voltage value to the second preset voltage value, the voltage change of the drive signal Sweep will be coupled to the third node p through the second capacitor C2, so that the potential of the third node p changes from the pulse width modulation voltage Vpwm to the sum of the difference between the second preset voltage value and the first preset voltage value and the pulse width modulation voltage Vpwm, thereby turning off the fourth transistor T4. If the fourth transistor T4 is always in the on state, the first node q is always in the pull-down state, the drive transistor T2 is always in the off state, the light-emitting element D1 cannot emit light, and the light-emitting time of the light-emitting element D1 cannot be adjusted. Therefore, when the fourth transistor T4 is an N-type thin-film transistor, the change in the driving signal Sweep from the first preset voltage value to the second preset voltage value can be used to couple the potential of the third node p through the second capacitor C2, thereby causing the fourth transistor T4 to change from the on state to the off state.

[0088] Based on the above embodiments, combined with Figure 1 , Figure 2 and Figure 3As shown, if the pixel driving circuit uses N-type thin-film transistors, the detailed workflow of the pixel driving circuit includes: Vpwm data writing stage (i.e., the first writing period), Vpamdata writing stage (i.e., the second writing period), and light emission control stage (i.e., the light emission stage). Here, Vth4 is the threshold voltage of the fourth transistor T4.

[0089] During the Vpwm data write phase (i.e., the first write period): the voltage value of the Data signal is Vpwm. SPWM is initially high and then drops to low. Sweep is high, causing T5 to turn on. The data signal line Data writes Vpwm to the third node p through T5. At this time, the voltage of the third node p, Vp = Vpwm, causing T4 to turn on.

[0090] During the Vpam data write phase (i.e., the second write period): The voltage value of the Data signal is Vpam, and both SPWM and Sweep are low, causing T5 to be off. SPAM is first high and then drops to low, causing T1 to be on. The Data signal line writes Vpam to the first node q through T1. At this time, the voltage level of the first node q, Vq, equals Vpam. Sense is first high and then drops to low, and Vref is low, causing T3 to be on. The reference signal line Vref is written to the second node s through T3. At this time, the voltage of the second node s, Vs, equals Vref. The drive signal Sweep changes from a first preset voltage value to a second preset voltage value, causing T4 to be off.

[0091] During the light-emitting control phase (i.e., the light-emitting phase): The voltage value of the Data signal is low (e.g., 0V) and SPAM is low, causing T1 to turn off. Sense is low and Vref is low, causing T3 to turn off. VDD changes from low to high (e.g., 15V), causing T2 to turn on. The second node s is charged to the Vs potential. The gate voltage of T2 is Vg = Vpam + (Vs - Vref), and the source-gate voltage of T2 is Vgs = Vpam - Vref, causing the light-emitting device D1 to start emitting light. Subsequently, the Sweep signal gradually increases in a stepwise manner, gradually raising the potential of the third node p through the second capacitor C2 until (Vpwm + ΔVsweep) - Vref > Vth4, at which point T4 turns on. Vref pulls the potential of the first node q low, causing T2 to turn off and stop emitting light. Because the Sweep signal gradually increases in a stepwise manner, ΔVsweep remains a constant value, thus keeping the light-emitting time of the light-emitting device D1 constant.

[0092] This application's pixel driving circuit uses pulse width modulation (PWM) to improve low grayscale color shift and pulse amplitude modulation (PWM) to ensure high brightness at high grayscale. It also compensates for the threshold voltage Vth4 of the fourth transistor T4 in the PWM module 30, thereby achieving stable panel display brightness. This avoids the instability of light emission caused by the drift of the threshold voltage Vth4 of the fourth transistor T4 without compensation. By connecting a driving signal Sweep during the light emission phase of each frame driving cycle, the potential at the third node p connected to the gate of the fourth transistor T4 is progressively raised or increased. The voltage value of the driving signal Sweep increases continuously in a stepwise manner to a first preset voltage value, which is equal to the threshold voltage of the fourth transistor. This allows the threshold voltage Vth4 of the fourth transistor T4 to fluctuate within a certain range, which in turn allows the voltage of the third node p to fluctuate within a certain range, keeping the light emission time of the light-emitting module 10 stable, thus achieving stable panel display brightness.

[0093] This application also provides a display panel including a plurality of sub-pixel units arranged in an array, each of the sub-pixel units including the pixel driving circuit described in the above embodiments.

[0094] This application also provides a driving method, applied to the above-mentioned... Figures 1 to 3 The method for the pixel driving circuit described in the corresponding embodiment includes the following steps:

[0095] During the light-emitting phase of each frame driving cycle, a driving signal Sweep is input to the gate of the fourth transistor T4.

[0096] The duration of light emission of the light-emitting module 10 is controlled by the driving transistor T2 according to the driving signal Sweep.

[0097] The voltage value of the drive signal Sweep increases in a stepwise manner until the fourth transistor T4 is turned on.

[0098] In some embodiments, the stepwise increase in the voltage value of the drive signal Sweep includes:

[0099] The sum is obtained based on the pulse width modulation voltage connected to the pulse width modulation module 30 and the incremental magnitude ΔVsweep of the drive signal Sweep. The difference is then calculated based on the sum and the reference voltage connected to the pulse amplitude modulation module to obtain the final result.

[0100] When the calculation result does not reach the threshold voltage Vth4 of the fourth transistor T4, the step-like increase in the voltage value of the drive signal Sweep, ΔVsweep, is positively correlated with the drift amplitude of the threshold voltage Vth4 of the fourth transistor T4.

[0101] When the calculation result reaches the threshold voltage Vth4 of the fourth transistor T4, the step-like increment ΔVsweep of the voltage value of the drive signal Sweep is equal to the increment ΔVsweep when the calculation result reaches the threshold voltage Vth4.

[0102] It should be noted that the channel material of these transistors is low-temperature polycrystalline silicon, which not only improves the dynamic performance of the pixel circuit but also simplifies the fabrication process, structure, and cost. While low-temperature polycrystalline silicon thin-film transistors are a preferred option, they are not the only option. At least one of the aforementioned transistors may also be an indium gallium zinc oxide thin-film transistor.

[0103] The pixel driving circuit and its driving method, as well as the display panel provided in the embodiments of this application, have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A pixel driving circuit, characterized in that, include: Light-emitting module; A pulse amplitude modulation module includes a driving transistor, one end of which is connected to the light-emitting module; A pulse width modulation module is connected to the pulse amplitude modulation module. The pulse width modulation module includes a fourth transistor. The gate of the fourth transistor is used to receive an input driving signal during the light emission phase of each frame driving cycle. The pulse width modulation module controls the light emission duration of the light emission module through the driving transistor according to the driving signal. The voltage value of the driving signal increases in a stepwise manner until the fourth transistor is turned on; The sum is obtained based on the pulse width modulation voltage connected to the pulse width modulation module and the increment of the driving signal. The difference between the sum and the reference voltage connected to the pulse amplitude modulation module is then calculated to obtain the final result. When the calculation result does not reach the threshold voltage of the fourth transistor, the step-like increase in the voltage value of the driving signal is positively correlated with the drift amplitude of the threshold voltage of the fourth transistor. When the calculation result reaches the threshold voltage of the fourth transistor, the step-like increment of the voltage value of the driving signal is equal to the increment when the calculation result reaches the threshold voltage.

2. The pixel driving circuit according to claim 1, characterized in that, The drive cycle also includes a write phase, which comprises a first write period and a second write period; wherein... During the first write operation, the pulse width modulation module receives a drive signal, and the level of the drive signal is a first preset voltage value. During the second write operation, the pulse width modulation module is connected to a second preset voltage value, which is less than the first preset voltage value. During the light emission stage, the driving signal received by the pulse width modulation module increases continuously in a stepwise manner from the second preset voltage value to the first preset voltage value.

3. The pixel driving circuit according to claim 1, characterized in that, The pulse amplitude modulation module further includes: a first transistor, a first capacitor, and a third transistor; The gate of the driving transistor is connected to a first node, one of the source and drain of the driving transistor is connected to a first supply voltage, and the other of the source and drain of the driving transistor is connected to a second node. The gate of the first transistor is connected to a pulse amplitude modulation control signal line to receive a pulse amplitude modulation voltage. One of the source and drain of the first transistor is connected to a data signal line, and the other of the source and drain of the first transistor is connected to the first node. The first capacitor is coupled between the first node and the second node; The gate of the third transistor is connected to the pulse amplitude modulation external compensation control signal line, one of the source and drain of the third transistor is connected to the second node, and the other of the source and drain of the third transistor is connected to the reference signal line to access the reference voltage.

4. The pixel driving circuit according to claim 3, characterized in that, The pulse width modulation module also includes a fifth transistor and a second capacitor; The gate of the fourth transistor is connected to the third node, one of the source and drain of the fourth transistor is connected to the first node, and the other of the source and drain of the fourth transistor is connected to the reference signal line to access the reference voltage. The gate of the fifth transistor is connected to the pulse width modulation control signal line to receive the pulse width modulation voltage. One of the source and drain of the fifth transistor is connected to the data signal line, and the other of the source and drain of the fifth transistor is connected to the third node. The second capacitor is coupled between the sweep frequency signal line and the third node to access the drive signal.

5. The pixel driving circuit according to claim 4, characterized in that, When the reference signal line controls the driving transistor to turn off via the fourth transistor, the threshold voltage of the fourth transistor is obtained by detecting the potential of the third node.

6. The pixel driving circuit according to claim 5, characterized in that, If the fourth transistor is an N-type thin-film transistor, when the driving signal changes from the first preset voltage value to the second preset voltage value, the change in the driving signal from the first preset voltage value to the second preset voltage value is coupled to the third node through the second capacitor, so that the fourth transistor changes from the on state to the off state.

7. A display panel, characterized in that, It includes a plurality of sub-pixel units arranged in an array, each of the sub-pixel units including a pixel driving circuit as described in any one of claims 1 to 6.

8. A driving method, characterized in that, Applied to the pixel driving circuit as described in any one of claims 1-6, the method includes the steps of: A drive signal is input to the gate of the fourth transistor during the light-emitting phase of each frame drive cycle. The duration of light emission of the light-emitting module is controlled by the driving transistor according to the driving signal; The voltage value of the driving signal increases in a stepwise manner until the fourth transistor is turned on.

9. The driving method according to claim 8, characterized in that, The stepwise increase in the voltage value of the driving signal includes: The sum is obtained by combining the pulse width modulation voltage connected to the pulse width modulation module and the incremental magnitude of the driving signal. The difference between the sum and the reference voltage connected to the pulse amplitude modulation module is then calculated to obtain the final result. When the calculation result does not reach the threshold voltage of the fourth transistor, the step-like increase in the voltage value of the driving signal is positively correlated with the drift amplitude of the threshold voltage of the fourth transistor. When the calculation result reaches the threshold voltage of the fourth transistor, the step-wise increase in the voltage value of the driving signal is equal to the increase in the calculation result when it reaches the threshold voltage.

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