Display device
By employing alternating first and second transistors in the display device and adjusting the clock signal using a detection and compensation module, the problem of uneven brightness caused by inconsistent transistor electrical characteristics in the Demux module was solved, thus achieving uniform brightness of the displayed image.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGZHOU CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
- Filing Date
- 2023-08-25
- Publication Date
- 2026-06-23
Smart Images
Figure CN117475840B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology
[0002] To reduce the number of source drivers in a display device while still achieving large-size and high-resolution displays, a demultiplexing module is proposed between the source drivers and the data lines. The demux module time-division multiplexes the data signal output from one source driver to multiple data lines, thereby reducing the number of source drivers. The inputs of the demux module are electrically connected 1:1 to the outputs of the source drivers via signal lines, and the outputs of the demux module are electrically connected to the sub-pixels of the display panel via data lines. The ratio of the number of inputs to outputs of the demux module is 1:X, where X is an integer greater than or equal to 2.
[0003] In the Demux module of related technologies, the demultiplexing unit, electrically connected to the data line, operates alternately within the display cycle using a dual-transistor architecture to prevent the aging of a single transistor from affecting the sub-pixel data writing signal. However, due to limitations in current transistor manufacturing processes, the electrical characteristics of the two transistors are not completely identical, resulting in different conduction levels during their respective conduction periods. This leads to inconsistent charging times for sub-pixels on the same data line, causing sub-pixels charging when one transistor is on to be brighter, while those charging when the other transistor is on to be dimmer, resulting in uneven brightness in the displayed image. Summary of the Invention
[0004] This application provides a display device that solves the problem of inconsistent brightness in the displayed image.
[0005] This application provides a display device, including:
[0006] The display panel includes multiple data lines, multiple scan lines, and multiple sub-pixels, wherein one of the sub-pixels is electrically connected to one of the data lines and one of the scan lines;
[0007] At least one demultiplexing module is provided, the demultiplexing module comprising multiple demultiplexing units. A first transistor of each demultiplexing unit is electrically connected to a first clock control terminal, and a second transistor of each demultiplexing unit is electrically connected to a second clock control terminal. The source of the first transistor is electrically connected to the multiplexed data signal input terminal of the display device, and the drain of the first transistor is electrically connected to a data line. The source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor. The first transistor is used to provide the data signal from the multiplexed data signal input terminal to the data line under the control of a first clock signal from the first clock control terminal, and the second transistor is used to provide the data signal to the data line under the control of a second clock signal from the second clock control terminal.
[0008] A detection module is electrically connected to a first sub-pixel under test that receives the data signal based on the conduction of the first transistor, and the detection module is also electrically connected to a second sub-pixel under test that receives the data signal based on the conduction of the second transistor. The detection module is used to detect the first pixel voltage of the first sub-pixel under test and the second pixel voltage of the second sub-pixel under test, and output a feedback signal based on the first pixel voltage and the second pixel voltage, wherein the first sub-pixel under test and the second sub-pixel under test are two sub-pixels electrically connected to the same data line.
[0009] A compensation module, which is electrically connected to the detection module, is used to output a compensation signal based on the feedback signal;
[0010] A clock signal control module is electrically connected to the first clock control terminal, the second clock control terminal, and the compensation module. The clock signal control module is used to compensate the voltage value of the first clock signal or the voltage value of the second clock signal based on the compensation signal.
[0011] In the display device provided in this application, the display period of one frame of the image displayed by the display panel includes at least one first scan period and at least one second scan period, and the first scan period and the second scan period alternate.
[0012] The first transistor is used to output the data signal to the first sub-pixel under test after receiving the first clock signal in the first scan cycle, and the second transistor is used to output the data signal to the second sub-pixel under test after receiving the second clock signal in the second scan cycle.
[0013] The detection module is electrically connected to the first sub-pixel under test that receives the data signal in the first scan cycle, and the detection module is electrically connected to the second sub-pixel under test that receives the data signal in the second scan cycle.
[0014] In the display device provided in this application, the first scanning cycle includes m first sub-scanning cycles, and the second scanning cycle includes m second sub-scanning cycles;
[0015] The detection module is electrically connected to the first sub-pixel under test that receives the data signal in the nth first sub-scan cycle, and the detection module is electrically connected to the second sub-pixel under test that receives the data signal in the nth second sub-scan cycle.
[0016] Where m and n are integers, n is greater than or equal to 1, and m is greater than or equal to n.
[0017] In the display device provided in this application, the first transistor and the second transistor are both N-type transistors, or the first transistor and the second transistor are both P-type transistors.
[0018] In the display device provided in this application, the compensation module is further configured to determine whether the current image displayed on the display panel is a pure grayscale image, and when the current image is the pure grayscale image, output the compensation signal to the clock signal control module.
[0019] In the display device provided in this application, the compensation module includes a grayscale acquisition unit, a grayscale judgment unit, a sub-pixel quantity judgment unit, and a processing unit;
[0020] The grayscale acquisition unit is used to acquire the first grayscale of the sub-pixel in the current image;
[0021] The grayscale determination unit is used to calculate the first number of sub-pixels whose first grayscale is greater than a preset grayscale.
[0022] The sub-pixel quantity determination unit is used to compare the size of the first quantity and the preset quantity, and output a compensation control signal based on the comparison result that the first quantity is greater than or equal to the preset quantity;
[0023] The processing unit is used to output the compensation signal based on the compensation control signal and the feedback signal.
[0024] In the display device provided in this application, the detection module includes a first sampling unit, a second sampling unit, and a comparison unit;
[0025] The first sampling unit is electrically connected to the first sub-pixel under test, and the first sampling unit is used to generate a first sampling signal based on the voltage of the first pixel;
[0026] The second sampling unit is electrically connected to the second sub-pixel under test, and the second sampling unit is used to generate a second sampling signal based on the voltage of the second pixel;
[0027] The first input terminal of the comparison unit is electrically connected to the first sampling unit, the second input terminal of the comparison unit is electrically connected to the second sampling unit, and the output terminal of the comparison unit is electrically connected to the compensation module. The comparison unit is used to output the feedback signal based on the first sampling signal and the second sampling signal.
[0028] In the display device provided in this application, the compensation module is used to output a first compensation signal based on the feedback signal indicating that the voltage value of the first sampled signal is greater than the voltage value of the second sampled signal;
[0029] Alternatively, the compensation module may output a second compensation signal based on the feedback signal indicating that the voltage value of the first sampled signal is less than the voltage value of the second sampled signal.
[0030] In the display device provided in this application, the clock signal control module is used to compensate the voltage value of the second clock signal based on the first compensation signal;
[0031] Alternatively, the clock signal control module is used to compensate the voltage value of the second clock signal based on the second compensation signal.
[0032] In the display device provided in this application, the display device further includes a detection and control module, which is electrically connected to the power supply terminal, the compensation module, and the detection module. The detection and control module is used to output the power signal of the power supply terminal to the detection module based on the detection and control signal provided by the compensation module.
[0033] The display device provided in this application detects the pixel voltages of a first and a second sub-pixel under test, which are electrically connected to the same data line, through a detection module. A compensation module then provides a compensation signal to a clock signal control module based on the detection results. The clock signal control module compensates for the voltage value of either the first clock signal controlling the conduction of the first transistor or the voltage value of the second clock signal controlling the conduction of the second transistor. The first sub-pixel under test is the sub-pixel that writes data signals when the first transistor, electrically connected to the data line, is turned on. The second sub-pixel under test is the sub-pixel that writes data signals when the second transistor, electrically connected to the data line, is turned on. The first pixel voltage of the first sub-pixel under test is related to the conduction level of the first transistor, and the second pixel voltage of the second sub-pixel under test is related to the conduction level of the second transistor. Therefore, the brightness of the sub-pixels on the same data line is consistent, improving the uniformity of brightness in the displayed image. Attached Figure Description
[0034] Figure 1 This is a first block diagram of a display device provided in an embodiment of this application;
[0035] Figure 2 for Figure 1 A schematic diagram showing the connection between the central display panel and the demultiplexing module;
[0036] Figure 3 for Figure 2 A schematic diagram of a driving timing sequence for neutron pixels;
[0037] Figure 4 for Figure 1 Circuit diagram of the detection module;
[0038] Figure 5 for Figure 1 Block diagram of the compensation module;
[0039] Figure 6 for Figure 1 A schematic diagram showing the signal flow between the demultiplexing module, detection module, compensation module, and clock signal control module in the system;
[0040] Figure 7 This is a second block diagram of a display device provided in an embodiment of this application. Detailed Implementation
[0041] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. The described embodiments are only used to explain the ideas of the present invention and should not be regarded as limiting the scope of protection of this application.
[0042] like Figure 1As shown, the display device 100 provided in this application embodiment includes a display panel 10, a demultiplexing module 20, a detection module 30, a compensation module 40, and a clock signal control module 50.
[0043] like Figure 1 as well as Figure 2 As shown, the display panel 10 has a display area and a non-display area surrounding the display area. The display panel 10 includes multiple data lines SL, multiple scan lines GL, and multiple sub-pixels p. The multiple data lines SL extend along a first direction d1 and are spaced apart along a second direction d2. The multiple scan lines GL extend along the second direction d2 and are spaced apart along the first direction d1. The first direction d1 and the second direction d2 intersect.
[0044] Multiple sub-pixels p are disposed in the display area of the display panel 10, and the multiple sub-pixels p are arranged in an array. Each sub-pixel p is electrically connected to a data line SL, and each sub-pixel p is electrically connected to a scan line GL. Figure 3 In the diagram, the first direction d1 is the row direction of the sub-pixel array, and the second direction d2 is the column direction of the sub-pixel array. Multiple sub-pixels p include a red sub-pixel p1, a green sub-pixel p2, and a blue sub-pixel p3. Sub-pixels in the same column have the same color, any two adjacent sub-pixels in the same row have different colors, and any two adjacent sub-pixels in the same row have opposite voltage polarities.
[0045] The data line SL provides data signals to sub-pixel p. Sub-pixel p charges and emits light based on the received data signals. The brightness of sub-pixel p depends on both the voltage value of the data signal and the charging duration. The scan line GL provides scan signals to sub-pixel p to control the start and end points of the data signal writing process. In other words, the scan line GL controls the duration of the data signal writing process for sub-pixel p, which in turn controls the charging duration of sub-pixel p.
[0046] The demultiplexing module 20 is electrically connected to multiple data lines SL. The multiplexed data signal input terminal IN of the display device 100 receives data signals. The demultiplexing module 20 is electrically connected to the multiplexed data signal output terminal IN. The multiple clock control terminals of the demultiplexing module 20 receive corresponding clock control signals. Based on the received clock control signals, the clock control terminals of the demultiplexing module 20 provide the data signals from the multiplexed data signal input terminal to one or more data lines SL electrically connected to the demultiplexing module 20 in a time-division manner.
[0047] The demultiplexing module 20 includes multiple demultiplexing units. Each demultiplexing unit is electrically connected to a first clock control terminal CK1, a second clock control terminal CK2, and a data signal input terminal IN. Furthermore, each demultiplexing unit is electrically connected to only one data line SL, and each data line SL is electrically connected to only one demultiplexing unit. Under the control of the first clock signal from the first clock control terminal CK1 or the second clock signal from the second clock control terminal CK2, the demultiplexing unit outputs the data signal from the multiplexed data signal input terminal IN to the data line SL electrically connected to it.
[0048] like Figure 2 As shown, a demultiplexing module 20 includes three demultiplexing units, all of which are electrically connected to the multiplexed data signal input terminal IN. Figure 2 The demultiplexing circuit is shown to be a 1:3 demultiplexing architecture, that is, one multiplexed data signal input terminal IN provides data signals to three data lines SL in a time-division manner.
[0049] like Figure 2 As shown, a demultiplexing unit includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is electrically connected to a first clock control terminal CK1, the source of the first transistor T1 is connected to the multiplexed data signal input terminal IN, and the drain of the first transistor T1 is electrically connected to a data line SL. The first transistor T1 is in a conducting state or a cutoff state based on the first clock signal input to its gate. When in the conducting state, the first transistor T1 provides a data signal to the data line SL. The gate of the second transistor T2 is electrically connected to a second clock control terminal CK2, the source of the second transistor T2 is electrically connected to the source of the first transistor T1, and the drain of the second transistor T2 is electrically connected to the drain of the first transistor T1. The second transistor T2 is in a conducting state or a cutoff state based on the second clock signal input to its gate. When in the conducting state, the second transistor T2 provides a data signal to the data line SL.
[0050] The first transistor T1 and the second transistor T2 can both be N-type transistors. The gate of the first transistor T1 is in a conducting state when it receives a high-level clock signal, and in a cutoff state when it receives a low-level clock signal. The gate of the second transistor T2 is in a conducting state when it receives a high-level clock signal, and in a cutoff state when it receives a low-level clock signal. Similarly, the first transistor T1 and the second transistor T2 can both be P-type transistors. The gate of a P-type transistor is in a conducting state when it receives a low-level signal, and in a cutoff state when it receives a high-level signal. One of the first transistors T1 and the second transistor T2 can be an N-type transistor, and the other can be a P-type transistor.
[0051] Since the first transistor T1 and the second transistor T2 are both N-type transistors or both P-type transistors, the first transistor T1 and the second transistor T2 meet the same conditions for being in the on state, so as to detect and compensate the gate voltage of the transistor with weaker conduction, and reduce the sub-pixel brightness difference caused by the first transistor T1 and the second transistor T2.
[0052] Since the first clock control terminal CK1 and the second clock control terminal CK2 provide the first clock signal and the second clock signal to the demultiplexing unit at different time periods, the first transistor T1 and the second transistor T2 can be turned on at different time periods, thereby charging the sub-pixel p on the data line in turn through the first transistor T1 and the second transistor T2.
[0053] The detection module 30 is electrically connected to the first sub-pixel p01 under test, which receives a data signal based on the conduction of the first transistor T1. The detection module 30 is also electrically connected to the second sub-pixel p02 under test, which receives a data signal based on the conduction of the second transistor T2. The first sub-pixel p01 and the second sub-pixel p02 under test are two sub-pixels p electrically connected to the same data line SL. Since multiple scan lines GL are turned on row by row, multiple sub-pixels p on the same data line SL are charged by writing data signals one by one. Since a data line SL is electrically connected to a demultiplexing unit, any sub-pixel p on the same data line SL is written with the data signal provided by the multiplexed data signal input terminal IN under the control of the same demultiplexing unit.
[0054] like Figure 2 as well as Figure 3 As shown. Within one display period t of the image displayed on the display panel 10, one display period t includes at least one first scan period t1 and at least one second scan period t2, with the first scan period t1 and the second scan period t2 alternating.
[0055] The first transistor T1 is used to output a data signal to the first sub-pixel under test p01 after receiving the first clock signal in the first scan period t1. The second transistor T2 is used to output a data signal to the second sub-pixel under test p02 after receiving the second clock signal in the second scan period t2.
[0056] The detection module 30 is electrically connected to the first sub-pixel p01 under test that receives a data signal in the first scan period t1, and the detection module 30 is electrically connected to the second sub-pixel p02 under test that receives a data signal in the second scan period t2.
[0057] The display panel 10 specifically includes a scan lines GL. Within one frame display period t of the image displayed on the display panel 10, the first scan line GL_1 to the a-th scan line GL_a control the writing of data signals to sub-pixels p line by line along the first direction d1.
[0058] A display period t frames includes a first scan period t1 and a second scan period t2. In the first scan period t1, the first scan line GL_1 to the b-th scan line GL_b sequentially control the writing of data signals to the first sub-pixel p_1 to the b-th sub-pixel p_b electrically connected to the same data line SL along the first direction d1. a and b are both integers greater than 0, a is greater than b, and b is greater than or equal to 1.
[0059] During the first scan cycle t1, the first transistor T1 receives the first clock signal provided by the first clock control terminal CK1 and is turned on during the conduction period of the first scan cycle t1, writing data signals to the first sub-pixel p_1 to the b-th sub-pixel p_b electrically connected to the same data line SL. Thus, the pixel voltage of the first sub-pixel p_1 to the b-th sub-pixel p_b electrically connected to the same data line SL is related to the conduction degree of the first transistor T1.
[0060] In the second scan cycle t2, the b+1th scan line GL_b+1 to the ath scan line GL_a are scanned line by line along the first direction d1, and the data signals of the b+1th sub-pixel p_b+1 to the ath sub-pixel p_a, which are electrically connected to the same data line SL, are written line by line.
[0061] During the second scan cycle t2, the demultiplexing unit receives the second clock signal provided by the second clock control terminal CK2. The second transistor T2 in the demultiplexing unit is turned on during the conduction period of the second scan cycle t2, and writes data signals to the (b+1)th sub-pixel p_b+1 to the (a)th sub-pixel p_a that are electrically connected to the same data line SL. Thus, the pixel voltage of the (b+1)th sub-pixel p_b+1 to the (a)th sub-pixel p_a that are electrically connected to the same data line SL is related to the conduction degree of the second transistor T2.
[0062] Therefore, the detection module 30 only needs to detect the pixel voltage of one sub-pixel from the first sub-pixel p_1 to the b-th sub-pixel p_b, and the pixel voltage of one sub-pixel from the (b+1)-th sub-pixel p_b+1 to the a-th sub-pixel p_a. Thus, the detection module 30 only needs to be electrically connected to one sub-pixel from the first sub-pixel p_1 to the b-th sub-pixel p_b, and to one sub-pixel from the (b+1)-th sub-pixel p_b+1 to the a-th sub-pixel p_a.
[0063] In other embodiments, a display period tframe includes two first scan periods t1 and two second scan periods t2, with the first scan periods t1 and the second scan periods t2 alternating.
[0064] In the first scan cycle t1_1, the first scan line GL_1 to the c1th scan line GL_c1 control the writing of data signals to the first sub-pixel p_1 to the c1th sub-pixel p_c1 electrically connected to the same data line SL line by line along the first direction d1.
[0065] In the first scan cycle t1_1, the first transistor T1 receives the first clock signal provided by the first clock control terminal CK1 and turns on during the conduction period in the first scan cycle t1_1, writing data signals to the first sub-pixel p_1 to the c1th sub-pixel p_c1 electrically connected to the same data line SL. Thus, the pixel voltage of the first sub-pixel p_1 to the c1th sub-pixel p_c1 electrically connected to the same data line SL is related to the conduction degree of the first transistor T1.
[0066] In the first second scan cycle t2_1, the (c1+1)th scan line GL_c1+1 to the (c2)th scan line GL_c2 controls the writing of data signals to the (c1+1)th sub-pixel p_c1+1 to the (c2)th sub-pixel p_c2, which are electrically connected to the same data line SL, line by line along the first direction d1.
[0067] In the first second scan cycle t2_1, the second transistor T2 receives the second clock signal provided by the second clock control terminal CK2 and is turned on during the conduction period of the first second scan cycle t2_1, writing data signals to the c1+1th sub-pixel p_c1+1 to the c2th sub-pixel p_c2 which are electrically connected to the same data line SL. Thus, the pixel voltage of the c1+1th sub-pixel p_c1+1 to the c2th sub-pixel p_c2 which are electrically connected to the same data line SL is related to the conduction degree of the second transistor T2.
[0068] In the second first scan cycle t1_2, the c2+1 scan line GL_c2+1 to the c3 scan line GL_c3 control the c2+1 sub-pixel p_c2+1 to the c3 sub-pixel p_c3 electrically connected to the same data line SL to write data signals line by line along the first direction d1.
[0069] In the second first scan cycle t1_2, the first transistor T1 receives the first clock signal provided by the first clock control terminal CK1. Similarly, the pixel voltage of the c2+1th sub-pixel p_c2+1 to the c3th sub-pixel p_c3, which are electrically connected to the same data line SL, is related to the conduction degree of the first transistor T1.
[0070] In the second second scan cycle t2_2, the c3+1 scan line GL_c3+1 to the a scan line GL_a control the writing of data signals to the c3+1 sub-pixels p_c3+1 to the a sub-pixels p_a, which are electrically connected to the same data line SL, line by line along the first direction d1.
[0071] In the second second scan cycle t2_2, the second transistor T2 receives the second clock signal provided by the second clock control terminal CK2. Similarly, the pixel voltages of the c3+1th sub-pixel p_c3+1 to the ath sub-pixel p_a, which are electrically connected to the same data line SL, are related to the conduction degree of the second transistor T2.
[0072] a, c1, c2, and c3 are all integers greater than 0, c3 is greater than c2, c2 is greater than c1, and c1 is greater than or equal to 1.
[0073] Therefore, the detection module 30 only needs to detect the pixel voltage of one of the sub-pixels from the first sub-pixel p_1 to the c1th sub-pixel p_c1 or the pixel voltage of one of the sub-pixels from the c2+1th sub-pixel p_c2+1, and the pixel voltage of one of the sub-pixels from the c1+1th sub-pixel p_c1+1 to the c2th sub-pixel p_c2 or the pixel voltage of one of the sub-pixels from the c3+1th sub-pixel p_c3+1 to the ath sub-pixel p_a.
[0074] like Figure 3 As shown, the first scan period t1 may include m first sub-scan periods t11, and the second scan period t2 may include m second sub-scan periods t12.
[0075] The first sub-scan cycle t11_1 to the m-th sub-scan cycle t11_m are sequential in time, and each sub-scan cycle t11 drives at least one scan line GL to open.
[0076] The first second sub-scan cycle t21_1 to the m-th second sub-scan cycle t21_m are sequential in time, and each second sub-scan cycle t21 drives at least one scan line GL to open. Furthermore, the number of scan lines GL opened by the first sub-scan cycle t11 is the same as the number of scan lines GL opened by the second sub-scan cycle t21. For example, if the first sub-scan cycle t11 drives e scan lines GL to open, then the second sub-scan cycle t21 drives e scan lines GL to open, where e is an integer greater than or equal to 1.
[0077] The detection module 30 is electrically connected to the first sub-pixel p01 under test that receives a data signal in the nth first sub-scan period t11_n, and the detection module 30 is electrically connected to the second sub-pixel p02 under test that receives a data signal in the nth second sub-scan period t21_n. m and n are both integers, n is greater than or equal to 1, and m is greater than or equal to n.
[0078] Combination Figure 2 as well as Figure 3 As shown, the following explanation will be based on an example of a first scan cycle t1 in a display period t frame, which includes three first sub-scan cycles t11, and a second scan cycle t2, which includes three second sub-scan cycles t21. Furthermore, each first sub-scan cycle t11 drives one scan line GL to open, and each second sub-scan cycle t21 drives one scan line GL to open.
[0079] In the first sub-scanning cycle t11_1 of the first first scan cycle t1_1, the first scan line GL_1 is turned on, and the sub-pixel p_f1, which is electrically connected to the f-th data line SL_f and the first scan line GL_1, writes a data signal. In the second sub-scanning cycle t11_2 of the first first scan cycle t1_1, the second scan line GL_2 is turned on, and the sub-pixel p_f2, which is electrically connected to the f-th data line SL_f and the second scan line GL_2, writes a data signal. In the third sub-scanning cycle t11_3 of the first first scan cycle t1_1, the third scan line GL_3 is turned on, and the sub-pixel p_f3, which is electrically connected to the f-th data line SL_f and the third scan line GL_3, writes a data signal. f is an integer greater than or equal to 1.
[0080] Since the first transistor T1 is turned on during the conduction period of the first scan cycle t1 based on the first clock signal, the pixel voltages of sub-pixels p_f1, p_f2, and p_f3, which are electrically connected to the f-th data line SL_f, are related to the conduction level of the first transistor T1. The conduction level of the first transistor T1 affects the charging time of sub-pixels p_f1, p_f2, and p_f3, and thus affects the pixel voltage values of sub-pixels p_f1, p_f2, and p_f3.
[0081] In the first second sub-scanning cycle t21_1 of the first second scan cycle t2_1, the fourth scan line GL_4 is turned on, and the sub-pixel p_f4, which is electrically connected to the f-th data line SL_f and the fourth scan line GL_4, writes a data signal; in the second second sub-scanning cycle t21_2 of the first second scan cycle t1_2, the fifth scan line GL_5 is turned on, and the sub-pixel p_f5, which is electrically connected to the f-th data line SL_f and the fifth scan line GL_5, writes a data signal; in the third second sub-scanning cycle t21_3 of the first second scan cycle t1_2, the sixth scan line GL_6 is turned on, and the sub-pixel p_f6, which is electrically connected to the f-th data line SL_f and the sixth scan line GL_6, writes a data signal.
[0082] Since the second transistor T2 is turned on during the conduction period of the second scan cycle t2 based on the second clock signal, the pixel voltages of sub-pixels p_f4, p_f5, and p_f6, which are electrically connected to the f-th data line SL_f, are related to the conduction level of the second transistor T2. The conduction level of the second transistor T2 affects the charging time of sub-pixels p_f4, p_f5, and p_f6, thus affecting the pixel voltage values of these sub-pixels, resulting in brightness differences among the multiple sub-pixels.
[0083] When the display panel 10 displays a pure grayscale image, the brightness of different sub-pixels p is inconsistent when the first transistor T1 and the second transistor T2 are turned on alternately. This results in three rows of sub-pixels being too bright and three rows of sub-pixels being too dark, causing horizontal stripes to appear when the display panel displays a pure grayscale image.
[0084] The detection module 30 is electrically connected to sub-pixel p_f1 and sub-pixel p_f4, thereby detecting the charging difference generated on sub-pixel p_f1 and sub-pixel p_f4 when the first transistor T1 and the second transistor T2 of the same demultiplexing unit are turned on for the first time.
[0085] In some preferred embodiments provided in this application, the detection module 30 and the first data line SL_1 ( Figure 2 The leftmost data line SL) is electrically connected, or the detection module 30 is connected to the last data line SL_12. Figure 2The rightmost data line SL is electrically connected. Connecting the detection module 30 to the first data line SL_1 or to the last data line SL_12 facilitates the design of the wiring layout between the first sub-pixel p01 to be tested, the second sub-pixel p02 to be tested, and the detection module 30 within the surface of the display panel 10, ensuring that the other wiring layouts of the display panel 10 do not need to be changed due to the addition of the detection module 30.
[0086] The detection module 30 is used to detect the first pixel voltage of the first sub-pixel p01 to be tested and the second pixel voltage of the second sub-pixel p02 to be tested, and output a feedback signal based on the first pixel voltage and the second pixel voltage.
[0087] When multiple sub-pixels p electrically connected to the same data line are charged for the same duration by multiple scan lines GL, the magnitude of the first pixel voltage of the first sub-pixel p01 under test is related to the voltage value of the data signal at the multiplexed data signal input terminal IN and the degree of conduction of the demultiplexing unit when it receives the first clock signal. Similarly, the magnitude of the second pixel voltage of the second sub-pixel p02 under test is related to the voltage value of the data signal at the multiplexed data signal input terminal IN and the degree of conduction of the demultiplexing unit when it receives the second clock signal. When multiple sub-pixels p electrically connected to the same data line SL display the same grayscale, the data signal provided by the multiplexed data signal input terminal IN is the same. Therefore, the magnitude of the first pixel voltage of the first sub-pixel p01 under test is related to the degree of conduction of the demultiplexing unit when it receives the first clock signal, and the magnitude of the second pixel voltage of the second sub-pixel p02 under test is related to the degree of conduction of the demultiplexing unit when it receives the second clock signal.
[0088] Therefore, by detecting the first pixel voltage of the first sub-pixel p01 under test and the second pixel voltage of the second sub-pixel p02 under test by the detection module 30, the difference between the degree of conduction of the demultiplexing unit based on the first clock signal and the degree of conduction based on the second clock signal can be determined.
[0089] like Figure 4 As shown, the detection module 30 includes a first sampling unit 301, a second sampling unit 302, and a comparison unit 303.
[0090] The first sampling unit 301 is electrically connected to the first sub-pixel under test p01. The first sampling unit 301 is used to generate a first sampling signal based on the first pixel voltage V1 of the first sub-pixel under test p01. The first sampling unit 301 may include a first sampling resistor, or it may include multiple first sampling resistors connected in series or in parallel. The resistance value of the first sampling resistor and the number of first sampling resistors R1 can be determined according to actual needs.
[0091] The second sampling unit 302 is electrically connected to the second sub-pixel under test p02. The second sampling unit 302 is used to generate a second sampling signal based on the second pixel voltage V2 of the second sub-pixel under test p02. The second sampling unit 302 may include a second sampling resistor, or it may include multiple second sampling resistors connected in series or in parallel. The resistance value and the number of second sampling resistors can be determined according to actual needs.
[0092] The first input terminal of the comparison unit 303 is electrically connected to the first sampling unit 301, the second input terminal of the comparison unit 303 is electrically connected to the second sampling unit 302, and the output terminal of the comparison unit 303 is electrically connected to the compensation module 40. The comparison unit 303 is used to output a feedback signal to the compensation module 40 based on the first sampling signal provided by the first sampling unit 301 and the second sampling signal provided by the second sampling unit 302.
[0093] Comparison unit 303 can be a comparator, such as Figure 4 As shown, the first sampling unit 301 is electrically connected to the negative input terminal of the comparator, and the second sampling unit 302 is electrically connected to the positive input terminal of the comparator. The comparator compares the voltage values of the first and second sampled signals. When the voltage value of the first sampled signal is greater than the voltage value of the second sampled signal, the comparator outputs a low-level feedback signal to the compensation module 40. When the voltage value of the first sampled signal is less than the voltage value of the second sampled signal, the comparator outputs a high-level feedback signal to the compensation module 40.
[0094] Similarly, the first sampling unit 301 is electrically connected to the non-inverting input terminal of the comparator, and the second sampling unit 302 is electrically connected to the negative-inverting input terminal of the comparator. When the voltage value of the first sampling signal is greater than the voltage value of the second sampling signal, the comparator outputs a high-level feedback signal to the compensation module 40. When the voltage value of the first sampling signal is less than the voltage value of the second sampling signal, the comparator outputs a low-level feedback signal to the compensation module 40.
[0095] The compensation module 40 is electrically connected to the detection module 30. The compensation module 40 is used to output a compensation signal based on a feedback signal. That is, the compensation module 40 is used to output a first compensation signal based on a feedback signal indicating that the voltage value of the first sampled signal is greater than the voltage value of the second sampled signal, or the compensation module 40 is used to output a second compensation signal based on a feedback signal indicating that the voltage value of the first sampled signal is less than the voltage value of the second sampled signal.
[0096] In other embodiments provided in this application, the compensation module 40 is further used to determine whether the current image displayed by the display panel 10 is a pure grayscale image, and when the current image is a pure grayscale image, outputs a compensation signal to the clock signal control module 50. A pure grayscale image refers to an image in which all sub-pixels p of the display panel 10 display the same grayscale value. Therefore, when the display panel 10 displays a pure grayscale image, the data signals provided by the multiplexed data signal input terminal IN to different data lines G10 are the same, and the pixel voltage value of the sub-pixel is directly related to the conduction degree of the first transistor T1 or the second transistor T2.
[0097] like Figure 5 As shown, the compensation module 40 includes a grayscale acquisition unit 401, a grayscale judgment unit 402, a sub-pixel quantity judgment unit 403, and a processing unit 404.
[0098] The grayscale acquisition unit 401 is used to acquire the first grayscale of a sub-pixel in the current image. The grayscale acquisition unit 401 can acquire the first grayscale of all sub-pixels in a preset area of the display panel 10 in the current image. The preset area can be the entire display area AA of the display panel 10, or it can be a part of the display area AA. The grayscale judgment unit 402 is used to calculate the first number of sub-pixels whose first grayscale is greater than the preset grayscale. The sub-pixel number judgment unit 403 is used to compare the first number with the preset number, and output a compensation control signal based on the comparison result that the first number is greater than or equal to the preset number. The processing unit 404 is used to output a compensation signal to the clock signal control module 50 based on the compensation control signal provided by the sub-pixel number judgment unit 403 and the feedback signal provided by the detection module 30.
[0099] The compensation module 40 can be a timing controller. The grayscale acquisition unit 401, grayscale judgment unit 402 and sub-pixel quantity judgment unit 403 can be implemented by setting the pattern detection function (PDF) related registers through the timing controller to detect the features of the pure grayscale image.
[0100] The clock signal control module 50 is electrically connected to the first clock control terminal CK1, the second clock control terminal CK2, and the compensation module 40. The clock signal control module 50 is used to compensate the voltage value of the first clock signal or the voltage value of the second clock signal based on the compensation signal provided by the compensation module 40.
[0101] That is, the clock signal control module 50 is used to compensate the voltage value of the second clock signal based on the first compensation signal, or the clock signal control module 50 is used to compensate the voltage of the first clock signal based on the second compensation signal.
[0102] The first compensation signal is a compensation signal output by the compensation module 40 based on a feedback signal indicating that the voltage value of the first sampled signal is greater than the voltage value of the second sampled signal. In this case, the conduction degree of the first transistor T1 is greater than that of the second transistor T2. Therefore, the conduction degree of the second transistor T2 needs to be adjusted, that is, the voltage value of the second clock signal received by the gate of the second transistor T2 needs to be compensated to increase the conduction degree of the second transistor T2, thereby increasing the charging time of the corresponding sub-pixel.
[0103] The second compensation signal is a compensation signal output by the compensation module 40 based on the feedback signal that the voltage value of the first sampling signal is less than the voltage value of the second sampling signal. In this case, the conduction degree of the first transistor T1 is less than that of the second transistor T2. Therefore, the conduction degree of the first transistor T1 needs to be adjusted, that is, the voltage value of the first clock signal received by the gate of the first transistor T1 needs to be compensated to increase the conduction degree of the first transistor T1, thereby increasing the charging time of the corresponding sub-pixel.
[0104] like Figure 6 As shown, the clock signal control module 50 may include a power management integrated chip (PMIC) and a level shifter (LVSH). The PMIC compensates the voltage value of the second constant voltage high-level signal VGH2 based on the received first compensation signal COMP1, and provides the compensated second constant voltage high-level signal VGH2 to the LVSH. The LVSH then provides the compensated second clock signal to the second clock control terminal CK2_R / G / B based on the compensated second constant voltage high-level signal VGH2 to compensate the voltage value of the second clock signal, thereby increasing the conduction degree of the second transistor T2, increasing the charging time of the corresponding sub-pixel, and improving the luminous brightness of the sub-pixel. The PMIC compensates the voltage value of the first constant-voltage high-level signal VGH1 based on the received second compensation signal COMP2, and provides the compensated first constant-voltage high-level signal VGH1 to the LVSH. The LVSH then provides a compensated first clock signal to the first clock control terminal CK1_R / G / B based on the compensated first constant-voltage high-level signal VGH1, in order to compensate the voltage value of the first clock signal, thereby increasing the conduction level of the first transistor T1, increasing the charging time of the corresponding sub-pixel, and improving the luminous brightness of the sub-pixel, thus solving the problem of… Figure 2 When the display panel shown is used to display a pure grayscale image, three rows of sub-pixels appear too bright and three rows of sub-pixels appear too dark. This solution addresses the issue of horizontal stripes appearing on the display screen and improves the uniformity of brightness and darkness in the display image.
[0105] like Figure 7As shown, the display device 100 also includes a detection control module 60. The detection control module 60 is electrically connected to the power supply terminal Vcc, the detection module 30, and the compensation module 40. The detection control module 60 outputs a power signal from the power supply terminal Vcc to the detection module 30 based on the detection control signal provided by the compensation module 40, causing the detection module 30 to operate according to the power signal. The compensation module 40 provides a detection control signal to the detection module 30 based on the current display screen being a pure grayscale screen, so that the compensation module 40 first determines whether the current screen is a pure grayscale screen, and then controls the detection module 30 to operate.
[0106] The display device 100 provided in this application embodiment detects the pixel voltage of the first and second sub-pixels to be tested electrically connected to the same data line by setting a detection module 30, and compensates the voltage value of the first clock signal or the voltage value of the second clock signal based on the detection result, so as to control the charging time of the sub-pixels electrically connected to the same data line to be consistent or substantially consistent, thereby ensuring that the sub-pixels on the same data line emit light with consistent brightness based on the same data signal provided by the multiplexed data input terminal IN.
[0107] Of course, this application may have other various embodiments. Without departing from the spirit and essential points of this application, those skilled in the art can make various corresponding changes and modifications based on this application, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.
Claims
1. A display device, characterized in that, include: The display panel includes multiple data lines, multiple scan lines, and multiple sub-pixels, wherein one of the sub-pixels is electrically connected to one of the data lines and one of the scan lines; At least one demultiplexing module is provided, the demultiplexing module comprising multiple demultiplexing units. A first transistor of each demultiplexing unit is electrically connected to a first clock control terminal, and a second transistor of each demultiplexing unit is electrically connected to a second clock control terminal. The source of the first transistor is electrically connected to the multiplexed data signal input terminal of the display device, and the drain of the first transistor is electrically connected to a data line. The source of the second transistor is electrically connected to the source of the first transistor, and the drain of the second transistor is electrically connected to the drain of the first transistor. The first transistor is used to provide the data signal from the multiplexed data signal input terminal to the data line under the control of a first clock signal from the first clock control terminal, and the second transistor is used to provide the data signal to the data line under the control of a second clock signal from the second clock control terminal. A detection module is electrically connected to a first sub-pixel under test that receives the data signal based on the conduction of the first transistor, and the detection module is also electrically connected to a second sub-pixel under test that receives the data signal based on the conduction of the second transistor. The detection module is used to detect the first pixel voltage of the first sub-pixel under test and the second pixel voltage of the second sub-pixel under test, and output a feedback signal based on the first pixel voltage and the second pixel voltage, wherein the first sub-pixel under test and the second sub-pixel under test are two sub-pixels electrically connected to the same data line. A compensation module, which is electrically connected to the detection module, is used to output a compensation signal based on the feedback signal; A clock signal control module is electrically connected to the first clock control terminal, the second clock control terminal, and the compensation module. The clock signal control module is used to compensate the voltage value of the first clock signal or the voltage value of the second clock signal based on the compensation signal.
2. The display device according to claim 1, characterized in that, The display panel displays a frame of an image, and the display cycle includes at least one first scan cycle and at least one second scan cycle, with the first scan cycle and the second scan cycle alternating. The first transistor is used to output the data signal to the first sub-pixel under test after receiving the first clock signal in the first scan cycle, and the second transistor is used to output the data signal to the second sub-pixel under test after receiving the second clock signal in the second scan cycle. The detection module is electrically connected to the first sub-pixel under test that receives the data signal in the first scan cycle, and the detection module is electrically connected to the second sub-pixel under test that receives the data signal in the second scan cycle.
3. The display device according to claim 2, characterized in that, The first scan cycle includes m first sub-scan cycles, and the second scan cycle includes m second sub-scan cycles; The detection module is electrically connected to the first sub-pixel under test that receives the data signal in the nth first sub-scan cycle, and the detection module is electrically connected to the second sub-pixel under test that receives the data signal in the nth second sub-scan cycle. Where m and n are integers, n is greater than or equal to 1, and m is greater than or equal to n.
4. The display device according to any one of claims 1-3, characterized in that, The first transistor and the second transistor are both N-type transistors, or the first transistor and the second transistor are both P-type transistors.
5. The display device according to claim 1, characterized in that, The compensation module is also used to determine whether the current image displayed on the display panel is a pure grayscale image, and when the current image is a pure grayscale image, output the compensation signal to the clock signal control module.
6. The display device according to claim 5, characterized in that, The compensation module includes a grayscale acquisition unit, a grayscale judgment unit, a sub-pixel quantity judgment unit, and a processing unit. The grayscale acquisition unit is used to acquire the first grayscale of the sub-pixel in the current image; The grayscale determination unit is used to calculate the first number of sub-pixels whose first grayscale is greater than a preset grayscale. The sub-pixel quantity determination unit is used to compare the size of the first quantity and the preset quantity, and output a compensation control signal based on the comparison result that the first quantity is greater than or equal to the preset quantity; The processing unit is used to output the compensation signal based on the compensation control signal and the feedback signal.
7. The display device according to claim 1 or 5, characterized in that, The detection module includes a first sampling unit, a second sampling unit, and a comparison unit; The first sampling unit is electrically connected to the first sub-pixel under test, and the first sampling unit is used to generate a first sampling signal based on the voltage of the first pixel; The second sampling unit is electrically connected to the second sub-pixel under test, and the second sampling unit is used to generate a second sampling signal based on the voltage of the second pixel; The first input terminal of the comparison unit is electrically connected to the first sampling unit, the second input terminal of the comparison unit is electrically connected to the second sampling unit, and the output terminal of the comparison unit is electrically connected to the compensation module. The comparison unit is used to output the feedback signal based on the first sampling signal and the second sampling signal.
8. The display device according to claim 7, characterized in that, The compensation module is used to output a first compensation signal based on the feedback signal indicating that the voltage value of the first sampled signal is greater than the voltage value of the second sampled signal; Alternatively, the compensation module may output a second compensation signal based on the feedback signal indicating that the voltage value of the first sampled signal is less than the voltage value of the second sampled signal.
9. The display device according to claim 8, characterized in that, The clock signal control module is used to compensate the voltage value of the second clock signal based on the first compensation signal; Alternatively, the clock signal control module is used to compensate the voltage value of the second clock signal based on the second compensation signal.
10. The display device according to claim 1 or 5, characterized in that, The display device further includes a detection and control module, which is electrically connected to the power supply, the compensation module, and the detection module. The detection and control module is used to perform detection and control based on the detection and control signals provided by the compensation module. The power signal from the power supply terminal is output to the detection module.