PCIE high time uniformity transmission method based on DMA ring buffer
By using a DMA ring buffer and interrupt signal coordination, the problem of insufficient time uniformity in the PCIE transmission method is solved, realizing the time uniformity and real-time performance of data transmission in the power industry, while maintaining the flexibility and efficiency of transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUPER HIGH VOLTAGE BRANCH OF STATE GRID JIANGXI ELECTRIC POWER CO LTD
- Filing Date
- 2023-11-13
- Publication Date
- 2026-06-09
AI Technical Summary
Existing PCIe transmission methods struggle to achieve high temporal uniformity in the power industry, especially given the limitations of processor scheduling characteristics, making it difficult to meet the temporal uniformity requirements for data transmission.
A PCIE high time uniformity transmission method based on DMA ring buffer is adopted. The main controller, PCIE device and DMA transmission controller are coordinated by periodic interrupt signals. A ring linked list is constructed to manage the DMA send and receive area. The transmission rate is controlled by the interrupt signal frequency to ensure the time uniformity and real-time performance of data transmission.
It achieves time uniformity in PCIe message transmission, maintains transmission flexibility and real-time performance, and ensures efficient transmission of power business data by controlling the transmission rate through interrupt signal frequency.
Smart Images
Figure CN117499173B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer communication in the power industry, and specifically to a PCIE high time uniformity transmission method based on DMA ring buffer. Background Technology
[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard, and its PCIe 6.0 standard was released on January 12, 2022. Currently, various versions of PCIe are widely used in device communication across different fields. In the power industry, with the increasing adoption of smart devices, the amount of data collected for related business operations is gradually increasing, necessitating the introduction of PCIe communication technology to adapt to the industry's development pace.
[0003] Meanwhile, data transmission in the power industry has high requirements for real-time performance and time uniformity, and there are many types of service messages. In previous PCIe transmission methods, although processor-initiated PCIe transmission control could achieve high real-time performance, it was difficult to achieve high time uniformity due to the scheduling characteristics of the system running on the processor. Summary of the Invention
[0004] To address the above issues and ensure accurate time uniformity of power business data transmission, this invention proposes a PCIe high time uniformity transmission method based on a DMA ring buffer. This method, in conjunction with external interrupts, enables high time uniformity in PCIe packet transmission.
[0005] The above-mentioned objectives of the present invention are achieved through the following technical means:
[0006] A PCIe high time uniformity transmission method based on DMA ring buffer includes the following message transmission steps:
[0007] PCIe devices periodically send interrupt signals.
[0008] When the main controller receives an interrupt signal, it generates TLP information required for the PCIe read request based on the starting address of the DMA transmit area and the total data length of the message. The TLP information is then sent to the PCIe device read control module via the PCIe bus controller.
[0009] When the PCIe device read control module receives an interrupt signal, it generates a memory read request TLP transaction based on the TLP information.
[0010] Based on the memory read request (TLP) transaction, between the current interrupt signal and the next interrupt signal, the PCIe bus controller controls the DMA transfer controller to read the total message from the main memory and send the total message to the PCIe device read control module.
[0011] The PCIe device read control module parses the total message obtained between the current interrupt signal and the previous interrupt signal, and sends each sub-message in the total message to the corresponding port of the PCIe device.
[0012] As described above, the main controller includes a message sending module and a sending control module.
[0013] The main controller constructs a transmit ring list, requests multiple DMA transmit areas from the main memory, records the starting address of each DMA transmit area in the transmit ring list, adds the state machine parameters corresponding to the starting address of each DMA transmit area to the transmit ring list, and initializes the state machine parameters corresponding to the starting address of each DMA transmit area to the idle state.
[0014] When the main controller's message sending module receives an interrupt signal from a PCIe device, it traverses the circular linked list of messages:
[0015] The starting address of the DMA send area in the send ring list whose state machine parameters are in the "writing" state is taken as the starting address of the sendable DMA send area. The state machine parameters of the sendable DMA send area starting address are then modified to the sendable state.
[0016] The starting address of the DMA send area in the send ring list with the state machine parameter set to idle is selected as the starting address of the write DMA send area. The state machine parameter of the write DMA send area starting address is then modified to the writing state. Between the current interrupt signal and the next interrupt signal, the service data to be sent is packaged into a total message according to the data transmission protocol format, and the packaged total message is copied to the starting address of the write DMA send area.
[0017] When the main controller's transmit control module receives an interrupt signal from a PCIe device, it traverses the transmit circular linked list:
[0018] The starting address of the DMA send area in the sending circular list whose state machine parameters are in the "sending" state is used as the starting address of the sending idle DMA send area. The state machine parameters of the starting address of the sending idle DMA send area are then modified to the "idle" state.
[0019] The starting address of the DMA send area in the send ring list whose state machine parameter is in the sendable state is selected as the starting address of the DMA send area in the send ring list. TLP information is generated based on the starting address of the DMA send area in the send ring list and the total data length of the message. The TLP information is sent to the PCIe device read control module through the PCIe bus controller, and the state machine parameter of the starting address of the DMA send area in the send ring list is set to the sendable state.
[0020] As described above, the PCIe device read control module includes a first BAR space, a PCIe read unit, a first FIFO, a second FIFO, and a destination port control unit.
[0021] The first BAR space is used to receive and store TLP information and send the TLP information to the PCIE read unit. The PCIE read unit generates a memory read request (TLP) transaction based on the TLP information and sends the memory read request (TLP) transaction to the PCIE bus controller. The PCIE bus controller controls the DMA transfer controller to read the total message of the corresponding length and address in the DMA send area based on the memory read request (TLP) transaction. The total message is transmitted to the PCIE read unit via the PCIE bus controller. The PCIE read unit stores the read total message in the first FIFO. The destination port control unit unpacks the total message in the second FIFO according to the data transmission protocol format to obtain each sub-message. By parsing the destination port field in the sub-message, the sub-message is transmitted to the corresponding port. Finally, the first FIFO is used as the second FIFO, and the second FIFO is used as the first FIFO.
[0022] The PCIe high time uniformity transmission method based on DMA ring buffer also includes a message reception step:
[0023] PCIe devices periodically send interrupt signals.
[0024] When the main controller receives an interrupt signal, it generates TLP information based on the starting address of the DMA receive area during writing. The TLP information is then sent to the PCIe device write control module via the PCIe bus controller.
[0025] After receiving the TLP information, the PCIe device write control module writes the total length of the data received from the port between the current interrupt signal and the previous interrupt signal into the TLP information. Based on the TLP information, it generates a memory write request (TLP) transaction. The PCIe bus controller reads the total data between the current interrupt signal and the previous interrupt signal through the memory write request (TLP) transaction and initiates a DMA transfer operation to the DMA transfer controller, writing the total data between the current interrupt signal and the previous interrupt signal into the main memory at the address corresponding to the starting address of the DMA receive area during the write operation.
[0026] As described above, the main controller includes a message parsing module and a receive control module.
[0027] The main controller constructs a receiving circular linked list, requests multiple DMA receiving areas from the main memory, records the starting address of each DMA receiving area in the receiving circular linked list, adds the state machine parameters corresponding to the starting address of each DMA receiving area to the receiving circular linked list, and initializes the state machine parameters corresponding to the starting address of each DMA receiving area to the idle state.
[0028] When the message parsing module of the main controller receives an interrupt signal, it traverses the receive circular linked list:
[0029] The starting address of the DMA receive area whose state machine parameter in the receive circular linked list is in the "reading" state is used as the starting address of the receive idle DMA receive area, and the state machine parameter corresponding to the starting address of the receive idle DMA receive area is modified to the "idle" state.
[0030] The starting address of the DMA receive area whose state machine parameters in the receive circular linked list are set to readable is selected as the starting address of the DMA receive area being read. The state machine parameters corresponding to the starting address of the DMA receive area being read are then modified to the reading state. Between the current interrupt signal and the next interrupt signal, the reading and parsing of the total message under the starting address of the DMA receive area being read is completed.
[0031] When the receiving control module receives an interrupt signal from the PCIe device, it traverses the receiving circular linked list:
[0032] The starting address of the DMA receive area whose state machine parameter is in the "writing" state in the receive circular linked list is taken as the starting address of the readable DMA receive area, and the state machine parameter corresponding to the starting address of the readable DMA receive area is modified to the readable state.
[0033] The starting address of the DMA receive area whose state machine parameter is in the idle state is selected as the starting address of the DMA receive area in the write process. TLP information is generated based on the starting address of the DMA receive area in the write process and written into the PCIe device write control module. The state machine parameter of the starting address of the DMA receive area in the write process is set to the write process state.
[0034] As described above, the PCIe device write control module includes a second BAR space, a PCIe write unit, a third FIFO, a fourth FIFO, and a source port control unit.
[0035] Between the current interrupt signal and the previous interrupt signal, the source port control unit generates a total message from the data received from the external port according to the data transmission protocol format and stores it in the third FIFO. When the PCIe device write control module receives an interrupt signal, the source port control unit writes the length of the data received from the external port between the current interrupt signal and the previous interrupt signal into the TLP information stored in the second BAR space. The PCIe write unit generates a memory write request (TLP) transaction based on the TLP information. The PCIe bus controller reads the total message in the third FIFO through the memory write request (TLP) transaction. The total message in the third FIFO is transmitted to the PCIe bus controller. Based on the received memory write request (TLP) transaction and the received total message, the PCIe bus controller initiates a DMA transfer operation to the DMA transfer controller. Between the current interrupt signal and the next interrupt signal, the total message generated between the current interrupt signal and the previous interrupt signal is written into the DMA memory corresponding to the starting address of the DMA receive area in the main memory.
[0036] When the PCIe device write control module receives an interrupt signal, between the current interrupt signal and the next interrupt signal, the source port control unit generates a total message based on the data transmission protocol format from the messages received by the external port and stores it in the fourth FIFO.
[0037] When the next interrupt signal arrives, the original third FIFO will be used as the new fourth FIFO, and the original fourth FIFO will be used as the new third FIFO.
[0038] Compared with the prior art, the present invention has the following advantages:
[0039] In the solution provided by this invention, the message sending module, the sending control module, the message parsing module, the receiving control module, the PCI bus controller, the PCIE device write control module, and the PCIE device read control module all work in coordination through the clock provided by the interrupt signal, so that the total message transmission can achieve a high time uniformity. The transmission rate can be controlled by controlling the frequency of the interrupt signal, so that the flexibility and real-time performance of PCIE transmission are not lost while maintaining high uniformity. Attached Figure Description
[0040] Figure 1 This is the overall connection diagram of the present invention;
[0041] Figure 2 This is a schematic diagram of the overall message structure;
[0042] Figure 3 This is a schematic diagram of the message sending steps of the present invention;
[0043] Figure 4 This is a schematic diagram of the message receiving steps of the present invention. Detailed Implementation
[0044] To facilitate understanding and implementation of the present invention by those skilled in the art, the present invention will be further described in detail below with reference to examples. The implementation examples described herein are only for illustration and explanation and are not intended to limit the present invention.
[0045] like Figure 1 As shown, a PCIe high time uniformity transfer device based on DMA ring buffer includes:
[0046] Main controller: The main controller can be a general-purpose processor, an embedded processor, or a processor that can be connected to a PCIe bus controller.
[0047] PCIe bus controller: In different processor architectures, it is called Northbridge chip, Root Complex, etc. As the main management device for one or more PCIe buses, the PCIe bus controller is connected to PCIe devices through the PCIe bus. It can be integrated with the main controller and main memory, or it can be connected to the main controller through other system buses.
[0048] DMA transfer controller: Depending on the host controller architecture, it can be integrated into the host controller or the PCIe bus controller to provide direct memory access functionality without the intervention of the host controller.
[0049] Main memory: The data storage unit for the transmission protocol, which is connected to the main controller and the PCIe bus controller through the system bus. It can control the DMA transfer controller through the PCIe bus controller and initiate DMA operations to transfer data.
[0050] PCIe device: The terminal device can be an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or other devices with PCIe functionality, and also provides external interrupt signals from the interrupt module to the main controller.
[0051] The main controller includes a message sending module, a message sending control module, a message parsing module, and a message receiving control module.
[0052] A PCIe device includes a PCIe device read control module, a PCIe device write control module, and multiple ports.
[0053] The PCIe device read control module includes a first BAR space, a PCIe read unit, a first FIFO, a second FIFO, and a destination port control unit.
[0054] The PCIe device write control module includes a second BAR space, a PCIe write unit, a third FIFO, a fourth FIFO, and a source port control unit.
[0055] like Figure 2 As shown, a PCIe high time uniformity transfer method based on DMA ring buffer is proposed:
[0056] Data transmission protocol formats are divided into general packet protocols and sub-message protocols.
[0057] The fields of the general message in the general contracting protocol include:
[0058] Data length: The total length of all valid data in the total message (PCIe memory read transaction message / PCIe memory write transaction message), occupying 32 bits;
[0059] Number of sub-messages: The number of sub-messages in this total message, occupying 32 bits.
[0060] The fields of a submessage in the submessage protocol include:
[0061] Destination Port: Indicates where the sub-message will go, from which port of the PCIe device it will be sent, occupying 16 bits;
[0062] Source Port: Indicates which port of the PCIe device the sub-message originated from, occupying 16 bits;
[0063] Message type: Indicates the type of sub-message, such as TCP, UDP, SMV, GOOSE, and other types, occupying 16 bits;
[0064] Timestamp: Indicates the time when a sub-message is received. It is mainly used when a sub-message is received, otherwise it is reserved and occupies 64 bits.
[0065] Sub-message content: Indicates the actual content of the sub-message, occupying 64 to 1520 bytes, and needs to be aligned upwards by 8 bytes;
[0066] Sub-message count: This field increments by one for each sub-message sent or received, occupying 32 bits;
[0067] Sub-message CRC: Indicates the CRC check of this message, occupying 32 bits;
[0068] like Figure 3 As shown, a PCIe high temporal uniformity transfer method based on DMA ring buffer is proposed.
[0069] Including message sending steps:
[0070] Step 1: The main controller constructs a transmit ring list. The main controller requests multiple 128KB DMA memory blocks from the main memory to be used as DMA transmit areas. The starting address of each DMA transmit area is recorded in the transmit ring list. At the same time, the state machine parameters corresponding to the starting address of each DMA transmit area are added to the transmit ring list, and the state machine parameters corresponding to the starting address of each DMA transmit area are initialized to the idle state.
[0071] Step 2: When the main controller's message sending module receives an interrupt signal from the PCIe device, it traverses the sending circular linked list.
[0072] The starting address of the DMA send area with the state machine parameter set to "Writing" in the send ring list is taken as the starting address of the sendable DMA send area. At the same time, the state machine parameter of the sendable DMA send area starting address is modified to the "Sendable" state. That is, between the current interrupt signal and the previous interrupt signal, the starting address of the DMA send area with the state machine parameter set to "Writing" in the send ring list has completed the writing of the total packet after encapsulation.
[0073] The starting address of the DMA send area with the state machine parameter set to Idle in the send ring list is selected as the starting address of the write DMA send area. The state machine parameter of the write DMA send area starting address is then changed to the writing state. Between the current interrupt signal and the next interrupt signal, the service data to be sent is packaged into a total message according to the data transmission protocol format, and the packaged total message is copied to the DMA memory at the starting address of the write DMA send area.
[0074] Step 3: When the main controller's transmit control module receives an interrupt signal from the PCIe device, it traverses the transmit circular linked list.
[0075] The starting address of the DMA send area in the sending circular linked list whose state machine parameter is in the sending (Sending) state is used as the starting address of the sending idle DMA send area. The state machine parameter of the starting address of the sending idle DMA send area is modified to the idle (Idle) state. That is, the state machine parameter of the starting address of the DMA send area where the total message transmission has been completed between the current interrupt signal and the previous interrupt signal is modified to the idle (Idle) state.
[0076] Subsequently, the starting address of the DMA send area in the send ring list with the state machine parameter set to "Sendable" is selected as the starting address of the DMA send area in progress. The total data length of the message corresponding to the starting address of the DMA send area in progress is obtained through the total message data length field of the data transfer protocol format. Based on the starting address of the DMA send area in progress and the total message data length, TLP (Transaction Layer Packet) information required for the PCIe read request is generated, and this TLP information is written to the BAR address of the first BAR space of the PCIe device read control module via an I / O write (IOWr) operation through the PCIe bus controller. After completing the above operations, the state machine parameter of the starting address of the DMA send area in progress in the send ring list is set to the "Sending" state, meaning the DMA send area, which is ready to be sent, is then sent.
[0077] Step 4: The PCIe device read control module includes a first BAR space, a PCIe read unit, a first FIFO, a second FIFO, and a destination port control unit. When the PCIe device read control module receives an interrupt signal from the PCIe device, the PCIe read unit obtains TLP information from the first BAR space, further parses the TLP information to obtain the DMA send area start address and data length, generates a memory read request TLP transaction based on the parsed DMA send area start address and data length, and then sends the memory read request TLP transaction to the PCIe bus controller. Based on this memory read request TLP transaction, the PCIe bus controller controls the DMA transfer controller to read the corresponding length of the total message from the parsed (requested) DMA memory address, and transmits it to the PCIe read unit via the PCIe bus controller. The PCIe reading unit stores the read total message in the first FIFO (FIFO_1). Simultaneously, the destination port control unit (TX DST PORT CTRL) unpacks the total message in the second FIFO (FIFO_2) according to the data transmission protocol format, obtaining individual sub-messages. Based on the destination port field indication in the sub-messages, the sub-messages are transmitted to the corresponding port (PORT_N). Finally, the first FIFO is used as the second FIFO, and the second FIFO is used as the first FIFO. When the next interrupt signal arrives, a ping-pong operation is achieved.
[0078] like Figure 4 As shown, the PCIe high time uniformity transmission method based on DMA ring buffer also includes a message receiving step:
[0079] Step 1: The main controller constructs a receiving circular linked list. The main controller requests multiple 128KB DMA memory blocks from the main memory to be used as DMA receiving areas. The starting address of each DMA receiving area is recorded in the receiving circular linked list. At the same time, the state machine parameters corresponding to the starting address of each DMA receiving area are added to the receiving circular linked list, and the state machine parameters corresponding to the starting address of each DMA receiving area are initialized to the idle state.
[0080] Step 2: When the main controller's message parsing module receives an interrupt signal from the PCIe device, it traverses the receive circular linked list.
[0081] The starting address of the DMA receive area whose state machine parameter is in the Reading state in the receive circular linked list is used as the starting address of the receive idle DMA receive area. The state machine parameter corresponding to the starting address of the receive idle DMA receive area is modified to the Idle state. That is, the state machine parameter of the starting address of the DMA send area where the total message reading is completed between the current interrupt signal and the previous interrupt signal is modified to the Idle state.
[0082] The starting address of the DMA receive area with the state machine parameter set to "Readable" in the receive circular linked list is selected as the starting address of the DMA receive area being read. The state machine parameter corresponding to the starting address of the DMA receive area being read is modified to the "Reading" state. The total message under the starting address of the DMA receive area being read is parsed according to the data transmission protocol format to obtain the received total message. That is, the reading and parsing of the total message under the starting address of the DMA receive area being read is completed between the current interrupt signal and the next interrupt signal.
[0083] Step 3: When the receiving control module receives an interrupt signal from the PCIe device, it traverses the receiving circular linked list.
[0084] The starting address of the DMA receive area whose state machine parameter is in the "Writing" state in the receive circular linked list is taken as the starting address of the readable DMA receive area. The state machine parameter corresponding to the starting address of the readable DMA receive area is modified to the "Readable" state. That is, between the current interrupt signal and the previous interrupt signal, the writing of the total message obtained by the current interrupt signal and the previous interrupt signal is completed.
[0085] The starting address of the DMA receive area in the receive ring list whose state machine parameter is in the Idle state is selected as the starting address of the DMA receive area in the writing process. This starting address of the DMA receive area in the writing process is used to generate the TLP information required for the PCIe memory write transaction. This TLP information is then written to the BAR address of the second BAR space of the PCIe device write control module via an I / O write (IOWr) operation through the PCIe bus controller. After completing the above operations, the state machine parameter of the starting address of the DMA receive area in the writing process is set to the Writing state.
[0086] Step 4: The PCIe device write control module includes a second BAR space, a PCIe write unit, a third FIFO, a fourth FIFO, and a source port control unit.
[0087] Between the current interrupt signal and the previous interrupt signal, the source port control unit generates a total message from the data received from the external port according to the data transmission protocol format and stores it in the third FIFO (FIFO_3). When the PCIe device write control module receives an interrupt signal, the source port control unit writes the length of the data received from the external port between the current interrupt signal and the previous interrupt signal into the TLP information stored at the BAR address in the second BAR space. Simultaneously, the PCIe write unit parses the TLP information stored in the second BAR space and generates a memory write request TLP transaction. The PCIe bus controller reads the total message from the third FIFO through the memory write request TLP transaction, and the total message is transmitted to the PCIe bus controller. Based on the received memory write request TLP transaction and the total message generated between the current interrupt signal and the previous interrupt signal, the PCIe bus controller initiates a DMA transfer operation to the DMA transfer controller. Between the current interrupt signal and the next interrupt signal, the total message generated between the current interrupt signal and the previous interrupt signal is written into the DMA memory corresponding to the starting address of the DMA receive area in the main memory.
[0088] When the PCIe device write control module receives an interrupt signal, between the current interrupt signal and the next interrupt signal, the source port control unit generates a total message based on the data transmission protocol format from the messages received by the external ports (PORT_0 to PORT_N) and stores it in the fourth FIFO (FIFO_4).
[0089] When the next interrupt signal arrives, the original third FIFO is used as the new fourth FIFO, and the original fourth FIFO is used as the new third FIFO, achieving the effect of ping-pong operation.
[0090] It should be noted that the specific embodiments described in this invention are merely illustrative of the spirit of the invention. Those skilled in the art to which this invention pertains can make various modifications or additions to the described specific embodiments or use similar methods to substitute them, without departing from the spirit of the invention or exceeding the scope defined by the appended claims.
Claims
1. A PCIe high time uniformity transfer method based on DMA ring buffer, characterized in that, Including message sending steps: PCIe devices periodically send interrupt signals. When the main controller receives an interrupt signal, it generates TLP information required for the PCIe read request based on the starting address of the DMA transmit area and the total data length of the message. The TLP information is then sent to the PCIe device read control module via the PCIe bus controller. When the PCIe device read control module receives an interrupt signal, it generates a memory read request TLP transaction based on the TLP information. Based on the memory read request (TLP) transaction, between the current interrupt signal and the next interrupt signal, the PCIe bus controller controls the DMA transfer controller to read the total message from the main memory and send the total message to the PCIe device read control module. The PCIe device read control module parses the total message obtained between the current interrupt signal and the previous interrupt signal, and sends each sub-message in the total message to the corresponding port of the PCIe device. The main controller includes a message sending module and a sending control module. The main controller constructs a transmit ring list, requests multiple DMA transmit areas from the main memory, records the starting address of each DMA transmit area in the transmit ring list, adds the state machine parameters corresponding to the starting address of each DMA transmit area to the transmit ring list, and initializes the state machine parameters corresponding to the starting address of each DMA transmit area to the idle state. When the main controller's message sending module receives an interrupt signal from a PCIe device, it traverses the circular linked list of messages: The starting address of the DMA send area in the send ring list whose state machine parameters are in the "writing" state is taken as the starting address of the sendable DMA send area. The state machine parameters of the sendable DMA send area starting address are then modified to the sendable state. The starting address of the DMA send area in the send ring list with the state machine parameter set to idle is selected as the starting address of the write DMA send area. The state machine parameter of the write DMA send area starting address is then modified to the writing state. Between the current interrupt signal and the next interrupt signal, the service data to be sent is packaged into a total message according to the data transmission protocol format, and the packaged total message is copied to the starting address of the write DMA send area. When the main controller's transmit control module receives an interrupt signal from a PCIe device, it traverses the transmit circular linked list: The starting address of the DMA send area in the sending circular list whose state machine parameters are in the "sending" state is used as the starting address of the sending idle DMA send area. The state machine parameters of the starting address of the sending idle DMA send area are then modified to the "idle" state. The starting address of the DMA send area in the send ring list whose state machine parameter is in the sendable state is selected as the starting address of the DMA send area in the send ring list. TLP information is generated based on the starting address of the DMA send area in the send ring list and the total data length of the message. The TLP information is sent to the PCIe device read control module through the PCIe bus controller, and the state machine parameter of the starting address of the DMA send area in the send ring list is set to the sendable state.
2. The PCIe high time uniformity transmission method based on DMA ring buffer according to claim 1, characterized in that, The PCIe device read control module includes a first BAR space, a PCIe read unit, a first FIFO, a second FIFO, and a destination port control unit. The first BAR space is used to receive and store TLP information and send the TLP information to the PCIE read unit. The PCIE read unit generates a memory read request (TLP) transaction based on the TLP information and sends the memory read request (TLP) transaction to the PCIE bus controller. The PCIE bus controller controls the DMA transfer controller to read the total message of the corresponding length and address in the DMA send area based on the memory read request (TLP) transaction. The total message is transmitted to the PCIE read unit via the PCIE bus controller. The PCIE read unit stores the read total message in the first FIFO. The destination port control unit unpacks the total message in the second FIFO according to the data transmission protocol format to obtain each sub-message. By parsing the destination port field in the sub-message, the sub-message is transmitted to the corresponding port. Finally, the first FIFO is used as the second FIFO, and the second FIFO is used as the first FIFO.
3. The PCIe high time uniformity transmission method based on DMA ring buffer according to claim 1, characterized in that, It also includes the message receiving step: PCIe devices periodically send interrupt signals. When the main controller receives an interrupt signal, it generates TLP information based on the starting address of the DMA receive area during writing. The TLP information is then sent to the PCIe device write control module via the PCIe bus controller. After receiving the TLP information, the PCIe device write control module writes the total length of the data received from the port between the current interrupt signal and the previous interrupt signal into the TLP information. Based on the TLP information, it generates a memory write request (TLP) transaction. The PCIe bus controller reads the total data between the current interrupt signal and the previous interrupt signal through the memory write request (TLP) transaction and initiates a DMA transfer operation to the DMA transfer controller, writing the total data between the current interrupt signal and the previous interrupt signal into the main memory at the address corresponding to the starting address of the DMA receive area during the write operation.
4. The PCIe high time uniformity transmission method based on DMA ring buffer according to claim 3, characterized in that, The main controller includes a message parsing module and a receiving control module. The main controller constructs a receiving circular linked list, requests multiple DMA receiving areas from the main memory, records the starting address of each DMA receiving area in the receiving circular linked list, adds the state machine parameters corresponding to the starting address of each DMA receiving area to the receiving circular linked list, and initializes the state machine parameters corresponding to the starting address of each DMA receiving area to the idle state. When the message parsing module of the main controller receives an interrupt signal, it traverses the receive circular linked list: The starting address of the DMA receive area whose state machine parameter in the receive circular linked list is in the reading state is used as the starting address of the receive idle DMA receive area, and the state machine parameter corresponding to the starting address of the receive idle DMA receive area is modified to the idle state. The starting address of the DMA receive area whose state machine parameters in the receive circular linked list are set to readable is selected as the starting address of the DMA receive area being read. The state machine parameters corresponding to the starting address of the DMA receive area being read are then modified to the reading state. Between the current interrupt signal and the next interrupt signal, the reading and parsing of the total message under the starting address of the DMA receive area being read is completed. When the receiving control module receives an interrupt signal from the PCIe device, it traverses the receiving circular linked list: The starting address of the DMA receive area whose state machine parameter is in the "writing" state in the receive circular linked list is taken as the starting address of the readable DMA receive area, and the state machine parameter corresponding to the starting address of the readable DMA receive area is modified to the readable state. The starting address of the DMA receive area whose state machine parameter is in the idle state is selected as the starting address of the DMA receive area in the write process. TLP information is generated based on the starting address of the DMA receive area in the write process and written to the PCIe device write control module. The state machine parameter of the starting address of the DMA receive area in the write process is set to the write process state.
5. The PCIe high time uniformity transmission method based on DMA ring buffer according to claim 4, characterized in that, The PCIe device write control module includes a second BAR space, a PCIe write unit, a third FIFO, a fourth FIFO, and a source port control unit. Between the current interrupt signal and the previous interrupt signal, the source port control unit generates a total message from the data received from the external port according to the data transmission protocol format and stores it in the third FIFO. When the PCIe device write control module receives an interrupt signal, the source port control unit writes the length of the data received from the external port between the current interrupt signal and the previous interrupt signal into the TLP information stored in the second BAR space. The PCIe write unit generates a memory write request (TLP) transaction based on the TLP information. The PCIe bus controller reads the total message in the third FIFO through the memory write request (TLP) transaction. The total message in the third FIFO is transmitted to the PCIe bus controller. Based on the received memory write request (TLP) transaction and the received total message, the PCIe bus controller initiates a DMA transfer operation to the DMA transfer controller. Between the current interrupt signal and the next interrupt signal, the total message generated between the current interrupt signal and the previous interrupt signal is written into the DMA memory corresponding to the starting address of the DMA receive area in the main memory. When the PCIe device write control module receives an interrupt signal, between the current interrupt signal and the next interrupt signal, the source port control unit generates a total message based on the data transmission protocol format from the messages received by the external port and stores it in the fourth FIFO. When the next interrupt signal arrives, the original third FIFO will be used as the new fourth FIFO, and the original fourth FIFO will be used as the new third FIFO.