Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. In this application embodiment, a second common electrode extending along a second direction is added to the array substrate, so that the first common electrode and the second common electrode disposed in different layers intersect and are electrically connected, so as to shorten the recovery time of the common electrode potential in the array substrate and thereby reduce the risk of horizontal crosstalk; at the same time, the first common electrode and the second common electrode are both partially overlapped with the pixel electrode to improve the aperture ratio.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel. Background Technology

[0002] In recent years, as consumers have increasingly demanded higher resolution, higher frame rate, and wider viewing angle LCD monitors, it is necessary to fundamentally solve the problem and improve brand influence and market share in order to meet the high requirements of customers. At the same time, the picture quality is in a dominant position in both the international and domestic markets, which poses a challenge to improving picture quality. Currently, improving horizontal crosstalk in picture quality is quite difficult.

[0003] Horizontal crosstalk refers to the potential change of the common electrode of the array substrate / color filter substrate caused by the rise or fall of the data signal. During the potential recovery time of the common electrode of the array substrate / color filter substrate, the pixel voltage is coupled, resulting in a temporary unstable state, which in turn produces horizontal lines. There are two main factors affecting horizontal crosstalk: the potential fluctuation amplitude of the common electrode and the recovery time.

[0004] In existing mass-produced liquid crystal displays, the presence of a-Si in the 4Mask process results in MIS capacitors in the display, which increases the amplitude of fluctuations and thus exacerbates horizontal crosstalk. Summary of the Invention

[0005] This application provides an array substrate and a display panel that can improve horizontal crosstalk while increasing aperture ratio.

[0006] This application provides an array substrate, including a display area and a non-display area located outside the display area, comprising:

[0007] substrate;

[0008] A first common electrode is disposed on the substrate, extending along a first direction;

[0009] A second common electrode is disposed on the substrate, extending along a second direction. The second common electrode is disposed on a different layer from the first common electrode and is electrically connected to the first common electrode. The second direction intersects the first direction.

[0010] Multiple pixel structures are disposed on the substrate, and each pixel structure includes a pixel electrode and a driving circuit connected to the pixel electrode.

[0011] In the orthographic projection pattern of the array substrate, both the first common electrode and the second common electrode partially overlap with the pixel electrode.

[0012] Optionally, in some embodiments of this application, the pixel electrode includes a first pixel electrode, the first pixel electrode includes a first main electrode, the first main electrode includes a first trunk and a second trunk, the first trunk and the second trunk are intersected, and the second common electrode includes a first segment;

[0013] In the orthographic projection region of the first main electrode, the second main trunk covers the first segment.

[0014] Optionally, in some embodiments of this application, the first pixel electrode further includes a first auxiliary electrode located on one side of the first main electrode, a circuit area is provided between the first main electrode and the first auxiliary electrode, the driving circuit is disposed in the circuit area, and the driving circuit is electrically connected to the first main electrode and the first auxiliary electrode.

[0015] The first auxiliary electrode includes a third main branch and a fourth main branch, which are arranged to cross each other. The second common electrode also includes a second segment and a third segment, the second segment being connected to the first segment and the third segment being connected to the side of the second segment away from the first segment. The second segment is arranged to avoid the driving circuit.

[0016] In the orthographic projection region of the first auxiliary electrode, the fourth main trunk covers the third segment.

[0017] Optionally, in some embodiments of this application, the array substrate includes a peripheral common electrode disposed in the non-display area, the peripheral common electrode extending along the outer periphery of the display area, and the first common electrode and the second common electrode being connected to the peripheral common electrode to form a mesh structure.

[0018] Optionally, in some embodiments of this application, in the overlapping region of the first common electrode and the second common electrode, the second common electrode is connected to the first common electrode through a via.

[0019] Optionally, in some embodiments of this application, each of the driving circuits includes a shared electrode, and the pixel electrode further includes a second pixel electrode disposed adjacent to the first pixel electrode. The driving circuit includes a first driving circuit connected to the first pixel electrode and a second driving circuit connected to the second pixel electrode.

[0020] In the adjacent first driving circuit and second driving circuit, the first driving circuit and the second driving circuit share a common electrode.

[0021] Optionally, in some embodiments of this application, the second pixel electrode includes a second main electrode and a second auxiliary electrode. The second main electrode includes a fifth main branch and a sixth main branch, which are intersected. The second auxiliary electrode includes a seventh main branch and an eighth main branch, which are intersected.

[0022] The shared electrode includes a first part, a second part, and a third part, wherein the first part is connected to one side of the second part, and the third part is connected to the side of the second part away from the first part;

[0023] In the orthographic projection pattern of the second pixel electrode, the fifth main trunk covers the first part, the seventh main trunk covers the third part, and the second part is disposed in the circuit area.

[0024] Optionally, in some embodiments of this application, the shared electrode further includes a fourth part, which is connected to the second part and extends to the circuit area where the first driving circuit is located;

[0025] The first driving circuit is electrically connected to the fourth part.

[0026] Optionally, in some embodiments of this application, the driving circuit further includes a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor, wherein the source of the first thin-film transistor is connected to a data line, the drain of the first thin-film transistor is connected to the auxiliary electrode, the source of the second thin-film transistor is electrically connected to the data line, the drain of the second thin-film transistor is connected to the main electrode, the drain of the second thin-film transistor is connected to the source of the third thin-film transistor, and the drain of the third thin-film transistor is connected to the shared electrode;

[0027] The data line includes a first data line that bypasses the fourth part and is connected to the first driving circuit. The first data line includes a first data line segment, a bent segment, and a second data line segment connected in sequence. The first data line segment and the second data line segment extend along the second direction. The bent segment is located in the circuit area. The first thin-film transistor and the third thin-film transistor of the first driving circuit are located on one side of the bent segment, and the second thin-film transistor of the first driving circuit is located on the other side of the bent segment.

[0028] Optionally, in some embodiments of this application, the bent segment includes a first sub-segment, a second sub-segment, and a third sub-segment that are sequentially adjacent to each other. The first sub-segment and the third sub-segment extend along the first direction, and the second sub-segment extends along the second direction. The first sub-segment is connected to the first data line segment, and the third sub-segment is connected to the second data line segment. The second sub-segment is located in the middle region of the circuit area.

[0029] In the first driving circuit, the first thin-film transistor is connected to one side of the second sub-segment, the second thin-film transistor is connected to the other side of the second sub-segment, the third thin-film transistor is located on the side of the second sub-segment away from the second thin-film transistor, and the fourth part is disposed between the first sub-segment and the third sub-segment and spaced apart from the second sub-segment.

[0030] Accordingly, this application also provides a display panel that includes an array substrate as described in any of the above embodiments.

[0031] In this embodiment, a second common electrode extending along a second direction is added to the array substrate, so that the first common electrode and the second common electrode disposed in different layers intersect and are electrically connected, thereby shortening the recovery time of the common electrode potential in the array substrate and reducing the risk of horizontal crosstalk; at the same time, the first common electrode and the second common electrode are both partially overlapped with the pixel electrode to improve the aperture ratio. Attached Figure Description

[0032] Figure 1 This is a partial structural schematic diagram of the array substrate provided in an embodiment of this application;

[0033] Figure 2 yes Figure 1 Enlarged view of section C;

[0034] Figure 3 yes Figure 1 A schematic diagram of the pixel structure corresponding to the removal of a second pixel electrode;

[0035] Figure 4 yes Figure 3 Enlarged view of section D. Detailed Implementation

[0036] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc., are used only as indications and do not impose numerical requirements or establish a sequence.

[0037] This application provides an array substrate and a display panel, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0038] Please refer to Figure 1 and Figure 3 This application provides an array substrate 100, including a display area AA and a non-display area NA located outside the display area AA. The array substrate 100 includes a substrate 11, a first common electrode 12, a second common electrode 13, and a pixel structure Px.

[0039] A first common electrode 12 extends along a first direction x and is disposed on a substrate 11. A second common electrode 13 extends along a second direction y and is disposed on a substrate 11. The second common electrode 13 is disposed on a different layer from the first common electrode 12. The second common electrode 13 is electrically connected to the first common electrode 12. The second direction y intersects the first direction x.

[0040] Multiple pixel structures Px are disposed on the substrate 11. Each pixel structure Px includes a pixel electrode 14 and a driving circuit 15 connected to the pixel electrode 14.

[0041] Among them, the orthographic projection pattern on the array substrate 100 (such as...) Figure 2 As shown in the figure, the first common electrode 12 and the second common electrode 13 are both partially overlapped with the pixel electrode 14.

[0042] The array substrate 100 of this application embodiment adds a second common electrode 13 extending along the second direction y, so that the first common electrode 12 and the second common electrode 13 disposed in different layers intersect and are electrically connected, thereby accelerating the signal transmission rate and shortening the recovery time of the common electrode potential in the array substrate 100, thereby reducing the risk of horizontal crosstalk; at the same time, the first common electrode 12 and the second common electrode 13 are both partially overlapped with the pixel electrode 14 to improve the aperture ratio.

[0043] It should be noted that the first common electrode 12 and the second common electrode 13 are disposed in different layers, that is, an insulating layer is disposed between the first common electrode 12 and the second common electrode 13. For example, the first common electrode 12 is disposed on the substrate 11, the insulating layer covers the first common electrode 12 and the substrate 11, and the second common electrode 13 is disposed on the side of the insulating layer away from the substrate.

[0044] The first common electrode 12 and the second common electrode 13 are both partially overlapped with the pixel electrode 14 to form a capacitor.

[0045] Optionally, the first direction x is perpendicular to the second direction y. In some embodiments, the angle between the first direction x and the second direction y is an acute angle.

[0046] In addition, some signal components in the driving circuit 15 are disposed on the same layer as the first common electrode 12, such as the gate of the thin film transistor; some signal components are disposed on the same layer as the second common electrode 13, such as the source, drain and common electrode 151 of the thin film transistor.

[0047] A driving circuit 15 further includes a first thin-film transistor t1, a second thin-film transistor t2, and a third thin-film transistor t3. The source of the first thin-film transistor t1 is connected to a data line data, and the drain of the first thin-film transistor t1 is connected to an auxiliary electrode (first auxiliary electrode 142 or second auxiliary electrode 144). The source of the second thin-film transistor t2 is electrically connected to the data line data, and the drain of the second thin-film transistor t2 is connected to a main electrode (first main electrode 141 or second main electrode 143). The drain of the second thin-film transistor t2 is connected to the source of the third thin-film transistor t3, and the drain of the third thin-film transistor t3 is connected to a shared electrode 151.

[0048] It should be explained that "a feature extends along a certain direction" means that the extension trend of the feature extends along that direction. Therefore, "a feature extends along a certain direction" includes, but is not limited to, the extension trajectory of the feature being a straight line, a wavy line, or a broken line.

[0049] Optionally, the pixel electrode 14 can be made of oxides such as indium tin oxide or indium zinc oxide.

[0050] Optional, please refer to Figure 2 and Figure 3 Pixel electrode 14 includes a first pixel electrode 14a. First pixel electrode 14a includes a first main electrode 141. First main electrode 141 includes a first main branch 1411 and a second main branch 1412. First main branch 1411 and second main branch 1412 are intersected. Second common electrode 13 includes a first segment 131.

[0051] In the orthographic projection region of the first main electrode 141, the second main trunk 1412 covers the first segment 131.

[0052] In this embodiment, the first segment 131 of the second common electrode 13 overlaps with the second main branch 1412 of the first pixel electrode 14a to improve the aperture ratio.

[0053] Optionally, the first main electrode 1411 extends along a first direction x, and the second main electrode 1412 extends along a second direction y. The first main electrode 141 also includes a plurality of first branch electrodes, some of which are connected to the first main electrode 1411, and others of which are connected to the second main electrode 1412. The first branch electrodes are distributed in four domain regions of the first main electrode 141.

[0054] Optionally, the first pixel electrode 14a further includes a first auxiliary electrode 142 located on one side of the first main electrode 141. A circuit region dl is disposed between the first main electrode 141 and the first auxiliary electrode 142. A driving circuit 15 is disposed in the circuit region dl. A driving circuit 15 is electrically connected to the first main electrode 141 and the first auxiliary electrode 142.

[0055] The first auxiliary electrode 142 includes a third main branch 1421 and a fourth main branch 1422. The third main branch 1421 and the fourth main branch 1422 are arranged intersectingly. The second common electrode 13 also includes a second segment 132 and a third segment 133. The second segment 132 is connected to the first segment 131, and the third segment 133 is connected to the side of the second segment 132 away from the first segment 131. The second segment 132 is positioned away from the drive circuit 15.

[0056] In the orthographic projection region of the first auxiliary electrode 142, the fourth main trunk 1422 covers the third segment 133.

[0057] In this embodiment, the third segment 133 of the second common electrode 13 overlaps with the fourth main branch 1422 of the first auxiliary electrode 142 to improve the opening ratio.

[0058] Optionally, the third main branch 1421 extends along the first direction x, and the fourth main branch 1422 extends along the second direction y. Optionally, the first auxiliary electrode 142 also includes a plurality of second branch electrodes, some of which are connected to the third main branch 1421, and other portions of which are connected to the fourth main branch 1422. The second branch electrodes are distributed in the four domain regions of the first auxiliary electrode 142.

[0059] In this embodiment, the pixel electrode 14 is an 8-domain pixel electrode. In some embodiments, the pixel electrode 14 may also be a 4-domain pixel electrode or a 2-domain pixel electrode, that is, the pixel electrode 14 includes a first main branch 1411 and a second main branch 1412 that are arranged in a cross configuration, wherein the second main branch 1412 and the first segment 131 of the second common electrode 13 are overlapped.

[0060] Optionally, the first common electrode 12 further includes a vertical portion 121 extending along the second direction y. In the region of the first pixel electrode 14a, the vertical portion 121 of one first common electrode 12 overlaps with the second main branch 1412, and the vertical portion of another first common electrode 12 overlaps with the fourth main branch 1422.

[0061] The width of the vertical portion 121 is greater than the width of the second main branch 1412 and the fourth main branch 1422.

[0062] Optionally, the array substrate 100 includes a peripheral common electrode 16 disposed in the non-display area NA. The peripheral common electrode 16 extends along the outer periphery of the display area AA. The first common electrode 12 and the second common electrode 13 are both connected to the peripheral common electrode 16 to form a mesh structure.

[0063] In this embodiment, the common electrode of the array substrate 100 is formed into a grid structure, which makes the transmission of the common electrode signal faster, thereby further accelerating the recovery of the common electrode potential and shortening the recovery time of the common electrode potential, thereby reducing the risk of horizontal crosstalk.

[0064] Optionally, in the overlapping region of the first common electrode 12 and the second common electrode 13, the second common electrode 13 is connected to the first common electrode 12 via a via. This arrangement increases the number of nodes connecting the first common electrode 12 and the second common electrode 13, thereby increasing the signal transmission paths of the entire common electrode grid and shortening the recovery time of the common electrode potential.

[0065] Optionally, each driving circuit 15 includes a shared electrode 151. The pixel electrode 14 also includes a second pixel electrode 14b disposed adjacent to the first pixel electrode 14a. The driving circuit 15 includes a first driving circuit 15a connected to the first pixel electrode 14a and a second driving circuit 15b connected to the second pixel electrode 14b.

[0066] In the adjacent first driving circuit 15a and second driving circuit 15b, the first driving circuit 15a and the second driving circuit 15b share a common electrode 151.

[0067] In this embodiment, the first driving circuit 15a and the second driving circuit 15b share a common electrode 151, thereby freeing up space for the second common electrode 13, which improves the aperture ratio. Specifically, the common electrode 151 is located in the region of the second pixel electrode 14b and partially extends into the region of the first pixel electrode 14a, while the second common electrode 13 is located in the first pixel electrode 14a.

[0068] It should be noted that blue, red, and green pixel structures form a pixel unit.

[0069] Optionally, in a pixel unit, the first pixel electrode 14a is a blue pixel electrode, and the second pixel electrode 14b includes a red pixel electrode and a green pixel electrode. One of the red pixel electrode and the green pixel electrode shares a common electrode 151 with the driving circuit 15 corresponding to the blue pixel electrode. That is, a pixel unit has two common electrodes 151 and one second common electrode 13.

[0070] In some embodiments, in two pixel units, adjacent pixel structures share a common electrode 151, that is, two pixel units have three common electrodes 151 and three second common electrodes 13. This arrangement increases the number of second common electrodes 13, thereby improving the recovery time of the common electrode potential.

[0071] Optionally, the second pixel electrode 14b includes a second main electrode 143 and a second auxiliary electrode 144. The second main electrode 143 includes a fifth main electrode 1431 and a sixth main electrode 1432. The fifth main electrode 1431 and the sixth main electrode 1432 are arranged intersectingly. The second auxiliary electrode 144 includes a seventh main electrode 1441 and an eighth main electrode 1442. The seventh main electrode 1441 and the eighth main electrode 1442 are arranged intersectingly.

[0072] The shared electrode 151 includes a first part 1511, a second part 1512, and a third part 1513. The first part 1511 is connected to one side of the second part 1512. The third part 1513 is connected to the side of the second part 1512 away from the first part 1511.

[0073] In the orthographic projection pattern of the second pixel electrode 14b, the fifth main branch 1431 covers the first part 1511, the seventh main branch 1441 covers the third part 1513, and the second part 1512 is disposed in the circuit area dl.

[0074] In this embodiment, the first part 1511 and the third part 1513 of the shared electrode 151 are respectively overlapped with the second pixel electrode 14b to improve the aperture ratio.

[0075] Optionally, the fifth main trunk 1431 and the seventh main trunk 1441 are arranged to extend along the first direction x, and the sixth main trunk 1432 and the eighth main trunk 1442 are arranged to extend along the second direction y.

[0076] Optionally, the second main electrode 143 further includes a plurality of third branch electrodes, some of which are connected to the fifth main trunk 1431, and others of which are connected to the sixth main trunk 1432. The third branch electrodes are distributed in four domain regions of the second main electrode 143. The second auxiliary electrode 144 further includes a plurality of fourth branch electrodes, some of which are connected to the seventh main trunk 1441, and others of which are connected to the eighth main trunk 1442. The fourth branch electrodes are distributed in four domain regions of the second auxiliary electrode 144.

[0077] Optionally, the shared electrode 151 also includes a fourth part 1514, which is connected to the second part 1512 and extends to the circuit area dl where the first drive circuit 15a is located.

[0078] The first drive circuit 15a is electrically connected to the fourth part 1514.

[0079] Optionally, the fourth part 1514 extends along the first direction x to the circuit area dl of the first drive circuit 15a.

[0080] Optional, please refer to Figure 3 and Figure 4 In the first driving circuit 15a, the source of the first thin-film transistor t1 is connected to a data line data, and the drain of the first thin-film transistor t1 is connected to the first auxiliary electrode 142. The source of the second thin-film transistor t2 is connected to the data line data, the drain of the second thin-film transistor t2 is connected to the first main electrode 141, the drain of the second thin-film transistor t2 is connected to the source of the third thin-film transistor t3, and the drain of the third thin-film transistor t3 is connected to the shared electrode 151.

[0081] The data line includes a first data line d1, which bypasses the fourth part 1514. The first data line d1 is connected to the first driving circuit 15a. The first data line d1 includes a first data line segment d11, a bent segment d12, and a second data line segment d13 connected in sequence. The first data line segment d11 and the second data line segment d13 extend along the second direction y. The bent segment d12 is located in the circuit area d1. The first thin-film transistor t1 and the third thin-film transistor t3 of the first driving circuit 15a are located on one side of the bent segment d12, and the second thin-film transistor t2 of the first driving circuit 15a is located on the other side of the bent segment d12.

[0082] In this embodiment, the bending segment d12 is used to avoid the fourth part 1514, thus preventing a short circuit between the two. The first thin-film transistor t1, the third thin-film transistor t3, and the second thin-film transistor t2 are respectively located on both sides of the bending segment d12, saving layout space and increasing the aperture ratio.

[0083] The bent segment d12 can be of any shape, as long as it does not short-circuit with the drive circuit 15 or cause the drive circuit 15 to malfunction.

[0084] Optionally, in this embodiment, the bent segment d12 includes a first sub-segment d121, a second sub-segment d122, and a third sub-segment d123 that are sequentially adjacent. The first sub-segment d121 and the third sub-segment d123 extend along a first direction x, and the second sub-segment d122 extends along a second direction y. The first sub-segment d121 is connected to the first data line segment d11, and the third sub-segment d123 is connected to the second data line segment d13. The second sub-segment d122 is located in the middle region of the circuit area d1.

[0085] In the first driving circuit 15a, the first thin-film transistor t1 is connected to one side of the second sub-segment d122, and the second thin-film transistor t2 is connected to the other side of the second sub-segment d122. The third thin-film transistor t3 is located on the side of the second sub-segment d122 away from the second thin-film transistor t2, and the fourth part 1514 is disposed between the first sub-segment d121 and the third sub-segment d123 and spaced apart from the second sub-segment d122.

[0086] The data line also includes a second data line d2, which is connected to the second drive circuit 15b.

[0087] In addition, the method for fabricating the array substrate 100 in this embodiment is to form a first metal layer on the substrate 11. The first metal layer includes a first common electrode 12, a scan line (scan), and a gate of a thin-film transistor. The gate of the thin-film transistor is connected to the scan line (scan).

[0088] The scan line extends along the first direction x, and the data line extends along the second direction y.

[0089] A first insulating layer is formed on the first metal layer. A second metal layer is formed on the first insulating layer. The second metal layer includes a data line, the source and drain of a thin-film transistor, a shared electrode 151, and a second common electrode 13.

[0090] A second insulating layer is formed on the second metal layer. A pixel electrode layer is formed on the second insulating layer, the pixel electrode layer including a pixel electrode 14 and a masking electrode 17. The masking electrode 17 masks the data line, wherein when the array substrate 100 is engaged with the color filter substrate, the potential of the masking electrode 17 and the common electrode on the color filter substrate are the same, the liquid crystal in this area is not deflected, thereby replacing the black matrix in this area.

[0091] The peripheral common electrode 16 can be formed in the first metal layer or the second metal layer, or it can be partially in the first metal layer and partially in the second metal layer.

[0092] Optionally, the first metal and the second metal may be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co), an alloy with any of the above metal elements as components, or an alloy combining any of the above metal elements. Furthermore, the first metal and the second metal may have a single-layer structure or a stacked structure of two or more layers.

[0093] Accordingly, this application also provides a display panel that includes the array substrate 100 as described in any of the above embodiments. That is, the structure of the array substrate of the display panel in this embodiment is similar to or the same as the structure of the array substrate 100 in the above embodiments.

[0094] Optionally, the display panel may also include a color filter substrate and a liquid crystal, wherein the liquid crystal is disposed between the array substrate 100 and the color filter substrate.

[0095] The display panel of this application embodiment adopts a second common electrode extending along a second direction in the array substrate, so that the first common electrode and the second common electrode disposed in different layers intersect and are electrically connected, so as to shorten the recovery time of the common electrode potential in the array substrate and thereby reduce the risk of horizontal crosstalk; at the same time, the first common electrode and the second common electrode are both partially overlapped with the pixel electrode to improve the aperture ratio.

[0096] The above provides a detailed description of an array substrate and display panel provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An array substrate, comprising a display area and a non-display area located outside the display area, characterized in that, include: substrate; A first common electrode is disposed on the substrate, extending along a first direction; A second common electrode is disposed on the substrate, extending along a second direction. The second common electrode is disposed on a different layer from the first common electrode and is electrically connected to the first common electrode. The second direction intersects the first direction. Multiple pixel structures are disposed on the substrate. Each pixel structure includes a pixel electrode and a driving circuit connected to the pixel electrode. The driving circuit includes a third thin-film transistor and a shared electrode. The drain of the third thin-film transistor is connected to the shared electrode. The drain of the third thin-film transistor is disposed on a different layer from the first common electrode. In the orthographic projection pattern of the array substrate, both the first common electrode and the second common electrode are partially overlapped with the pixel electrode. The first common electrode further includes a vertical portion extending along the second direction, and the second common electrode includes a first segment extending along the second direction. The width of the vertical portion is greater than the width of the first segment, and the vertical portion and the first segment overlap in the orthographic projection pattern of the array substrate.

2. The array substrate according to claim 1, characterized in that, The pixel electrode includes a first pixel electrode, the first pixel electrode includes a first main electrode, the first main electrode includes a first main branch and a second main branch, and the first main branch and the second main branch are arranged in an intersecting manner. In the orthographic projection region of the first main electrode, the second main trunk covers the first segment.

3. The array substrate according to claim 2, characterized in that, The first pixel electrode also includes a first auxiliary electrode located on one side of the first main electrode. A circuit area is provided between the first main electrode and the first auxiliary electrode. The driving circuit is disposed in the circuit area and is electrically connected to the first main electrode and the first auxiliary electrode. The first auxiliary electrode includes a third main branch and a fourth main branch, which are arranged to cross each other. The second common electrode also includes a second segment and a third segment, the second segment being connected to the first segment and the third segment being connected to the side of the second segment away from the first segment. The second segment is arranged to avoid the driving circuit. In the orthographic projection region of the first auxiliary electrode, the fourth main trunk covers the third segment.

4. The array substrate according to claim 3, characterized in that, The array substrate includes a peripheral common electrode disposed in the non-display area. The peripheral common electrode extends along the outer periphery of the display area. The first common electrode and the second common electrode are both connected to the peripheral common electrode to form a grid structure.

5. The array substrate according to claim 3 or 4, characterized in that, Each of the driving circuits includes a shared electrode, and the pixel electrode further includes a second pixel electrode disposed adjacent to the first pixel electrode. The driving circuit includes a first driving circuit connected to the first pixel electrode and a second driving circuit connected to the second pixel electrode. In the adjacent first driving circuit and second driving circuit, the first driving circuit and the second driving circuit share a common electrode.

6. The array substrate according to claim 5, characterized in that, The second pixel electrode includes a second main electrode and a second auxiliary electrode. The second main electrode includes a fifth main branch and a sixth main branch, which are arranged intersectingly. The second auxiliary electrode includes a seventh main branch and an eighth main branch, which are arranged intersectingly. The shared electrode includes a first part, a second part, and a third part, wherein the first part is connected to one side of the second part, and the third part is connected to the side of the second part away from the first part; In the orthographic projection pattern of the second pixel electrode, the fifth main trunk covers the first part, the seventh main trunk covers the third part, and the second part is disposed in the circuit area.

7. The array substrate according to claim 6, characterized in that, The shared electrode further includes a fourth part, which is connected to the second part and extends into the circuit area where the first driving circuit is located; The first driving circuit is electrically connected to the fourth part.

8. The array substrate according to claim 7, characterized in that, The first driving circuit further includes a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor. The source of the first thin-film transistor is connected to a data line, the drain of the first thin-film transistor is connected to the first auxiliary electrode, the source of the second thin-film transistor is electrically connected to the data line, the drain of the second thin-film transistor is connected to the first main electrode, the drain of the second thin-film transistor is connected to the source of the third thin-film transistor, and the drain of the third thin-film transistor is connected to the shared electrode. The data line includes a first data line that bypasses the fourth part and is connected to the first driving circuit. The first data line includes a first data line segment, a bent segment, and a second data line segment connected in sequence. The first data line segment and the second data line segment extend along the second direction. The bent segment is located in the circuit area. The first thin-film transistor and the third thin-film transistor of the first driving circuit are located on one side of the bent segment, and the second thin-film transistor of the first driving circuit is located on the other side of the bent segment.

9. The array substrate according to claim 8, characterized in that, The bent segment includes a first sub-segment, a second sub-segment, and a third sub-segment that are sequentially adjacent to each other. The first sub-segment and the third sub-segment extend along the first direction, and the second sub-segment extends along the second direction. The first sub-segment is connected to the first data line segment, and the third sub-segment is connected to the second data line segment. The second sub-segment is located in the middle region of the circuit area. In the first driving circuit, the first thin-film transistor is connected to one side of the second sub-segment, the second thin-film transistor is connected to the other side of the second sub-segment, the third thin-film transistor is located on the side of the second sub-segment away from the second thin-film transistor, and the fourth part is disposed between the first sub-segment and the third sub-segment and spaced apart from the second sub-segment.

10. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

Images