Data management method, method for checking data and related devices

Abstract

The embodiment of the application relates to the application field of storage devices, and discloses a data management method, a method for checking data and related devices, the data management method comprising: establishing a second memory mapping relationship between a host system and each flash memory device; storing a plurality of data blocks corresponding to strip data to a plurality of flash memory devices, wherein each flash memory device has a first memory mapping relationship with other flash memory devices; determining a target flash memory device as a computing engine; sending a checking command to the target flash memory device, so that the target flash memory device performs data calculation on the plurality of data blocks based on the second memory mapping relationship, to generate and store checking data. The checking data in the application can be calculated by the flash memory device, and a special RAID controller is not needed to calculate the checking data, so that the transmission process of the checking data between the RAID controller and the storage device can be reduced, and the bandwidth requirement of the redundant array of independent disks system is reduced.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a data management method, a data verification method, and related apparatus. Background Technology

[0002] Redundant Arrays of Inexpensive Disks (RAID) is a storage array composed of multiple storage devices that can operate simultaneously. RAID technology can improve the read and write performance of a storage array or provide data redundancy protection.

[0003] Currently, RAID systems typically consist of a processor system, a memory system, a communication bus, a RAID controller, and a storage array. In developing this application, the inventors discovered at least the following problems in the prior art:

[0004] When generating parity data, the RAID controller needs to receive all relevant data from the stripe, perform calculations, and then store the resulting parity data in a storage device within the storage array. When recovering data from a specific stripe, the RAID controller needs to read the other data from the stripe, along with the parity data, to perform the recovery operation. Therefore, the RAID controller requires two sets of high-speed Peripheral Component Interconnect Express (PCIe) buses: one between the RAID controller and the host, and another between the RAID controller and the storage device. However, this architecture requires the RAID controller to have high bandwidth to meet performance requirements, which is currently difficult to achieve at high performance levels. Furthermore, using a standalone RAID controller, especially a hardware one, incurs high costs, while a software one offers performance limitations. Summary of the Invention

[0005] This application provides a data management method, a data verification method, and related apparatus to reduce the transmission process of verification data between the RAID controller and the storage device, thereby reducing the bandwidth requirements of the independent disk redundant array system.

[0006] The embodiments of this application provide the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a data management method applied to a host system, wherein the host system is communicatively connected to multiple flash memory devices, and each flash memory device has a first memory mapping relationship with other flash memory devices;

[0008] Data management methods include:

[0009] Establish a second memory mapping relationship between the host system and each flash memory device;

[0010] The striped data is stored in several data blocks corresponding to several flash memory devices, with each data block corresponding to one flash memory device.

[0011] Identify the target flash memory device as the computing engine;

[0012] A verification command is sent to the target flash memory device so that the target flash memory device performs data calculations on several data blocks based on a second memory mapping relationship to generate and store verification data.

[0013] Secondly, embodiments of this application provide a host system that applies the data management method of the first aspect. The host system includes:

[0014] The processor system, connected to the host memory system, is used to divide a strip of data into several data blocks and transfer the data blocks to the host memory system;

[0015] The host memory system, connected to the processor system, is used to store data blocks.

[0016] Thirdly, embodiments of this application provide a method for verifying data, applied to a storage array. The storage array includes multiple flash memory devices, each flash memory device having a first memory mapping relationship with other flash memory devices, each flash memory device being communicatively connected to a host system, and each flash memory device having a second memory mapping relationship with the host system.

[0017] Methods for validating data include:

[0018] Based on the verification command sent by the host system and the second memory mapping relationship, data calculations are performed on several data blocks to generate and store verification data. The verification data is directly stored in the flash memory medium by the target flash memory device, and the verification command and data blocks are obtained by the data management method of the first aspect.

[0019] Fourthly, embodiments of this application provide a storage array that applies the method for verifying data as described in the third aspect, the storage array comprising multiple flash memory devices;

[0020] Each flash memory device includes:

[0021] Independent disk redundant array engine;

[0022] At least one flash memory medium is communicatively connected to an independent redundant disk array engine.

[0023] Fifthly, embodiments of this application provide a distributed independent disk redundancy array system, comprising:

[0024] Such as the host system in the second aspect;

[0025] For example, in the fourth aspect, the storage array, the host system is connected to the storage array via a communication bus.

[0026] In a sixth aspect, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions, which enable a host system to execute the data management method of the first aspect, or enable a storage array to execute the method for verifying data of the third aspect.

[0027] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a data management method applied to a host system. The host system is communicatively connected to multiple flash memory devices, wherein each flash memory device has a first memory mapping relationship with the other flash memory devices. The data management method includes: establishing a second memory mapping relationship between the host system and each flash memory device; storing several data blocks corresponding to striped data to several flash memory devices, wherein each data block corresponds one-to-one with one flash memory device; determining a target flash memory device as the computing engine; and sending a verification command to the target flash memory device, so that the target flash memory device performs data calculations on the several data blocks based on the second memory mapping relationship to generate and store verification data.

[0028] The host system stores several data blocks corresponding to the striped data to different flash memory devices and sends a verification command to the target flash memory device so that the target flash memory device can perform data calculation on several data blocks based on the second memory mapping relationship. The verification data in this application can be calculated by the flash memory device, without the need for a dedicated RAID controller to calculate the verification data. This can reduce the transmission process of verification data between the RAID controller and the storage device and reduce the bandwidth requirements of the independent disk redundant array system. Attached Figure Description

[0029] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0030] Figure 1 This is a schematic diagram of the structure of an independent disk redundant array system provided in an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of the structure of a first storage array provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the data distribution at different stages of an independent disk redundant array system provided in an embodiment of this application;

[0034] Figure 5 This is a schematic diagram illustrating the writing of data in a redundant array system with independent disks provided in an embodiment of this application;

[0035] Figure 6 This is a schematic diagram illustrating data recovery from an independent disk redundant array system provided in an embodiment of this application;

[0036] Figure 7 This is a flowchart illustrating a data management method provided in an embodiment of this application;

[0037] Figure 8 This is a schematic diagram illustrating the mapping relationship between the read / write storage buffer and the read / write storage buffer mapping area of ​​a flash memory device provided in an embodiment of this application;

[0038] Figure 9 This is a schematic diagram illustrating the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​a flash memory device, provided in an embodiment of this application.

[0039] Figure 10 This is a schematic diagram of a host system updating at least one data block according to an embodiment of this application;

[0040] Figure 11 This is a schematic diagram of a host system data recovery process provided in an embodiment of this application;

[0041] Figure 12 This is a flowchart illustrating a method for verifying data provided in an embodiment of this application;

[0042] Figure 13 This is a schematic diagram illustrating the writing of verification data to a target flash memory device according to an embodiment of this application;

[0043] Figure 14 This is a schematic diagram illustrating the writing of verification data to another target flash memory device according to an embodiment of this application;

[0044] Figure 15 This is a schematic diagram of a process for updating verification data in a target flash memory device according to an embodiment of this application;

[0045] Figure 16 This is a schematic diagram illustrating the updating of verification data for a target flash memory device according to an embodiment of this application;

[0046] Figure 17 This is a schematic diagram illustrating the process of a target flash memory device recovering data from damaged data blocks, provided in an embodiment of this application.

[0047] Figure 18 This is a schematic diagram illustrating how a target flash memory device recovers data from damaged data blocks, as provided in an embodiment of this application.

[0048] Figure 19 This is a schematic diagram of a distributed independent disk redundancy array system provided in an embodiment of this application;

[0049] Figure 20 This is a schematic diagram of the structure of a host system provided in an embodiment of this application;

[0050] Figure 21 This is a schematic diagram of the structure of a second storage array provided in an embodiment of this application;

[0051] Figure 22 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0052] Figure 23 This is a schematic diagram of the specific structure of a distributed independent disk redundant array system provided in an embodiment of this application;

[0053] Figure 24 This is a schematic diagram of data distribution at different stages of a distributed independent disk redundant array system provided in an embodiment of this application;

[0054] Figure 25 This is a schematic diagram illustrating the data writing process of a distributed independent disk redundant array system provided in an embodiment of this application;

[0055] Figure 26 This is a schematic diagram illustrating the data update process of a distributed independent disk redundant array system provided in an embodiment of this application;

[0056] Figure 27 This is a schematic diagram of the data recovery process of a distributed independent disk redundant array system provided in an embodiment of this application.

[0057] Explanation of icon numbers:

[0058]

[0059] Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0062] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0063] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an independent disk redundant array system provided in an embodiment of this application;

[0064] like Figure 1 As shown, the independent disk redundant array system 100 includes a processor system 101, a memory system 102, a system communication bus 103, a RAID controller 104, and a first storage array 105. The RAID controller 104 includes a RAID engine 1041 and an internal communication bus 1042.

[0065] The processor system 101 is used to send commands to the RAID controller 104 to enable the RAID controller 104 to perform data verification or data recovery; the memory system 102 is used to store data blocks to be sent to the RAID controller 104. The processor system 101 includes a central processing unit (CPU), and the memory system 102 includes double data rate synchronous dynamic random access memory (DDR SDRAM).

[0066] The processor system 101 and the memory system 102 constitute the host (not shown). The host communicates with the RAID controller 104 through the system communication bus 103, which is a high-speed serial computer expansion (Peripheral Component Interconnect Express, PCIe) bus. The system communication bus 103 includes an RC module or a Switch module.

[0067] The RAID controller 104 is specifically used to verify the data sent by the host, generate verification data, and transmit the verification data along with several data packets sent by the host to the first storage array 105. The RAID controller 104 can be a hardware structure or a software structure. The RAID engine 1041 is used to verify the data sent by the host and generate verification data. The RAID controller 104 communicates with the first storage array 105 through an internal communication bus 1042, which is a PCIe bus and includes an RC module or a Switch module.

[0068] In other words, the RAID controller 104 is similar to a bridge chip. The data sent by the host will generate the required data through the RAID controller 104, and the data sent by the host will also be transmitted to the first storage array 105 through the RAID controller 104.

[0069] The first storage array 105 is a Redundant Array of Inexpensive Disks (RAID) used to store data transmitted by the RAID controller 104.

[0070] RAID technology uses multiple storage devices grouped together to form a storage array. Multiple storage devices working simultaneously can improve the read / write performance of the storage array or provide data redundancy protection. RAID technology mainly includes three operations: mirroring, striping, and error correction. Mirroring copies data multiple times and saves it to different storage devices; striping divides continuous data into segments and saves them separately on different devices; error correction performs calculations on the data to calculate redundant protection data, generally called parity data, so that errors can be detected and corrected when they occur.

[0071] For details, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a first storage array provided in an embodiment of this application;

[0072] In this embodiment of the application, the structure of the first storage array is described using a disk array in RAID-5 mode as an example.

[0073] like Figure 2As shown, the first storage array 105 includes a first storage device, a second storage device, a third storage device, and a fourth storage device, wherein the first, second, third, and fourth storage devices have identical structures. The first storage device stores data blocks A1, B1, C1, and parity data Dp; the second storage device stores data blocks A2, B2, Cp, and D1; the third storage device stores data blocks A3, Bp, C2, and D2; and the fourth storage device stores parity data Ap, B3, C3, and D3.

[0074] Stripe 1 includes data blocks A1, A2, and A3, with Ap being the parity data for stripe 1; stripe 2 includes data blocks B1, B2, and B3, with Bp being the parity data for stripe 2; stripe 3 includes data blocks C1, C2, and C3, with Cp being the parity data for stripe 3; stripe 4 includes data blocks D1, D2, and D3, with Dp being the parity data for stripe 4.

[0075] In this embodiment, the storage device in the first storage array 105 can be a magnetic tape, a hard disk, a flash memory device, etc. The specific structure of the storage device is described below using a flash memory device as an example; for example, a solid-state drive (SSD).

[0076] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0077] like Figure 3 As shown, the flash memory device 300 includes a connector 301, a storage control chip 302, other peripheral units 303, a cache unit 304, and a flash memory medium 305.

[0078] The connector 301 connects the storage control chip 302 to the host for communication. The host may be a computer or server. Alternatively, the connector 301 connects the storage control chip 302 to the RAID controller 104 for communication. The storage control chip 302 connects the connector 301, other peripheral units 303, cache unit 304, and flash memory medium 305. It serves as a control and processing unit to manage the internal system of the flash memory device. The storage control chip 302 includes, but is not limited to, a solid-state drive controller. The peripheral units 303 connect to the storage control chip 302 and include components such as serial ports, sensors, registers, and power chips. The cache unit 304 connects to the storage control chip 302 and serves as a cache and algorithm table storage unit. The cache unit 304 is generally a dynamic random access memory (DRAM).

[0079] The flash memory medium 305, serving as the storage medium of the flash memory device 300, is also known as flash memory, Flash, Flash storage, or Flash chip. It acts as a storage unit for storing user data, system data, etc. Multiple channels connect the storage controller chip 302 and the flash memory medium 305, with each channel independently connected to one flash memory medium. For example, channel 0 connects to one flash memory medium, channel 1 connects to one flash memory medium, and so on, up to channel x. A key characteristic of the flash memory medium 305 is that it must be erased before writing, and each flash memory has a limited number of erase cycles.

[0080] Please combine Figure 1 See Figure 4 , Figure 4 This is a schematic diagram of the data distribution at different stages of an independent disk redundant array system provided in an embodiment of this application;

[0081] In this embodiment, during the writing process, data is first divided into several data blocks. For example, data block A is divided into data blocks A1, A2, and A3; data block B is divided into data blocks B1, B2, and B3; data block C is divided into data blocks C1, C2, and C3; and data block D is divided into data blocks D1, D2, and D3. The divided data blocks are first stored in the memory system 102 and then ultimately stored in different storage devices.

[0082] like Figure 4 As shown, the memory system 102 stores data blocks A1, A2, A3, B1, B2, B3, C1, C2, C3, D1, D2, and D3.

[0083] The RAID engine 1041 obtains several data blocks stored in the memory system 102 through the system communication bus 103 and performs data verification to obtain verification data. For example, the RAID engine 1041 performs data verification on data blocks A1, A2, and A3 to obtain verification data Ap; the RAID engine 1041 performs data verification on data blocks B1, B2, and B3 to obtain verification data Bp; the RAID engine 1041 performs data verification on data blocks C1, C2, and C3 to obtain verification data Cp; and the RAID engine 1041 performs data verification on data blocks D1, D2, and D3 to obtain verification data Dp.

[0084] The RAID engine 1041 stores each data block and parity data to different storage devices via the internal communication bus 1042. For example: storing parity data Dp to the first storage device, data block D1 to the second storage device, data block D2 to the third storage device, and data block D3 to the fourth storage device; storing data block C1 to the first storage device, parity data Cp to the second storage device, data block C2 to the third storage device, and data block C3 to the fourth storage device; storing data block B1 to the first storage device, data block B2 to the second storage device, parity data Bp to the third storage device, and data block B3 to the fourth storage device; storing data block A1 to the first storage device, data block A2 to the second storage device, data block A3 to the third storage device, and parity data Ap to the fourth storage device.

[0085] Understandably, during the data reading process, the data read from the first storage array 105 needs to go through the RAID controller 104 before it can be transmitted to the memory system 102.

[0086] Please see Figure 5 , Figure 5 This is a schematic diagram illustrating the writing of data in a redundant array system with independent disks provided in an embodiment of this application;

[0087] The following explanation uses the independent disk redundant array system 100 writing data block A as an example. Data block A is divided into data block A1, data block A2 and data block A3. Data block A1, data block A2 and data block A3 are first stored in memory system 102 and finally stored in different storage devices.

[0088] like Figure 5 As shown, the memory system 102 stores data blocks A1, A2, and A3. The RAID controller 104 receives all the data in the memory system 102, verifies the data of data blocks A1, A2, and A3 to obtain verification data Ap, and forwards data blocks A1, A2, and A3 to the first storage device, the second storage device, and the third storage device, respectively, and writes the verification data Ap to the fourth storage device.

[0089] Please see Figure 6 , Figure 6 This is a schematic diagram illustrating data recovery from an independent disk redundant array system provided in an embodiment of this application;

[0090] like Figure 6As shown, when data block A1 stored in the first storage device is damaged and the independent disk redundant array system 100 needs to recover data block A1, the RAID controller 104 reads data block A2, data block A3 and parity data Ap from the first storage array 105, recovers data block A1 according to data block A2, data block A3 and parity data Ap, and then transmits the recovered data block A1 to the memory system 102.

[0091] In the above process, the RAID controller 104, acting as a bridge, needs to receive all relevant data: when generating parity data, the RAID controller 104 needs to receive all relevant data from the stripe, perform calculations, and then store the resulting parity data into a storage device in the first storage array 105; when recovering data from a specific stripe, the RAID controller 104 needs to read other data from the stripe and the parity data to perform the recovery operation. Therefore, the RAID controller 104 needs to have two sets of PCIe buses, one between the RAID controller 104 and the host, and another between the RAID controller 104 and the storage device. However, this architecture requires the RAID controller 104 to have high bandwidth to meet performance requirements. Furthermore, using a hardware RAID controller for a standalone RAID controller 104 would incur higher costs, while using a software RAID controller would further limit performance.

[0092] Example 1

[0093] To reduce the transmission of verification data between the RAID controller and storage devices and lower the bandwidth requirements of a redundant array of independent disks, this application provides a data management method. The host system stores several data blocks corresponding to striped data on different flash memory devices and sends a verification command to the target flash memory device. This allows the target flash memory device to perform data calculations on the several data blocks based on a second memory mapping relationship, thereby enabling the flash memory device to calculate the verification data. This eliminates the need for a dedicated RAID controller, reducing the transmission of verification data between the RAID controller and storage devices and lowering the bandwidth requirements of the redundant array of independent disks.

[0094] Please see Figure 7 , Figure 7 This is a flowchart illustrating a data management method provided in an embodiment of this application;

[0095] This data management method is applied to a host system, specifically to at least one processor within the host system. The host system is communicatively connected to multiple flash memory devices, each of which has a first memory mapping relationship with the other flash memory devices.

[0096] Specifically, each flash memory device includes a read / write storage buffer and a read / write storage buffer mapping area. The first memory mapping relationship includes the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffers of other flash memory devices. The read / write storage buffer is used to store data blocks read from the flash memory medium, and the read / write storage buffer mapping area is used to store data blocks from other flash memory devices. Flash memory devices include, but are not limited to, non-volatile memory express solid state drives (NVMe SSDs).

[0097] Please see Figure 8 , Figure 8 This is a schematic diagram illustrating the mapping relationship between the read / write storage buffer and the read / write storage buffer mapping area of ​​a flash memory device provided in an embodiment of this application;

[0098] Figure 8 Taking two flash memory devices as an example, this illustrates the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer of the other flash memory devices.

[0099] like Figure 8 As shown, both flash memory device 1 and flash memory device 2 include a read / write storage buffer and a read / write storage buffer mapping area. The read / write storage buffer mapping area of ​​flash memory device 1 is mapped to the read / write storage buffer of flash memory device 2, and the read / write storage buffer mapping area of ​​flash memory device 2 is mapped to the read / write storage buffer of flash memory device 1.

[0100] It is understandable that when there are at least three flash memory devices, the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer of other flash memory devices is similar to... Figure 8 The similarities are not elaborated upon here.

[0101] like Figure 7 As shown, the data management method includes:

[0102] Step S701: Establish a second memory mapping relationship between the host system and each flash memory device;

[0103] Specifically, the host system includes a host memory buffer for storing striped data, which is divided into several data blocks. Each flash memory device includes a memory buffer mapping area for storing at least one data block. The second memory mapping relationship includes the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device.

[0104] In this embodiment of the application, the step of establishing a second memory mapping relationship between the host system and each flash memory device includes: allocating a host memory buffer in the memory of the host system; and mapping the host memory buffer to the storage space of each flash memory device to establish a mapping relationship between the host memory buffer and the memory buffer mapping area of ​​each flash memory device.

[0105] Specifically, the host system allocates a host memory buffer in memory as a mapping area for the data required for RAID calculations by the flash memory device. The RAID calculation includes calculating parity data when writing new stripe data, recalculating parity data when updating some data blocks, and recovering data blocks when a data block is damaged.

[0106] The host system and flash memory devices communicate via the Non-Volatile Memory Express (NVMe) protocol. The host system maps its host memory buffer to the storage space of each flash memory device based on mapping operations within the NVMe protocol, establishing an address mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device. Specifically, when a flash memory device is recognized by the host system, the host system completes the mapping operation by performing a handshake with the flash memory device according to the NVMe driver.

[0107] Please see Figure 9 , Figure 9 This is a schematic diagram illustrating the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​a flash memory device, provided in an embodiment of this application.

[0108] In this embodiment, the host system can communicate with N flash memory devices, where N is a positive integer. N can be set by those skilled in the art according to actual needs, and is not limited in this embodiment. The following example using four flash memory devices illustrates the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device.

[0109] like Figure 9 As shown, each flash memory device includes a memory buffer mapping area, and the host system's host memory buffer is mapped to the memory buffer mapping area of ​​each flash memory device.

[0110] In this embodiment, by establishing a mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device, this application does not require a dedicated RAID controller to forward data blocks and calculate verification data during the bridging process, thus saving costs.

[0111] Step S702: Store the data blocks corresponding to the stripe data into several flash memory devices;

[0112] Specifically, striped data refers to the data to be stored. The host system stripes the data to be stored into several data blocks, and then stores each data block in a different flash memory device. Each data block corresponds one-to-one with a flash memory device.

[0113] In this application embodiment, the step of storing several data blocks corresponding to striped data to several flash memory devices includes: dividing a striped data into several data blocks and storing each data block to a different flash memory device.

[0114] Specifically, the host system divides a striped data into several data blocks using striping and stores them in the host memory buffer. Then, each data block is stored in the corresponding flash memory device. The number of data blocks depends on the RAID algorithm and the protection requirements of the independent disk redundant array system, and is not limited in this embodiment.

[0115] Step S703: Determine the target flash memory device as the computing engine;

[0116] Specifically, the target flash memory device is used to calculate and store verification data.

[0117] In this embodiment of the application, the step of determining the target flash memory device as the computing engine includes: selecting a flash memory device as the target flash memory device from among flash memory devices that do not store data blocks.

[0118] Specifically, when the host system stores several data blocks corresponding to a stripe of data to different flash memory devices, it will select one of the flash memory devices that does not store the aforementioned data blocks as the target flash memory device for calculating and storing the verification data.

[0119] It is understandable that, since the host system's memory buffer and the memory buffer mapping area of ​​each flash memory device are mapped, each flash memory device connected to the host system can act as a computing engine for RAID calculations; that is, each flash memory device connected to the host system can act as a target flash memory device. Compared to existing solutions where the RAID controller with two PCIe buses requires higher bandwidth, this application distributes the RAID calculation task to each flash memory device, thereby reducing the bandwidth requirements for RAID calculations.

[0120] Step S704: Send a verification command to the target flash memory device so that the target flash memory device performs data calculation on several data blocks based on the second memory mapping relationship to generate and store verification data.

[0121] Specifically, the host system sends a verification command to the target flash memory device, enabling the target flash memory device to obtain several data blocks corresponding to a stripe of data based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area. The target flash memory device's memory buffer mapping area is used to store the several data blocks corresponding to the stripe of data.

[0122] The verification command includes a write verification data command, which includes the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data. When a standalone redundant disk array system needs to write new stripe data, the host system sends a write verification data command to the target flash memory device, causing the target flash memory device to perform data calculations on several data blocks corresponding to the new stripe data within the memory buffer mapping area, thereby generating and storing the verification data.

[0123] In this embodiment, the host system sends a verification command to the target flash memory device, so that the target flash memory device performs data calculation on several data blocks based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area. The verification data in this application can be calculated by the flash memory device, without the need for a dedicated RAID controller to calculate the verification data. This reduces the transmission process of verification data between the RAID controller and the storage device, and lowers the bandwidth requirements of the independent disk redundant array system.

[0124] In this embodiment of the application, the method further includes: updating at least one data block.

[0125] For details, please refer to Figure 10 , Figure 10 This is a schematic diagram of a host system updating at least one data block according to an embodiment of this application;

[0126] like Figure 10 As shown, the process of a host system updating at least one data block includes:

[0127] Step S1001: Update at least one data block to obtain at least one first data block;

[0128] Specifically, the host system updates the data blocks to be updated in memory to obtain a first data block that corresponds one-to-one with each data block to be updated, where the first data block is the updated data block.

[0129] Step S1002: Store the first data block to the corresponding flash memory device;

[0130] Specifically, the host system stores each first data block to the corresponding flash memory device. It can be understood that the flash memory device corresponding to the first data block is the flash memory device that stores the data block to be updated corresponding to that first data block; other unupdated data blocks do not need to be rewritten to the flash memory device.

[0131] Step S1003: Send an update verification data command to the target flash memory device so that the target flash memory device performs data calculations on the unupdated data blocks in the first data block and stripe data based on the first memory mapping relationship and the second memory mapping relationship, so as to generate and store the updated verification data.

[0132] Specifically, the verification command also includes an update verification data command, which includes the offset address and data length of the first data block in the host memory buffer, the logical address of the unupdated data blocks in their respective flash memory devices, and the logical address corresponding to the updated verification data.

[0133] The host system sends an update check data command to the target flash memory device, so that the target flash memory device can obtain the first data block based on the second memory mapping relationship, obtain the unupdated data block in the stripe data based on the first memory mapping relationship, and perform data calculation on the first data block and the unupdated data block in the stripe data in the memory buffer mapping area, thereby generating and storing the updated check data.

[0134] In this embodiment, the host system stores the updated data block to the corresponding flash memory device and sends an update verification data command to the target flash memory device, so that the target flash memory device generates and stores the updated verification data based on the first memory mapping relationship and the second memory mapping relationship. This application does not require the RAID controller to act as a bridge process to forward the data block and calculate the verification data when updating at least one data block, which can improve the data update efficiency and storage efficiency.

[0135] In this embodiment of the application, the method further includes: data recovery of the damaged data block.

[0136] For details, please refer to Figure 11 , Figure 11 This is a schematic diagram of a host system data recovery process provided in an embodiment of this application;

[0137] like Figure 11 As shown, the process of restoring data in the host system includes:

[0138] Step S1101: When any data block is damaged, a data recovery command is sent to the target flash memory device so that the target flash memory device can recover the damaged data block based on the first memory mapping relationship and the second memory mapping relationship, and generate a second data block;

[0139] Specifically, when any data block is corrupted, the host system sends a data recovery command to the target flash memory device. This allows the target flash memory device to recover the corrupted data block based on the mapping relationships between its read / write storage buffer and those of other flash memory devices, and between the host system's memory buffer and the target flash memory device's memory buffer, generating a second data block. The data recovery command includes the logical address of the third data block on the corresponding flash memory device, the logical address of the checksum data, and the destination offset address of the second data block in the host memory buffer. The third data block includes uncorrupted data blocks within the striped data, and the second data block is the data block obtained after the corrupted data block has been recovered.

[0140] Step S1102: Obtain the second data block based on the second memory mapping relationship.

[0141] Specifically, after the target flash memory device completes data recovery and stores the second data block in the memory buffer mapping area, the host system obtains the second data block based on the mapping relationship between the host memory buffer and the memory buffer mapping area of ​​the target flash memory device.

[0142] In this embodiment, when any data block is damaged, the host system sends a data recovery command to the target flash memory device. After the target flash memory device completes data recovery, the second data block is obtained based on the mapping relationship between the host memory buffer and the memory buffer mapping area of ​​the target flash memory device. Compared with the existing solution, which requires the RAID controller to read the undamaged data and verification data from each storage device, perform data recovery, and then transmit the recovered data to the host, this application does not require the RAID controller to perform data recovery, thus improving data recovery efficiency.

[0143] In this embodiment, since the RAID calculation is performed by the target flash memory device and there is no dedicated RAID controller, the host system and the target flash memory device control the relevant RAID operations based on specific commands. Specifically, while establishing an address mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, the host system and the target flash memory device communicate through custom commands in the Non-Volatile Memory Host Controller Interface Specification Protocol, such as through the VU Command in the NVMe protocol.

[0144] In this embodiment, a data management method is provided, applied to a host system. The host system is communicatively connected to multiple flash memory devices, wherein each flash memory device has a first memory mapping relationship with the other flash memory devices. The data management method includes: establishing a second memory mapping relationship between the host system and each flash memory device; storing several data blocks corresponding to striped data to the several flash memory devices, wherein each data block corresponds one-to-one with one flash memory device; determining a target flash memory device as the computing engine; and sending a verification command to the target flash memory device, causing the target flash memory device to perform data calculations on the several data blocks based on the second memory mapping relationship to generate and store verification data.

[0145] The host system stores several data blocks corresponding to the striped data to different flash memory devices and sends a verification command to the target flash memory device so that the target flash memory device can perform data calculation on several data blocks based on the second memory mapping relationship. The verification data in this application can be calculated by the flash memory device, without the need for a dedicated RAID controller to calculate the verification data. This can reduce the transmission process of verification data between the RAID controller and the storage device and reduce the bandwidth requirements of the independent disk redundant array system.

[0146] Example 2

[0147] Please see Figure 12 , Figure 12 This is a flowchart illustrating a method for verifying data provided in an embodiment of this application;

[0148] The method for verifying the data is applied to a storage array, for example, a second storage array comprising multiple flash memory devices that are communicatively connected. Specifically, the method for verifying the data is applied to at least one flash memory device in the second storage array, and is executed by an independent redundant disk array engine for each flash memory device. Each flash memory device has a first memory mapping relationship with other flash memory devices, each flash memory device is communicatively connected to the host system, and each flash memory device has a second memory mapping relationship with the host system.

[0149] Specifically, the host system includes a host memory buffer for storing striped data, which is divided into several data blocks. Each flash memory device includes a memory buffer mapping area, a read / write storage buffer, and a read / write storage buffer mapping area. The memory buffer mapping area stores at least one data block from the host system, the read / write storage buffer stores data blocks read from the flash memory medium, and the read / write storage buffer mapping area stores data blocks from other flash memory devices. A first memory mapping relationship includes the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffers of other flash memory devices, and a second memory mapping relationship includes the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device. Preferably, the flash memory device is an NVMe SSD.

[0150] It is understandable that for most flash memory device controllers, the controller itself has a built-in independent redundant disk array engine. The original function of this independent redundant disk array engine is to perform RAID protection on the data stored in the flash memory device. It should be noted that the RAID protection here is unrelated to the RAID calculation in this application. The RAID calculation in this application is system-level RAID. The independent redundant disk array engine can perform RAID protection on the data blocks or parity data stored in the flash memory device again after completing the verification data method in this application.

[0151] like Figure 12 As shown, the method for verifying the data includes:

[0152] Step S1201: Based on the verification command sent by the host system and the second memory mapping relationship, perform data calculation on several data blocks to generate and store verification data.

[0153] Specifically, the target flash memory device in the second storage array receives a verification command sent by the host system, and based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, obtains several data blocks corresponding to the striped data, performs data calculations on these data blocks in the memory buffer mapping area to generate verification data, and stores the verification data in the flash memory medium. The verification command and the several data blocks corresponding to the striped data are obtained by the data management method described in Embodiment 1 above.

[0154] It is understandable that although the target flash memory device is determined by the host system, the target flash memory device determined by the host system may be different when processing different stripe data. Therefore, each flash memory device in the second storage array can be used as the target flash memory device to perform the data verification method in Embodiment 2.

[0155] In this embodiment of the application, the step of performing data calculations on several data blocks based on the verification command sent by the host system and the second memory mapping relationship to generate and store verification data includes steps S1-S4, as follows:

[0156] Step S1: Receive and parse the command to write verification data to obtain the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data;

[0157] Specifically, the verification command includes a write verification data command, which includes the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data. The target flash memory device receives and parses the write verification data command sent by the host system to obtain the offset address and data length of each data block in the striped data in the host memory buffer, as well as the logical address corresponding to the verification data.

[0158] Step S2: Based on the second mapping relationship, the offset address of each data block in the host memory buffer, and the data length, obtain several data blocks corresponding to the striped data;

[0159] Specifically, since a mapping relationship is established between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, there will be an address segment in the target flash memory device's memory buffer mapping area pointing to the host system's host memory buffer. Therefore, the target flash memory device can obtain several data blocks corresponding to the striped data based on this mapping relationship, the offset address of each data block in the host memory buffer, and the data length.

[0160] Step S3: In the memory buffer mapping area of ​​the target flash memory device, perform an XOR operation on all data blocks of the stripe data to obtain the parity data corresponding to the stripe data;

[0161] Specifically, within the memory buffer mapping area, the target flash memory device performs an XOR operation on all data blocks of the stripe data to obtain the parity data corresponding to the stripe data, and stores the parity data in the internal storage space of the target flash memory device, for example, in the double-rate synchronous dynamic random access memory of the target flash memory device.

[0162] Step S4: Using the logical address corresponding to the verification data as the storage index, store the verification data in the flash memory medium.

[0163] Specifically, the target flash memory device uses the logical address corresponding to the verification data as a storage index to store the verification data from its internal storage space to the flash memory medium, and sends a command to the host system to complete the write verification data operation.

[0164] Please see Figure 13 , Figure 13This is a schematic diagram illustrating the writing of verification data to a target flash memory device according to an embodiment of this application;

[0165] Figure 13 The striped data is divided into data blocks A1, A2, and A3. The second storage array includes four flash memory devices, with flash memory device 4 being the target flash memory device. The process of writing verification data to the target flash memory device is described. It is understood that the second storage array may include N flash memory devices, where N is a positive integer. N can be determined by those skilled in the art based on actual conditions, and is not limited in the embodiments of this application.

[0166] like Figure 13 As shown, when the host system stores data blocks A1, A2, and A3 to flash memory devices 1, 2, and 3 respectively, flash memory device 4 serves as the target flash memory device. Based on the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​flash memory device 4, it obtains data blocks A1, A2, and A3. Within the memory buffer mapping area, it performs an XOR operation on data blocks A1, A2, and A3 to obtain check data Ap. Then, it stores the check data Ap in the internal storage space. Finally, using the logical address corresponding to the check data Ap as the storage index, it stores the check data Ap in the flash memory medium.

[0167] In this embodiment, verification data is generated and stored by performing data calculations on several data blocks based on the verification command sent by the host system, the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area. The verification data in this application can be calculated by the flash memory device, eliminating the need for a dedicated RAID controller to calculate the verification data. This reduces the transmission process of verification data between the RAID controller and the storage device, thereby lowering the bandwidth requirements of the independent disk redundant array system.

[0168] Please see Figure 14 , Figure 14 This is a schematic diagram illustrating the writing of verification data to another target flash memory device according to an embodiment of this application;

[0169] In this embodiment of the application, each flash memory device in the second storage array can be used as a target flash memory device to perform RAID calculations, that is, to calculate parity data when new stripe data is written, to recalculate parity data when some data blocks are updated, and to recover data blocks when a certain data block is damaged.

[0170] Figure 14 The striped data is divided into data block B1, data block B2 and data block B3. The second storage array includes 4 flash memory devices, and the target flash memory device is flash memory device 3. The process of writing verification data to the target flash memory device is described.

[0171] like Figure 14 As shown, when the host system stores data blocks B1, B2, and B3 to flash memory devices 1, 2, and 4 respectively, flash memory device 3 serves as the target flash memory device. Based on the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​flash memory device 3, it obtains data blocks B1, B2, and B3. Within the memory buffer mapping area, it performs an XOR operation on data blocks B1, B2, and B3 to obtain check data Bp. Then, it stores check data Bp in the internal storage space. Finally, using the logical address corresponding to check data Bp as the storage index, it stores check data Bp in the flash memory medium.

[0172] In this embodiment, the second storage array includes multiple flash memory devices. The memory buffer mapping area of ​​each flash memory device has an address mapping relationship with the host memory buffer of the host system. Each flash memory device in the storage array can independently complete the calculation of verification data without the need for a dedicated RAID controller to calculate the verification data. This reduces the transmission process of verification data between the RAID controller and the storage device, and lowers the bandwidth requirements of the independent disk redundant array system.

[0173] In this embodiment of the application, the method further includes: dividing a read-write storage buffer in the memory of each flash memory device; mapping the read-write storage buffer to the storage space of each of the remaining flash memory devices, so as to establish a mapping relationship between the read-write storage buffer mapping area of ​​each flash memory device and the read-write storage buffer of other flash memory devices.

[0174] Specifically, flash memory devices allocate read / write storage buffers in memory, which serve as mapping areas for calculating the data required during data recovery. Simultaneously, these read / write storage buffers are mapped to read / write storage buffer mapping areas of other flash memory devices. The mapping relationship between the read / write storage buffer and the read / write storage buffer mapping areas is as follows: Figure 8 As shown. The flash memory devices in the second storage array establish a mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer of other flash memory devices through the mapping operation of the NVMe protocol, that is, the first memory mapping relationship.

[0175] In this embodiment of the application, the method further includes: updating the corresponding verification data when at least one data block is updated. Specifically, when at least one data block in a certain data strip is updated, the flash memory device storing the verification data corresponding to that data strip undertakes the task of updating the verification data, that is, the target flash memory device mentioned above updates the verification data.

[0176] Please see Figure 15 , Figure 15This is a schematic diagram of a process for updating verification data in a target flash memory device according to an embodiment of this application;

[0177] like Figure 15 As shown, the process for updating verification data in the target flash memory device includes:

[0178] Step S1501: Based on the update verification data command sent by the host system and the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, obtain the first data block;

[0179] Specifically, the target flash memory device receives the update verification data command sent by the host system, and obtains the first data block corresponding to each data block to be updated based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area.

[0180] The first data block is the updated data block. The update verification data command includes the offset address and data length of the first data block in the host memory buffer, the logical addresses of the unupdated data blocks in their respective flash memory devices, and the logical address corresponding to the updated verification data. The update verification data command and the first data block are obtained by the data management method in Embodiment 1.

[0181] In this embodiment of the application, the step of obtaining the first data block based on the update verification data command sent by the host system and the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area includes steps S1-S2, as follows:

[0182] Step S1: Receive and parse the update verification data command to obtain the offset address and data length of the first data block in the host memory buffer, the logical address of the unupdated data blocks in their respective flash memory devices, and the logical address corresponding to the updated verification data.

[0183] Specifically, the target flash memory device receives and parses the update verification data command sent by the host system to obtain the offset address and data length of the first data block in the host memory buffer, the logical address of the unupdated data blocks in their respective flash memory devices, and the logical address corresponding to the updated verification data.

[0184] Step S2: Based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, the offset address and data length of the first data block in the host memory buffer, obtain the first data block.

[0185] Specifically, the target flash memory device obtains the first data block within the memory buffer mapping area based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, the offset address of the first data block in the host memory buffer, and the data length.

[0186] Step S1502: Based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices, obtain the data blocks that have not been updated in the stripe data;

[0187] Specifically, the target flash memory device retrieves unupdated data blocks from other flash memory devices based on the mapping relationship between the target flash memory device's read / write storage buffer mapping area and the read / write storage buffers of other flash memory devices.

[0188] In this embodiment of the application, the step of obtaining the unupdated data blocks in the stripe data based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices includes steps S1-S2, as follows:

[0189] Step S1: Send a first read command to each flash memory device that stores unupdated data blocks to obtain the address of each unupdated data block in the read / write storage buffer of the corresponding flash memory device;

[0190] Specifically, the target flash memory device determines the flash memory device containing the unupdated data blocks within the stripe data corresponding to the data block to be updated, and sends a first read command to each of these flash memory devices to obtain the address of each unupdated data block in the read / write storage buffer of its respective flash memory device. The first read command includes the logical address of the unupdated data block in the corresponding flash memory device.

[0191] Understandably, after receiving the first read command from the target flash memory device, other flash memory devices will read the unupdated data block from the flash memory medium according to the logical address of the unupdated data block, store the unupdated data block in the read / write storage buffer, and send the address of the unupdated data block in the read / write storage buffer to the target flash memory device.

[0192] Step S2: Based on the address of each unupdated data block in the read / write storage buffer of the corresponding flash memory device, obtain each unupdated data block through point-to-point operation.

[0193] Specifically, flash memory devices communicate based on peer-to-peer commands (P2P Commands) in the high-speed serial computer extended protocol. The target flash memory device retrieves each unupdated data block from the read / write buffer of the other flash memory device through a peer-to-peer operation via the PCIe bus, based on the address of each unupdated data block in the read / write buffer of the corresponding flash memory device, and stores the unupdated data block in the read / write buffer mapping area.

[0194] Understandably, peer-to-peer operation enables one flash memory device to directly access another flash memory device.

[0195] Step S1503: Perform data calculations on the first data block and the unupdated data blocks in the strip data to generate and store the updated verification data.

[0196] Specifically, the target flash memory device performs data calculations on the first data block and the unupdated data blocks in the stripe data corresponding to the first data block to generate and store updated verification data.

[0197] In this embodiment of the application, the step of performing data calculations on the first data block and the unupdated data blocks in the stripe data to generate and store updated verification data includes steps S1-S2, as follows:

[0198] Step S1: Perform an XOR operation between the unupdated data block stored in the memory buffer mapping area of ​​the target flash memory device and the first data block stored in the read / write storage buffer mapping area of ​​the target flash memory device to obtain the updated verification data;

[0199] Specifically, the target flash memory device performs an XOR operation on the unupdated data block stored in the memory buffer mapping area and the first data block stored in the read / write storage buffer mapping area to obtain the updated check data, and stores the updated check data in the internal storage space of the target flash memory device.

[0200] Step S2: Using the logical address corresponding to the updated verification data as the storage index, store the updated verification data into the flash memory medium of the target flash memory device.

[0201] Specifically, the target flash memory device uses the logical address corresponding to the updated verification data as a storage index to store the updated verification data from its internal storage space to the flash memory medium, and sends an update verification data command back to the host system to complete the process.

[0202] Please see Figure 16 , Figure 16 This is a schematic diagram illustrating the updating of verification data for a target flash memory device according to an embodiment of this application;

[0203] Figure 16 The striped data is divided into data block A1, data block A2 and data block A3. Data block A1 is updated to data block A1' in the host system, and data block A2 is updated to data block A2' in the host system. The second storage array includes 4 flash memory devices, and the target flash memory device is flash memory device 4. The process of updating the verification data of the target flash memory device is described.

[0204] like Figure 16 As shown, when the host system stores data block A1' and data block A2' in flash memory device 1 where data block A1 is located and flash memory device 2 where data block A2 is located, respectively, data block A3 does not need to be re-stored since it has not been updated. Flash memory device 4, as the target flash memory device, obtains data block A1' and data block A2' based on the update verification data command sent by the host system and the mapping relationship between the host memory buffer and the memory buffer mapping area of ​​flash memory device 4. Based on the mapping relationship between the read / write storage buffer of flash memory device 3 and the read / write storage buffer mapping area of ​​flash memory device 4, it obtains data block A3. Then, it performs an XOR operation on data block A1', data block A2', and data block A3 to generate updated verification data Ap', and stores the updated verification data Ap' from the internal storage space to the flash memory medium.

[0205] In this embodiment, a first data block is obtained based on the update verification data command sent by the host system and the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area. Based on the mapping relationship between the target flash memory device's read / write storage buffer mapping area and the read / write storage buffers of other flash memory devices, an unupdated data block in the striped data is obtained. Data calculations are performed on the first data block and the unupdated data blocks in the striped data to generate and store updated verification data. This application enables the flash memory device to calculate updated verification data when at least one data block is updated, eliminating the need for a dedicated RAID controller to forward updated data blocks and calculate verification data. This reduces the transmission process of verification data between the RAID controller and the storage device, thereby lowering the bandwidth requirements of the independent disk redundant array system.

[0206] In this embodiment of the application, the method further includes: data recovery of the damaged data block.

[0207] Please see Figure 17 , Figure 17 This is a schematic diagram illustrating the process of a target flash memory device recovering data from damaged data blocks, provided in an embodiment of this application.

[0208] like Figure 17 As shown, the process of data recovery from damaged data blocks by the target flash memory device includes:

[0209] Step S1701: Based on the data recovery command sent by the host system and the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices, obtain the third data block;

[0210] Specifically, the target flash memory device receives a data recovery command sent by the host system and obtains a third data block based on the mapping relationship between the target flash memory device's read / write storage buffer and the read / write storage buffers of other flash memory devices. The data recovery command includes the logical address of the third data block in the corresponding flash memory device, the logical address corresponding to the checksum data, and the destination storage offset address of the second data block in the host memory buffer. The third data block includes undamaged data blocks within the striped data, and the third data block corresponds to the same striped data as the damaged data block. The second data block is the data block obtained after the damaged data block has been recovered. The data recovery command and the third data block are obtained using the data management method described in Embodiment 1.

[0211] In this embodiment of the application, the step of obtaining the third data block based on the data recovery command sent by the host system and the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices includes steps S1-S3, as follows:

[0212] Step S1: Receive and parse the data recovery command to obtain the logical address of the third data block in the corresponding flash memory device, the logical address of the verification data, and the destination storage offset address of the second data block in the host memory buffer;

[0213] Specifically, the target flash memory device receives and parses the data recovery command sent by the host system to obtain the logical address of the third data block in the corresponding flash memory device, the logical address of the verification data, and the destination storage offset address of the second data block in the host memory buffer.

[0214] Step S2: Send a second read command to each flash memory device that stores the third data block to obtain the address of each third data block in the read / write storage buffer of the corresponding flash memory device;

[0215] Specifically, the target flash memory device sends a second read command to each flash memory device storing the third data block to obtain the address of each third data block in the read / write storage buffer of its respective flash memory device. The second read command includes the logical address of the third data block in the corresponding flash memory device.

[0216] It is understandable that after receiving the second read command from the target flash memory device, other flash memory devices will read the third data block from the flash memory medium according to the logical address of the third data block, store the third data block in the read-write storage buffer, and send the address of the third data block in the read-write storage buffer to the target flash memory device.

[0217] Step S3: Based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices, and the address of each third data block in the read / write storage buffer of the corresponding flash memory device, obtain each third data block through point-to-point operation.

[0218] Specifically, the target flash memory device reads the third data block from the read / write storage buffer of each flash memory device that stores the third data block through point-to-point operation via the PCIe bus, based on the mapping relationship between the target flash memory device's read / write storage buffer mapping area and the read / write storage buffer of each flash memory device that stores the third data block, and stores the read third data block in the target flash memory device's read / write storage buffer mapping area.

[0219] Step S1702: Based on the third data block and the verification data, perform data recovery on the damaged data block.

[0220] Specifically, the target flash memory device reads the check data corresponding to the stripe data where the third data block is located from the flash memory medium, and performs an XOR operation on the third data block and the check data to obtain the second data block corresponding to the damaged data block.

[0221] In this embodiment of the application, the step of recovering data from a damaged data block based on a third data block and verification data includes steps S1-S2, as follows:

[0222] Step S1: Based on the logical address corresponding to the verification data, read the verification data from the flash memory medium of the target flash memory device;

[0223] Specifically, the target flash memory device reads the verification data from the flash memory medium based on the logical address corresponding to the verification data, and stores the verification data in the internal storage space.

[0224] Step S2: In the read / write storage buffer mapping area of ​​the target flash memory device, perform an XOR operation on several third data blocks and the check data to obtain the second data block, and transfer the second data block to the destination storage offset address of the host memory buffer.

[0225] Specifically, in the target flash memory device's read / write storage buffer mapping area, several third data blocks are XORed with the checksum data to obtain the second data block. This second data block is then stored in the memory buffer mapping area. Based on the address mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, the second data block is transferred to its destination offset address in the host system's host memory buffer. After the target flash memory device completes data recovery, it sends a data recovery completion command to the host system.

[0226] In this embodiment of the application, when the flash memory device in the storage array performs data recovery or updates verification data, the address of the third data block obtained by the flash memory device in the read / write storage buffer and the address of the unupdated data block in the read / write storage buffer are both spatial domain addresses mapped to the target flash memory device.

[0227] Please see Figure 18 , Figure 18 This is a schematic diagram illustrating how a target flash memory device recovers data from damaged data blocks, as provided in an embodiment of this application.

[0228] Figure 18 The striped data is divided into data blocks A1, A2, and A3. The second storage array includes four flash memory devices. The target flash memory device is flash memory device 4. Data block A1 is damaged, while data blocks A2 and A3 are undamaged data blocks. That is, data blocks A2 and A3 are the third data blocks. This illustrates the process of the target flash memory device recovering data from the damaged data blocks.

[0229] like Figure 18 As shown, the damaged data blocks A1, A2, and A3 are stored in flash memory devices 1, 2, and 3, respectively. Flash memory device 4 serves as the target flash memory device. Based on the data recovery command sent by the host system and the mapping relationship between the read / write storage buffer of flash memory device 2 and the read / write storage buffer mapping area of ​​flash memory device 4, data block A2 is read from the read / write storage buffer of flash memory device 2, and data block A3 is read from the read / write storage buffer of flash memory device 3 based on the mapping relationship between the read / write storage buffer of flash memory device 3 and the read / write storage buffer mapping area of ​​flash memory device 4.

[0230] Then, the target flash memory device reads the check data Ap corresponding to the damaged data blocks A1, A2, and A3 from the flash memory medium. In the read / write storage buffer mapping area of ​​the target flash memory device, it performs an XOR operation on data blocks A2, A3, and check data Ap to obtain data block A1. The obtained data block A1 is the second data block mentioned above, thus completing the data recovery operation of the damaged data block A1. The obtained data block A1 is then stored in the memory buffer mapping area. Based on the address mapping relationship between the host memory buffer and the target flash memory device's memory buffer mapping area, data block A1 is transferred to the destination storage offset address of data block A1 in the host system's host memory buffer.

[0231] In this embodiment, a third data block is obtained by using the data recovery command sent by the host system and the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices. Based on the third data block and the verification data, the damaged data block is recovered. This application can recover the damaged data block by the flash memory device when the data block is damaged, without the need for a dedicated RAID controller to perform data recovery operations. This reduces the data transmission process between the RAID controller and the storage device and lowers the bandwidth requirements of the independent disk redundant array system.

[0232] In this embodiment, a method for verifying data is provided. This method is applied to a storage array, which includes multiple flash memory devices. Each flash memory device has a first memory mapping relationship with other flash memory devices, and each flash memory device is communicatively connected to a host system. Each flash memory device also has a second memory mapping relationship with the host system. The method for verifying data includes: performing data calculations on several data blocks based on a verification command sent by the host system and the second memory mapping relationship to generate and store verification data. The verification data is directly stored in the flash memory medium by the target flash memory device, and the verification command and data blocks are obtained by the data management method in Embodiment 1.

[0233] By performing data calculations on several data blocks based on the verification command sent by the host system and the second memory mapping relationship, verification data is generated and stored. In this application, the verification data is calculated by the flash memory device, which does not require a dedicated RAID controller to calculate the verification data. This reduces the transmission process of verification data between the RAID controller and the storage device and lowers the bandwidth requirements of the independent disk redundant array system.

[0234] Example 3

[0235] Please see Figure 19 , Figure 19 This is a schematic diagram of a distributed independent disk redundancy array system provided in an embodiment of this application;

[0236] like Figure 19 As shown, the distributed independent disk redundant array system 190 includes a host system 191 and a second storage array 192. The host system 191 and the second storage array 192 are connected via a communication bus, for example, via a PCIe bus.

[0237] Please see Figure 20 , Figure 20 This is a schematic diagram of the structure of a host system provided in an embodiment of this application;

[0238] In this embodiment, the host system applies the data management method described in Embodiment 1 above.

[0239] like Figure 20 As shown, the host system 191 includes a processor system 1911 and a host memory system 1912. The processor system 1911 and the host memory system 1912 are connected via a bus.

[0240] The processor system 1911, connected to the host memory system 1912, is used to divide a stripe of data into several data blocks and transfer the data blocks to the host memory system 1912. Specifically, the processor system 1911 is used to execute the data management method in Embodiment 1 above, such as: establishing a second memory mapping relationship between the host system and each flash memory device; storing several data blocks corresponding to the stripe data to several flash memory devices, wherein each data block corresponds one-to-one with a flash memory device; determining the target flash memory device as the computing engine; and sending a verification command to the target flash memory device so that the target flash memory device performs data calculations on the several data blocks based on the second memory mapping relationship to generate and store verification data. In this embodiment, the processor system 1911 includes, but is not limited to, a central processing unit (CPU).

[0241] The host memory system 1912, connected to the processor system 1911, is used to store data blocks. Specifically, the host memory system 1912 includes a host memory buffer, which is used to store striped data, wherein the striped data is divided into several data blocks.

[0242] In this embodiment, the host memory system 1912 includes, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM).

[0243] In this embodiment, a host system is provided that applies the data management method described in Embodiment 1. The host system includes: a processor system connected to a host memory system, used to divide a stripe of data into several data blocks and transmit the data blocks to the host memory system; and a host memory system connected to the processor system, used to store the data blocks. This application can reduce the number of RAID controllers and lower the bandwidth requirements of redundant independent disk array systems.

[0244] Please see Figure 21 , Figure 21 This is a schematic diagram of the structure of a second storage array provided in an embodiment of this application;

[0245] In this embodiment, the second storage array applies the method for verifying data described in Embodiment 2 above.

[0246] like Figure 21 As shown, the second storage array 192 includes multiple flash memory devices 1921. Each flash memory device 1921 can execute the data verification method described in Embodiment 2 above. The number of flash memory devices 1921 can be set by those skilled in the art according to actual conditions, and is not limited in this embodiment.

[0247] Please see Figure 22 , Figure 22 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0248] like Figure 22 As shown, the flash memory device 220 includes a standalone redundant disk array engine 221 and at least one flash memory medium 222. This flash memory device is a flash memory device in a second storage array.

[0249] Independent disk redundant array engine 221, connected to flash memory medium 222, is used to execute the method of verifying data in the above embodiment 2, for example: based on the verification command sent by the host system and the second memory mapping relationship, perform data calculation on several data blocks to generate and store verification data, wherein the verification data is directly stored in the flash memory medium by the target flash memory device, and the verification command and data blocks are obtained by the data management method in embodiment 1.

[0250] Flash memory 222 is communicatively connected to independent disk redundant array engine 221 and is used to store data blocks and parity data.

[0251] In this application embodiment, a storage array, such as a second storage array, is provided. This storage array applies the data verification method as described in Embodiment 2. The storage array includes multiple flash memory devices, each of which includes an independent redundant disk array engine and at least one flash memory medium communicatively connected to the independent redundant disk array engine. This application enables the RAID calculation task to be offloaded to the flash memory devices in the second storage array, eliminating the need for a dedicated RAID controller. This reduces the data transfer process between the RAID controller and the storage devices, and lowers the bandwidth requirements of the independent redundant disk array system.

[0252] Please see Figure 23 , Figure 23 This is a schematic diagram of the specific structure of a distributed independent disk redundant array system provided in an embodiment of this application;

[0253] like Figure 23 As shown, the distributed independent disk redundant array system 190 includes a host system 191, a second storage array 192, and a communication bus 193.

[0254] The host system 191 is used to execute the data management method in Embodiment 1. The host system 191 includes a processor system 1911 and a host memory system 1912. For the specific structure and function of the host system 191, please refer to [link / reference]. Figure 20 The relevant content will not be repeated here.

[0255] A communication bus 193 connects the host system 191 and the second storage array 192, and is used for data transmission. In this embodiment, the communication bus 193 includes, but is not limited to, a PCIe bus.

[0256] The second storage array 192 is used to execute the data verification method in Embodiment 2. For the specific structure and function of the second storage array 192, please refer to [link / details]. Figure 21 The relevant content will not be repeated here.

[0257] In this embodiment, each flash memory device in the second storage array has a first memory mapping relationship with other flash memory devices, and the host system has a second memory mapping relationship with each flash memory device in the second storage array. The host memory system includes a host memory buffer, and each flash memory device in the second storage array includes a memory buffer mapping area, a read / write storage buffer, and a read / write storage buffer mapping area. The first memory mapping relationship includes the mapping relationship between the read / write storage buffer of each flash memory device and the read / write storage buffer mapping areas of other flash memory devices. The second memory mapping relationship includes the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device in the second storage array.

[0258] In this embodiment, a distributed independent redundant disk array system is provided. This system includes: a host system for executing the data management method in Embodiment 1; and a storage array for executing the data verification method in Embodiment 2, wherein the host system and the storage array are connected via a communication bus. This application can distribute RAID computation tasks to various flash memory devices in the storage array, eliminating the need for a dedicated RAID controller. This reduces the data transmission process between the RAID controller and the storage devices, thereby lowering the bandwidth requirements of the independent redundant disk array system.

[0259] Please see Figure 24 , Figure 24 This is a schematic diagram of data distribution at different stages of a distributed independent disk redundant array system provided in an embodiment of this application;

[0260] In this embodiment, the host system divides stripe data A, stripe data B, and stripe data C into several data blocks and stores them in the host memory system. For example, stripe data A is divided into data block A1, data block A2, and data block A3; stripe data B is divided into data block B1, data block B2, and data block B3; stripe data C is divided into data block C1, data block C2, and data block C3; and stripe data D is divided into data block D1, data block D2, and data block D3.

[0261] like Figure 24 As shown, the host memory system 1912 stores data blocks A1, A2, A3, B1, B2, B3, C1, C2, C3, D1, D2, and D3.

[0262] The host system stores the data blocks corresponding to a stripe of data to different flash memory devices through the communication bus 193, and sends a verification command to the corresponding target flash memory device so that the target flash memory device can perform data calculation, generate and store verification data.

[0263] For example: The host system stores data block D1 to flash memory device 2, data block D2 to flash memory device 3, and data block D3 to flash memory device 4, while determining the target flash memory device as flash memory device 1. Flash memory device 1 receives the verification command sent by the host system, generates and stores verification data Dp; The host system stores data block C1 to flash memory device 1, data block C2 to flash memory device 3, and data block C3 to flash memory device 4, while determining the target flash memory device as flash memory device 2. Flash memory device 2 receives the verification command sent by the host system, generates and stores verification data Cp.

[0264] For example: The host system stores data block B1 to flash memory device 1, data block B2 to flash memory device 2, and data block B3 to flash memory device 4, while determining the target flash memory device as flash memory device 3. Flash memory device 3 receives the verification command sent by the host system, generates and stores verification data Bp; The host system stores data block A1 to flash memory device 1, data block A2 to flash memory device 2, and data block A3 to flash memory device 3, while determining the target flash memory device as flash memory device 4. Flash memory device 4 receives the verification command sent by the host system, generates and stores verification data Ap.

[0265] Please see Figure 25 , Figure 25 This is a schematic diagram illustrating the data writing process of a distributed independent disk redundant array system provided in an embodiment of this application;

[0266] like Figure 25 As shown, the data writing process in a distributed independent disk redundant array system includes:

[0267] Step S2501: Establish a second memory mapping relationship between the host system and each flash memory device;

[0268] Specifically, the second memory mapping relationship includes the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device. The host system allocates a host memory buffer in memory as a mapping area for the data required by the flash memory devices for RAID calculations. The distributed independent disk redundant array system is initialized to map the host memory buffer to the storage space of each flash memory device in the storage array, that is, to establish the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device.

[0269] Step S2502: The host system stores several data blocks corresponding to the stripe data into several flash memory devices and sends a write verification data command to the target flash memory device;

[0270] Specifically, the host system divides a stripe of data into several data blocks through striping and stores them in the host memory buffer. Then, each data block is stored in the corresponding flash memory device, and a write verification data command is sent to the target flash memory device. This allows the target flash memory device to obtain several data blocks corresponding to the stripe data based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area. The target flash memory device then performs data calculations on these data blocks in the memory buffer mapping area to generate and store the verification data.

[0271] Step S2503: The target flash memory device performs data calculations on several data blocks based on the write verification data command and the second memory mapping relationship to generate and store verification data.

[0272] Specifically, the target flash memory device receives and parses the write parity data command to obtain the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the parity data. Then, based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, and the offset address and data length of each data block in the host memory buffer, the target flash memory device obtains several data blocks corresponding to the striped data. Within the target flash memory device's memory buffer mapping area, it performs an XOR operation on all data blocks in the striped data to obtain the parity data corresponding to the striped data. Finally, using the logical address corresponding to the parity data as a storage index, it stores the parity data in the flash memory medium.

[0273] Please see Figure 26 , Figure 26 This is a schematic diagram illustrating the data update process of a distributed independent disk redundant array system provided in an embodiment of this application;

[0274] like Figure 26 As shown, the data update process of a distributed independent disk redundant array system includes:

[0275] Step S2601: Establish a first memory mapping relationship between each flash memory device and other flash memory devices, and a second memory mapping relationship between the host system and each flash memory device;

[0276] Specifically, the first memory mapping relationship includes the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer of other flash memory devices. The second memory mapping relationship includes the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device. The host system allocates a host memory buffer in memory as the mapping area for the data required by the flash memory devices for RAID calculations. The flash memory devices allocate read / write storage buffers in the storage space as the mapping area for the data required by the flash memory devices for data recovery calculations.

[0277] The distributed independent disk redundant array system is initialized by mapping the host memory buffer to the storage space of each flash memory device in the storage array, that is, establishing a mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device, and mapping the read and write storage buffer of each flash memory device to the storage space of other flash memory devices, that is, establishing a mapping relationship between the read and write storage buffer mapping area of ​​each flash memory device and the read and write storage buffer of other flash memory devices.

[0278] Step S2602: The host system stores the updated data block to the corresponding flash memory device and sends an update verification data command to the target flash memory device;

[0279] Specifically, the host system updates the data blocks to be updated in memory to obtain a first data block that corresponds one-to-one with each data block to be updated, stores each first data block in the corresponding flash memory device, and sends an update verification data command to the target flash memory device so that the target flash memory device can perform data calculations on the first data block and the unupdated data blocks in the stripe data based on the first memory mapping relationship and the second memory mapping relationship to generate and store the updated verification data.

[0280] Step S2603: The target flash memory device performs data calculations on the unupdated data blocks in the first data block and stripe data based on the update verification data command, the first memory mapping relationship and the second memory mapping relationship, and generates and stores the updated verification data.

[0281] Specifically, the target flash memory device receives an update verification data command from the host system. Based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, it obtains the first data block corresponding to each data block to be updated. Then, based on the mapping relationship between the target flash memory device's read / write storage buffer mapping area and the read / write storage buffers of other flash memory devices, the target flash memory device obtains the unupdated data blocks from the striped data in the other flash memory devices. Finally, the target flash memory device performs data calculations on the first data block and the corresponding unupdated data blocks in the striped data to generate and store the updated verification data.

[0282] Please see Figure 27 , Figure 27 This is a schematic diagram of a data recovery process provided in an embodiment of this application for a distributed independent disk redundant array system;

[0283] like Figure 27 As shown, the data recovery process of a distributed independent disk redundant array system includes:

[0284] Step S2701: Establish a first memory mapping relationship between each flash memory device and other flash memory devices, and a second memory mapping relationship between the host system and each flash memory device;

[0285] Specifically, the implementation method of this step is the same as that of step S2701, and will not be repeated here.

[0286] Step S2702: The host system sends a data recovery command to the target flash memory device;

[0287] Specifically, when any data block is damaged, the host system sends a data recovery command to the target flash memory device, so that the target flash memory device can perform data recovery on the damaged data block based on the first memory mapping relationship and the second memory mapping relationship, and generate a second data block. The second data block is the data block obtained after the damaged data block has been recovered.

[0288] Step S2703: The target flash memory device recovers the damaged data blocks based on the data recovery command sent by the host system, the first memory mapping relationship, and the second memory mapping relationship, and transmits the recovered data blocks to the host system.

[0289] Specifically, the target flash memory device receives a data recovery command from the host system and, based on the mapping relationship between the target flash memory device's read / write storage buffer and the read / write storage buffers of other flash memory devices, obtains a third data block. This third data block includes undamaged data blocks within the striped data. Then, the target flash memory device reads the parity data corresponding to the striped data containing the third data block from the flash memory medium and performs an XOR operation between the third data block and the parity data to obtain a second data block corresponding to the damaged data block. This second data block is then stored in the memory buffer mapping area. Finally, based on the address mapping relationship between the host memory buffer and the target flash memory device's memory buffer mapping area, the second data block is transferred to its destination storage offset address in the host system's host memory buffer.

[0290] In this embodiment, the host system in the distributed independent disk redundant array system executes the data management method in Embodiment 1, and the storage array executes the data verification method in Embodiment 2. This application can distribute RAID calculation tasks to each flash memory device in the storage array without the need for a dedicated RAID controller, thereby reducing the data transmission process between the RAID controller and the storage device and lowering the bandwidth requirements of the independent disk redundant array system.

[0291] Example 4

[0292] This application also provides a non-volatile computer storage medium storing computer-executable instructions that can be executed by one or more processors, enabling the one or more processors to execute the data management method in the first method embodiment or the data verification method in the second method embodiment.

[0293] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0294] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0295] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data management method applied to a host system, characterized in that, The host system is communicatively connected to multiple flash memory devices, wherein each flash memory device has a first memory mapping relationship with the other flash memory devices; each flash memory device includes a read / write storage buffer and a read / write storage buffer mapping area, and the first memory mapping relationship includes the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer of the other flash memory devices; The read / write storage buffer is used to store data blocks read from the flash memory medium, and the read / write storage buffer mapping area is used to store data blocks from other flash memory devices; the method includes: Establish a second memory mapping relationship between the host system and each of the flash memory devices; The striped data is stored in several data blocks corresponding to several flash memory devices, with each data block corresponding to one flash memory device. Identify the target flash memory device as the computing engine; A verification command is sent to the target flash memory device so that the target flash memory device performs data calculations on several data blocks based on the second memory mapping relationship to generate and store verification data; The verification command includes an update verification data command, which includes the offset address and data length of the first data block in the host memory buffer, the logical address of the unupdated data block in its respective flash memory device, and the logical address corresponding to the updated verification data. The method further includes: Update at least one of the data blocks to obtain at least one first data block; Store the first data block to the corresponding flash memory device; A command to update verification data is sent to the target flash memory device, so that the target flash memory device performs data calculations on the unupdated data blocks in the first data block and stripe data based on the first memory mapping relationship and the second memory mapping relationship, so as to generate and store the updated verification data.

2. The method according to claim 1, characterized in that, Each of the aforementioned flash memory devices includes a memory buffer mapping area for storing at least one of the data blocks; The verification command includes a write verification data command, which includes the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data. The establishment of the second memory mapping relationship between the host system and each of the flash memory devices includes: A host memory buffer is allocated in the memory of the host system. The host memory buffer is used to store striped data, wherein the striped data is divided into several data blocks. The host memory buffer is mapped to the storage space of each flash memory device to establish a mapping relationship between the host memory buffer and the memory buffer mapping area of ​​each flash memory device; Sending a verification command to the target flash memory device, so that the target flash memory device performs data calculations on several data blocks based on the second memory mapping relationship to generate and store verification data, includes: A write verification command is sent to the target flash memory device so that the target flash memory device performs data calculations on several data blocks in the memory buffer mapping area to generate and store verification data.

3. The method according to claim 1, characterized in that, The method further includes: When any of the data blocks is corrupted, a data recovery command is sent to the target flash memory device so that the target flash memory device can recover the corrupted data block based on the first memory mapping relationship and the second memory mapping relationship, and generate a second data block; Based on the second memory mapping relationship, obtain the second data block; The data recovery command includes the logical address of the third data block in the corresponding flash memory device, the logical address of the verification data, and the destination storage offset address of the second data block in the host memory buffer. The third data block includes undamaged data blocks in the striped data, and the second data block is the data block obtained after the damaged data block is recovered.

4. A host system, characterized in that, The host system, using the data management method as described in any one of claims 1-3, comprises: The processor system, connected to the host memory system, is used to divide a stripe of data into several data blocks and transfer the data blocks to the host memory system; The host memory system, connected to the processor system, is used to store the data blocks.

5. A method for verifying data, applied to a storage array, characterized in that, The storage array includes multiple flash memory devices, each of which has a first memory mapping relationship with the other flash memory devices, each of which is communicatively connected to a host system, and each of which has a second memory mapping relationship with the host system. The method includes: Based on the verification command sent by the host system and the second memory mapping relationship, data calculations are performed on several data blocks to generate and store verification data. The verification data is directly stored in the flash memory medium by the target flash memory device. The verification command and the data blocks are obtained by the data management method according to any one of claims 1-3.

6. The method according to claim 5, characterized in that, The verification command includes a command to write verification data. The host system includes a host memory buffer for storing striped data, wherein the striped data is divided into several data blocks. Each of the aforementioned flash memory devices includes a memory buffer mapping area for storing at least one of the data blocks; The second memory mapping relationship includes the mapping relationship between the host system's host memory buffer and the memory buffer mapping area of ​​each flash memory device; The step of performing data calculations on several data blocks based on the verification command sent by the host system and the second memory mapping relationship to generate and store verification data includes: Receive and parse the write verification data command to obtain the offset address and data length of each data block in the host memory buffer, as well as the logical address corresponding to the verification data; Based on the second memory mapping relationship, the offset address and data length of each data block in the host memory buffer, several data blocks corresponding to the striped data are obtained; Within the memory buffer mapping area of ​​the target flash memory device, perform an XOR operation on all data blocks of the stripe data to obtain the parity data corresponding to the stripe data. The verification data is stored in a flash memory medium using the logical address corresponding to the verification data as a storage index.

7. The method according to claim 6, characterized in that, The first memory mapping relationship includes the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffer of other flash memory devices. The method further includes: A read-write storage buffer is partitioned in the memory of each of the aforementioned flash memory devices, wherein the read-write storage buffer is used to store data blocks read from the flash memory medium; The read / write storage buffer is mapped to the storage space of each of the remaining flash memory devices to establish a mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffers of other flash memory devices. The read / write storage buffer mapping area is used to store data blocks from other flash memory devices. The first memory mapping relationship includes the mapping relationship between the read / write storage buffer mapping area of ​​each flash memory device and the read / write storage buffers of other flash memory devices.

8. The method according to claim 7, characterized in that, The method further includes: The first data block is obtained based on the update verification data command sent by the host system and the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area. Based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices, obtain the data blocks that have not been updated in the stripe data; Data calculations are performed on the first data block and the unupdated data blocks in the strip data to generate and store updated verification data, wherein the update verification data command and the first data block are obtained by the data management method of claim 1.

9. The method according to claim 8, characterized in that, The process of obtaining the first data block based on the update verification data command sent by the host system and the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area includes: Receive and parse the update verification data command to obtain the offset address and data length of the first data block in the host memory buffer, the logical address of the unupdated data blocks in their respective flash memory devices, and the logical address corresponding to the updated verification data; Based on the mapping relationship between the host system's host memory buffer and the target flash memory device's memory buffer mapping area, the offset address and data length of the first data block in the host memory buffer, the first data block is obtained.

10. The method according to claim 7, characterized in that, The method further includes: Based on the data recovery command sent by the host system and the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices, a third data block is obtained, wherein the third data block includes undamaged data blocks in the striped data; Based on the third data block and the verification data, data recovery is performed on the damaged data block, wherein the data recovery command and the third data block are obtained by the data management method of claim 3.

11. The method according to claim 10, characterized in that, The process of obtaining the third data block based on the data recovery command sent by the host system and the mapping relationship between the read / write storage buffer of the target flash memory device and the read / write storage buffers of other flash memory devices includes: Receive and parse the data recovery command to obtain the logical address of the third data block in the corresponding flash memory device, the logical address of the verification data, and the destination storage offset address of the second data block in the host memory buffer. A second read command is sent to each flash memory device storing a third data block to obtain the address of each third data block in the read / write storage buffer of the corresponding flash memory device, wherein the second read command includes the logical address of the third data block in the corresponding flash memory device; Based on the mapping relationship between the read / write storage buffer mapping area of ​​the target flash memory device and the read / write storage buffer of other flash memory devices, and the address of each third data block in the read / write storage buffer of the corresponding flash memory device, each third data block is obtained through point-to-point operation; The step of recovering the damaged data block based on the third data block and the verification data includes: Based on the logical address corresponding to the verification data, the verification data is read from the flash memory medium of the target flash memory device; In the read / write storage buffer mapping area of ​​the target flash memory device, a plurality of the third data blocks and the verification data are XORed to obtain the second data block, and the second data block is transmitted to the destination storage offset address of the host memory buffer.

12. A storage array, characterized in that, The method for verifying data as described in any one of claims 5-11, wherein the storage array comprises a plurality of flash memory devices; Each of the aforementioned flash memory devices includes: Independent disk redundant array engine; At least one flash memory medium is communicatively connected to the independent disk redundant array engine.

13. A distributed independent disk redundancy array system, characterized in that, include: The host system as described in claim 4; The storage array as described in claim 12, wherein, The host system is connected to the storage array via a communication bus.

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