A method for obtaining high-density nanoscale lines

Abstract

This invention relates to a method for obtaining high-density nanoscale lines, belonging to the field of semiconductor technology. It solves the problem of high manufacturing costs associated with the use of expensive extreme ultraviolet (EUV) lithography machines to reduce the width of the sacrificial layer in existing technologies. The method includes the following steps: sequentially forming a dielectric layer and an amorphous silicon layer on a substrate; irradiating a mask with a laser to crystallize silicon in a portion of the amorphous silicon layer, wherein the grain boundaries of the polycrystalline silicon formed after silicon crystallization in the amorphous silicon layer are determined by the spacing of regularly shaped apertures on the mask; planarizing the grain boundaries of the polycrystalline silicon in the amorphous silicon layer; removing the grain boundaries using an etchant to form grain boundary trenches; and forming a sacrificial layer using the grain boundary trenches, and obtaining nanoscale lines on the substrate using a sidewall transfer method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for obtaining high-density nanoscale lines. Background Technology

[0002] Integrated circuit linewidth refers to the minimum size that can be lithographically reproduced, determined by a specific process. It can generally be understood as the minimum line width in the fabricated circuit pattern. There is a corresponding relationship between integration density and linewidth; that is, the higher the integration density, the smaller the linewidth. Therefore, linewidth is often used to indicate the level of integrated circuit manufacturing technology.

[0003] As integrated circuit dimensions continue to shrink, it is necessary to continuously reduce the width of lithographic lines and the spacing between lines to improve integration density. An important method is to use sidewall transfer to obtain fine lines. The line width is determined by the thickness of the sidewalls, while the line spacing is determined by the width of the sacrificial layer covering the sidewalls. The width of the sacrificial layer is generally limited by the capabilities of the lithography machine. The industry uses expensive extreme ultraviolet (EUV) lithography technology to reduce the width of the sacrificial layer, resulting in high manufacturing costs. Summary of the Invention

[0004] Based on the above analysis, the present invention aims to provide a method for obtaining high-density nanoscale lines to solve the problem of high manufacturing costs associated with using expensive extreme ultraviolet (EUV) lithography machines to reduce the width of the sacrificial layer.

[0005] This invention provides a method for obtaining high-density nanoscale lines, comprising the following steps:

[0006] A dielectric layer and an amorphous silicon layer are sequentially formed on top of the substrate;

[0007] A laser is used to irradiate a mask to crystallize silicon in a portion of the amorphous silicon layer. The grain boundaries of the polycrystalline silicon formed after the crystallization of the portion of the amorphous silicon layer are determined by the spacing of the orifices with regular shapes on the mask.

[0008] The grain boundaries of the polycrystalline silicon in the amorphous silicon layer are planarized.

[0009] The grain boundaries are removed using an etchant to form grain boundary trenches; and

[0010] A sacrificial layer is formed using the grain boundary trenches, and nanoscale lines are obtained on the substrate using a sidewall transfer method.

[0011] Based on a further improvement of the above method, the material of the dielectric layer is silicon nitride.

[0012] The beneficial effects of the above-mentioned further improvement plan are:

[0013] Silicon nitride materials have good silicon wettability, which can reduce the nucleation rate during the crystallization process and promote lateral growth.

[0014] Based on a further improvement of the above method, the substrate material is silicon or silicon dioxide.

[0015] Based on a further improvement to the above method, the planarization treatment of the grain boundaries of the polycrystalline silicon in the amorphous silicon layer includes:

[0016] Silicon dioxide is deposited on the amorphous silicon layer;

[0017] The silicon dioxide on the polycrystalline silicon is removed using a chemical mechanical polishing process; and

[0018] The remaining surface silica on the amorphous silicon layer is removed using an acidic etching solution.

[0019] Based on a further improvement of the above method, the step of forming a sacrificial layer using the grain boundary trenches and obtaining nanoscale lines on the substrate using a sidewall transfer method includes:

[0020] A silicon dioxide film is filled over the polycrystalline silicon to cover the grain boundary trenches;

[0021] The surface silicon dioxide on the polycrystalline silicon is removed by chemical mechanical polishing or reverse etching.

[0022] The polycrystalline silicon is removed using an alkaline silicon etching solution, leaving the silicon dioxide filling the grain boundary trenches;

[0023] Using silicon dioxide within the grain boundary trench as a hard mask, the dielectric layer is etched and the etching stops on the substrate surface;

[0024] A silicon dioxide thin film is deposited to cover the substrate and the etched dielectric layer, and the surface silicon dioxide on the substrate and the etched dielectric layer is removed using a chemical mechanical polishing process or reverse etching; and

[0025] The dielectric layer is removed using an acidic etching solution, leaving sidewall silica, which is then used as a hard mask to etch nanoscale lines onto the substrate.

[0026] Based on a further improvement of the above method, the step of filling the grain boundary trench with a silicon dioxide thin film over the polycrystalline silicon includes:

[0027] The grain boundary trenches are covered by a silicon dioxide film filled over the polycrystalline silicon using an atomic layer deposition (ALD) process.

[0028] Based on a further improvement of the above method, the alkaline silicon etching solution is a tetramethylammonium hydroxide solution or a potassium hydroxide solution.

[0029] Based on a further improvement of the above method, the etchant is a Secco etchant.

[0030] Based on further improvements to the above method, the energy density of the laser is 100 millijoules per square centimeter to 2 joules per square centimeter.

[0031] Based on a further improvement of the above method, the width of the sacrificial layer is less than 10 nanometers.

[0032] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0033] 1. This invention proposes a method for reducing the width of the sacrificial layer based on laser technology, thereby reducing the frequency of use of EUV lithography machines, lowering manufacturing costs, and enabling the acquisition of high-density nanoscale lines at a lower manufacturing cost, thus improving integration.

[0034] 2. After filling the grain boundary trench, it can be used as a hard mask material for subsequent pattern transfer. Its thickness is mainly determined by the thickness of the polycrystalline silicon thin film, unlike the photolithography process, where the photoresist thickness decreases as the linewidth decreases.

[0035] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0036] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0037] Figure 1 This is a flowchart illustrating a method for obtaining high-density nanoscale lines according to an embodiment of the present invention.

[0038] Figure 2 A schematic diagram of a laser-irradiated mask according to an embodiment of the present invention is shown.

[0039] Figure 3-1 An example of a grain boundary of polycrystalline silicon formed according to an embodiment of the present invention is shown.

[0040] Figure 3-2 Another example of a grain boundary of polycrystalline silicon formed according to an embodiment of the present invention is shown.

[0041] Figure 3-3 A conceptual structural diagram of silicon dioxide deposited on an amorphous silicon layer 30 according to an embodiment of the present invention is shown.

[0042] Figure 3-4 A conceptual structural schematic diagram of silicon dioxide removal on polycrystalline silicon 70 using a chemical mechanical polishing process according to an embodiment of the present invention is shown.

[0043] Figure 4 An example of a planarized polycrystalline silicon grain boundary is shown according to an embodiment of the present invention.

[0044] Figure 5 An example of obtaining lines using the sidewall transfer method according to this embodiment is shown.

[0045] Figure 6 An example of nanoscale lines obtained on a substrate according to this embodiment is shown.

[0046] Figure 7 A conceptual structural schematic diagram is shown of filling a silicon dioxide thin film over polycrystalline silicon 70 to cover grain boundary trenches.

[0047] Figure 8 A conceptual structural diagram is shown after removing the surface silicon dioxide on polycrystalline silicon 70 using a chemical mechanical polishing process or reverse etching.

[0048] Figure 9 A conceptual structural diagram is shown after polysilicon 70 has been removed using an alkaline silicon etching solution.

[0049] Figure 10 A conceptual structural diagram is shown, illustrating the etching of the dielectric layer 20 using silicon dioxide within grain boundary trenches as a hard mask, stopping at the surface of the substrate 10.

[0050] Figure 11 A conceptual structural schematic diagram of a substrate 10 covered by a deposited silicon dioxide thin film and an etched dielectric layer 20 is shown.

[0051] Figure 12 A conceptual structural schematic diagram is shown, illustrating the removal of surface silicon dioxide on substrate 10 and etched dielectric layer 20 using chemical mechanical polishing or reverse etching.

[0052] Figure 13 A conceptual structural diagram is shown showing the removal of the dielectric layer 20 using an acidic etching solution, leaving the sidewall silica.

[0053] Figure 14 A conceptual structural schematic diagram is shown, illustrating the etching of nanoscale lines 80 on a substrate 10 using sidewall silica as a hard mask.

[0054] Figure 15 A process flow for obtaining high-density nanoscale lines according to an embodiment of the present invention is shown.

[0055] Figure label:

[0056] 10 - Substrate; 20 - Dielectric layer; 30 - Amorphous silicon layer; 40 - Mask; 50 - Circular hole; 60 - Crystalline silicon; 70 - Polycrystalline silicon; 80 - Fine line. Detailed Implementation

[0057] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0058] Figure 1 This is a flowchart illustrating a method for obtaining high-density nanoscale lines according to an embodiment of the present invention.

[0059] The following is combined with Figure 1 An embodiment of the present invention will be described.

[0060] like Figure 1 As shown, the method for obtaining this high-density nanoscale line includes:

[0061] Step 101: A dielectric layer and an amorphous silicon layer are sequentially formed on top of the substrate.

[0062] In this embodiment, the substrate material can be silicon or silicon dioxide, and a dielectric layer can be grown on the substrate using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The dielectric layer material can be silicon nitride, which has good silicon wettability, can reduce the nucleation rate during crystallization, and promote lateral growth.

[0063] In this embodiment, an amorphous silicon layer can be grown over the dielectric layer using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or reduced-pressure chemical vapor deposition (RPCVD).

[0064] In some embodiments, a thickness of 10 to 1000 Å (angstroms) for the dielectric layer and the amorphous silicon layer is advantageous.

[0065] Step 102: Use a laser to irradiate the mask to crystallize silicon in a portion of the amorphous silicon layer, wherein the grain boundaries of the polycrystalline silicon formed after the partial crystallization of the amorphous silicon layer are determined by the spacing of the orifices with regular shapes on the mask.

[0066] Figure 2 A schematic diagram of a laser-irradiated mask according to this embodiment is shown. Figure 2 As shown, the photomask 40 may have multiple circular holes 50. When the photomask 40 is irradiated with a laser, a portion of the amorphous silicon 60 on the amorphous silicon layer 30 is in a near-molten state. When the amorphous silicon 60 solidifies in the near-molten state, it undergoes lateral growth to form grain boundaries of polycrystalline silicon. The width of the grain boundaries is determined by the spacing of the circular holes 50 on the photomask 40.

[0067] It should be noted that since the apertures on the photomask 40 are circular, the near-molten amorphous silicon 60 under laser irradiation is also circular. Therefore, the amorphous silicon 60 can grow uniformly in all directions. When these growing amorphous silicon particles touch, they stop growing and form grain boundaries between polycrystalline silicon particles. Because the amorphous silicon 60 grows uniformly in all directions, when the circular apertures on the photomask are regularly distributed, the resulting polycrystalline silicon grain boundaries will be regular rectangles. Therefore, both a regular shape of the apertures on the photomask and a regular distribution between the apertures are advantageous.

[0068] In some embodiments, it is advantageous that the energy density of laser melting crystallization is between 100 millijoules per square centimeter and 2 joules per square centimeter, which can be achieved by adjusting the laser power.

[0069] Step 103: Planarize the grain boundaries of the polycrystalline silicon in the amorphous silicon layer.

[0070] Figure 3-1 An example of a grain boundary of polycrystalline silicon formed in step 102 according to this embodiment is shown, by Figure 3-1 As can be seen, protrusions may appear at the grain boundaries of polycrystalline silicon. In order to make the surface of the crystallized film smoother, the grain boundaries of polycrystalline silicon need to be planarized in step 103.

[0071] In some preferred embodiments, the planarization of the grain boundaries of polycrystalline silicon can be performed using the following process:

[0072] Silicon dioxide is deposited on the amorphous silicon layer 30;

[0073] The silicon dioxide on the polycrystalline silicon is removed using a chemical mechanical polishing process; and

[0074] The remaining surface silica on the amorphous silicon layer 30 is removed using an acidic etching solution.

[0075] In the above embodiments, a silicon dioxide layer with a thickness of 10–100 nm can be deposited on the amorphous silicon layer 30. Subsequently, the surface of the crystalline film is planarized using a chemical mechanical polishing process. Finally, the surface silicon dioxide on the amorphous silicon layer 30 is etched using an acidic etchant such as hydrofluoric acid.

[0076] The following is combined with Figures 3-2 to 3-4 The preferred embodiments described above will be explained.

[0077] Figure 3-2 Another example of a grain boundary of polycrystalline silicon formed according to step 102 of this embodiment is shown. For example... Figure 3-2 As shown, during the lateral growth of molten silicon, collisions occur with silicon growing from adjacent directions, causing the lateral growth to terminate and forming grain boundaries. The crystallized surface is not completely flat; at the grain boundaries, collisions from growth in opposite directions create a series of protrusions, thus requiring planarization treatment of the polycrystalline silicon grain boundaries. Figures 3-3 to 3-4 It shows the Figure 3-2 The process flow for planarizing the grain boundaries in the grain.

[0078] Figure 3-3 A conceptual structural diagram is shown after silicon dioxide is deposited on the amorphous silicon layer 30. Figure 3-3 The thickness of the deposited silica can be 10–100 nm.

[0079] Figure 3-4 A conceptual structural diagram is shown illustrating the removal of silicon dioxide from polycrystalline silicon 70 using a chemical mechanical polishing (CMP) process. CMP removes protrusions and smooths the surface.

[0080] Because in Figure 3-3 In the process shown, silicon dioxide will also be deposited on the remaining portion of the amorphous silicon layer 30 (i.e., the surface area outside the polycrystalline silicon 70), so the following process will be performed: using an acidic etching solution to remove the surface silicon dioxide on the remaining portion of the amorphous silicon layer 30.

[0081] Step 104: Use an etchant to remove the grain boundaries to form grain boundary trenches.

[0082] In this embodiment, Secco etching solution (a mixture of potassium dichromate, hydrofluoric acid and water) can be used for grain boundary etching.

[0083] It should be noted that Secco etching solution can etch amorphous silicon. Since the crystal orientation in the grain boundary is not uniform, the grain boundary is also a type of amorphous silicon. When Secco etching solution is used for grain boundary etching, the amorphous silicon layer 30 is also etched away, leaving polycrystalline silicon 70.

[0084] Figure 4 An example of a planarized polycrystalline silicon grain boundary is shown according to the preferred embodiment described above. By removing the grain boundary protrusions formed during laser crystallization, the resulting grain boundaries can be made smoother and more regular.

[0085] Step 105: A sacrificial layer is formed using the grain boundary trenches, and nanoscale lines are obtained on the substrate using a sidewall transfer method.

[0086] Figure 5 An example of obtaining lines via a sidewall transfer method according to this embodiment is shown, such as... Figure 5 As shown, the width of the lines is determined by the thickness of the sidewalls, and the spacing between the lines is determined by the width of the sacrificial layer covered by the sidewalls. In this embodiment, the sacrificial layer is formed by grain boundary trenches, and the sidewalls can cover the grain boundary trenches. By using the sidewall transfer method, sidewalls with a width on the nanoscale can be obtained. Then, the substrate is etched using the nanoscale sidewalls as a mask, thereby obtaining nanoscale lines on the substrate.

[0087] Figure 6 An example of nanoscale lines obtained on a substrate according to this embodiment is shown. Figure 6 As shown, the material of the fine line 80 is the same as that of the substrate 10, and the width of the fine line 80 is determined by the thickness of the sidewall of the grain boundary trench.

[0088] Compared with existing technologies, the method for obtaining high-density nanoscale lines provided in this embodiment proposes a method for reducing the width of the sacrificial layer based on laser technology, thereby reducing the frequency of use of EUV lithography machines, reducing manufacturing costs, and obtaining high-density nanoscale lines at a lower manufacturing cost, thus improving integration.

[0089] In some embodiments, the dielectric layer in step 101 may be made of silicon nitride. Silicon nitride has good silicon wettability, which can reduce the nucleation rate during crystallization and promote lateral growth.

[0090] In some embodiments, the substrate material in step 101 can be silicon or silicon dioxide. Damascus structures were previously mainly used in metal interconnect processes, resulting in relatively large dimensions and heavy reliance on photolithography machines. The above technical solution utilizes damascus structures to obtain hard mask materials with fine lines. The trenches in the damascus structure are obtained by etching to remove grain boundaries, and their dimensions can be as small as less than 20 nanometers, comparable to extreme ultraviolet lithography machines.

[0091] In some embodiments, step 105 may include the following steps:

[0092] S10: Fill the polycrystalline silicon with a silicon dioxide film to cover the grain boundary trench.

[0093] Figure 7 A conceptual structural diagram is shown illustrating a silicon dioxide film filling a grain boundary trench over polycrystalline silicon 70. In some embodiments, an atomic layer deposition (ALD) process can be used to fill the grain boundary trench with silicon dioxide, the silicon dioxide extending above the grain boundary trench and forming a silicon dioxide film on the polycrystalline silicon. It should be noted that since the grain boundary trenches of the polycrystalline silicon 70 can reach the nanometer scale, using an ALD process to fill the silicon dioxide is advantageous.

[0094] S20: Remove the surface silicon dioxide on the polycrystalline silicon using a chemical mechanical polishing process or reverse etching.

[0095] Figure 8 A conceptual structural diagram is shown after removing the surface silicon dioxide on polycrystalline silicon 70 using a chemical mechanical polishing process or reverse etching.

[0096] S30: Use an alkaline silicon etching solution to remove the polycrystalline silicon, leaving the silicon dioxide filling the grain boundary trenches.

[0097] Figure 9 A conceptual structural diagram of polycrystalline silicon 70 after removal using an alkaline silicon etchant is shown. In some embodiments, the alkaline silicon etchant may be a tetramethylammonium hydroxide solution or a potassium hydroxide solution.

[0098] S40: Using silicon dioxide within the grain boundary trench as a hard mask, etch the dielectric layer and stop at the substrate surface.

[0099] Figure 10 A conceptual structural diagram is shown, illustrating the etching of the dielectric layer 20 using silicon dioxide within grain boundary trenches as a hard mask, stopping at the surface of the substrate 10.

[0100] S50: Deposit a silicon dioxide thin film to cover the substrate and the etched dielectric layer, and remove the surface silicon dioxide on the substrate and the etched dielectric layer using a chemical mechanical polishing process or reverse etching.

[0101] Figure 11 A conceptual structural schematic diagram of a substrate 10 covered by a deposited silicon dioxide thin film and an etched dielectric layer 20 is shown.

[0102] Figure 12A conceptual structural schematic diagram is shown, illustrating the removal of surface silicon dioxide on substrate 10 and etched dielectric layer 20 using chemical mechanical polishing or reverse etching.

[0103] S60: Use an acidic etching solution to remove the dielectric layer, leaving sidewall silica, and use the sidewall silica as a hard mask to etch nanoscale lines on the substrate.

[0104] Figure 13 A conceptual structural diagram is shown showing the removal of the dielectric layer 20 using an acidic etching solution, leaving the sidewall silica.

[0105] Figure 14 A conceptual structural schematic diagram is shown, illustrating the etching of nanoscale lines 80 on a substrate 10 using sidewall silica as a hard mask.

[0106] In the embodiments described above in conjunction with steps S10-S60, the grain boundary trenches, after being filled, can be used as hard mask materials for subsequent pattern transfer. Their thickness is mainly determined by the thickness of the polycrystalline silicon thin film, unlike the photolithography process, where the photoresist thickness decreases as the linewidth decreases.

[0107] Figure 15 A process flow for obtaining high-density nanoscale lines according to an embodiment of the present invention is shown. The following is in conjunction with... Figure 15 Please provide an explanation.

[0108] like Figure 15 As shown, in step 1501, silicon nitride is grown to a thickness between 10 and 1000 Å. In step 1502, amorphous silicon is grown to a thickness between 10 and 1000 Å, using methods such as PECVD, LPCVD, and RPCVD. In step 1503, laser melting crystallization is performed using a laser irradiation mask, with the laser energy density ranging from 100 millijoules per square centimeter to 2 joules per square centimeter. In step 1504, silicon dioxide is deposited and removed using a chemical mechanical polishing (CMP) process. In step 1505, the surface silicon dioxide is etched using an acidic etchant. In step 1506, grain boundary etching is performed using a Secco etchant. In step 1507, a silicon dioxide film is filled into the grain boundaries and the surface silicon dioxide is removed using a CMP process or reverse etching. In step 1508, polycrystalline silicon is removed using an alkaline silicon etchant. In step 1509, silicon nitride is etched using silicon dioxide as a hard mask material, leaving a sacrificial layer. In step 1510, silicon dioxide is deposited again and a sidewall transfer method is used to leave sidewall silicon dioxide. In step 1511, silicon lines are etched using the sidewall silicon dioxide as a mask material.

[0109] The above text combined Figure 15The described embodiments have at least the following beneficial technical effects:

[0110] 1. Reducing the frequency of EUV lithography machine use lowers manufacturing costs, allowing for the production of high-density nanoscale lines at a lower cost, thus improving integration.

[0111] 2. After filling the grain boundary trench, it can be used as a hard mask material for subsequent pattern transfer. Its thickness is mainly determined by the thickness of the polycrystalline silicon thin film, unlike the photolithography process, where the photoresist thickness decreases as the linewidth decreases.

[0112] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for obtaining high-density nanometer-scale lines, characterized in that, Includes the following steps: A dielectric layer and an amorphous silicon layer are sequentially formed on top of the substrate; A laser is used to irradiate a mask to crystallize silicon in a portion of the amorphous silicon layer. The grain boundaries of the polycrystalline silicon formed after the crystallization of the portion of the amorphous silicon layer are determined by the spacing of the orifices with regular shapes on the mask. The grain boundaries of the polycrystalline silicon in the amorphous silicon layer are planarized. The grain boundaries are removed using an etchant to form grain boundary trenches; and A sacrificial layer is formed using the grain boundary trenches, and nanoscale lines are obtained on the substrate using a sidewall transfer method.

2. The method for obtaining high-density nanoscale lines according to claim 1, wherein the step of forming a sacrificial layer using the grain boundary trenches and obtaining nanoscale lines on the substrate using a sidewall transfer method comprises: A silicon dioxide film is filled over the polycrystalline silicon to cover the grain boundary trenches; The surface silicon dioxide on the polycrystalline silicon is removed by chemical mechanical polishing or reverse etching. The polycrystalline silicon is removed using an alkaline silicon etching solution, leaving the silicon dioxide filling the grain boundary trenches; Using silicon dioxide within the grain boundary trench as a hard mask, the dielectric layer is etched and the etching stops on the substrate surface; A silicon dioxide thin film is deposited to cover the substrate and the etched dielectric layer, and the surface silicon dioxide on the substrate and the etched dielectric layer is removed by chemical mechanical polishing or reverse etching. as well as The dielectric layer is removed using an acidic etching solution, leaving sidewall silica, which is then used as a hard mask to etch nanoscale lines onto the substrate.

3. The method for obtaining high-density nanoscale lines according to claim 1, wherein the material of the dielectric layer is silicon nitride.

4. The method for obtaining high-density nanoscale lines according to claim 1, wherein the substrate material is silicon or silicon dioxide.

5. The method for obtaining high-density nanoscale lines according to claim 1, wherein the planarization treatment of the grain boundaries of the polycrystalline silicon in the amorphous silicon layer comprises: Silicon dioxide is deposited on the amorphous silicon layer; The silicon dioxide on the polycrystalline silicon is removed using a chemical mechanical polishing process; as well as The remaining surface silica on the amorphous silicon layer is removed using an acidic etching solution.

6. The method for obtaining high-density nanoscale lines according to claim 2, wherein filling the grain boundary trenches with a silicon dioxide thin film over the polycrystalline silicon comprises: The grain boundary trenches are covered by a silicon dioxide film filled over the polycrystalline silicon using an atomic layer deposition (ALD) process.

7. The method for obtaining high-density nanoscale lines according to claim 2, wherein the alkaline silicon etching solution is a tetramethylammonium hydroxide solution or a potassium hydroxide solution.

8. The method for obtaining high-density nanoscale lines according to claim 1 or 2, wherein the etching solution is Secco etching solution.

9. The method for obtaining high-density nanoscale lines according to claim 1 or 2, wherein the energy density of the laser is from 100 millijoules per square centimeter to 2 joules per square centimeter.

10. The method for obtaining high-density nanoscale lines according to claim 1 or 2, wherein the width of the sacrificial layer is less than 10 nanometers.

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