Information security-based data processing acceleration method and device, equipment and medium
By generating a gold sequence in the FPGA chip for bilateral sampling and high-speed clock processing, the issues of information security and processing speed are solved, achieving a balance between data processing acceleration and security.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG INSPUR SCI RES INST CO LTD
- Filing Date
- 2023-11-13
- Publication Date
- 2026-07-24
AI Technical Summary
Existing technologies cannot improve the information processing speed of FPGA chips while ensuring information security, and the clock frequency of basic peripherals cannot meet the demand for higher clock frequencies.
By generating a target gold sequence for bilateral sampling, and utilizing a first-in-first-out queue, data splicing components, and decryption components, combined with a high-speed clock frequency for data processing, encryption, and decryption operations, rapid data transmission and processing are achieved.
While ensuring information security, the operating frequency and processing efficiency of the FPGA chip were increased, thereby improving the speed of data processing.
Smart Images
Figure CN117560142B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of information transmission and information encryption, and in particular to a data processing acceleration method, apparatus, device, and medium based on information security. Background Technology
[0002] FPGA (Field Programmable Gate Array) is a further development based on programmable devices such as PAL (Programmable Array Logic) and GAL (Generic Array Logic). It emerged as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), addressing the shortcomings of custom circuits while overcoming the limited gate count of earlier programmable devices. With technological advancements, FPGA chips are becoming increasingly integrated and faster in transmitting and receiving information. These faster transmission and reception requirements necessitate higher clock frequencies and operating frequencies. However, compared to other types of chip design, FPGA chip design typically requires a higher barrier to entry and a more rigorous basic design flow. The clock frequencies of existing basic peripherals are insufficient to meet the demands for higher clock frequencies, and information security is a crucial aspect of information transmission. Furthermore, current technology struggles to simultaneously increase information processing speed while ensuring information security. Summary of the Invention
[0003] In view of this, the purpose of this invention is to provide a data processing acceleration method, apparatus, device, and medium based on information security, which can effectively accelerate the data processing flow while ensuring information security. The specific solution is as follows:
[0004] In a first aspect, this application discloses a data processing acceleration method based on information security, applied to an FPGA chip, comprising:
[0005] Determine the encryption key corresponding to the target data sent by the local central processing unit, and generate the target gold sequence based on the encryption key and the target data;
[0006] The target gold sequence is sampled on both sides to obtain rising edge sampled data and falling edge sampled data, and the rising edge sampled data and falling edge sampled data are sent to a preset first-in-first-out queue.
[0007] The rising edge sampled data and the falling edge sampled data are sent to the local data splicing component through the preset first-in-first-out queue based on the preset phase difference and preset clock frequency.
[0008] The local data splicing component receives the rising edge sampling data and the falling edge sampling data based on a preset first high-speed clock, and splices the rising edge sampling data and the falling edge sampling data to obtain the target spliced data.
[0009] The local data splicing component sends the target spliced data to the local decryption component based on the preset first high-speed clock, so that the local decryption component can decrypt the target spliced data based on the preset second high-speed clock and the encryption cipher.
[0010] Optionally, determining the encryption cipher corresponding to the target data sent by the local central processing unit, and generating the target gold sequence based on the encryption cipher and the target data, includes:
[0011] A first m-sequence is generated based on the target data sent by the local central processing unit, and the encryption cipher corresponding to the target data is determined, so as to generate a second m-sequence based on the encryption cipher;
[0012] The first m-sequence and the second m-sequence are XORed to encrypt the target data, resulting in the target gold sequence.
[0013] Optionally, the step of performing bilateral sampling on the target gold sequence to obtain rising edge sampled data and falling edge sampled data, and sending the rising edge sampled data and the falling edge sampled data to a preset first-in-first-out queue, includes:
[0014] The target gold sequence is sampled bilaterally based on a preset timer. If the current value of the preset timer is the value of the first timer, rising edge sampling data is collected through the first path. If the current value of the preset timer is the value of the second timer, falling edge sampling data is collected through the second path.
[0015] Based on a preset communication protocol, the rising edge sampled data is sent to the first first-in-first-out queue, and the falling edge sampled data is sent to the second first-in-first-out queue.
[0016] Optionally, the step of sending the rising edge sampled data and the falling edge sampled data to the local data splicing component through the preset first-in-first-out queue based on a preset phase difference and a preset clock frequency includes:
[0017] Determine the preset clock frequency and preset phase difference, and determine the first transmission period corresponding to the first first-in-first-out queue and the second transmission period corresponding to the second first-in-first-out queue based on the preset phase difference;
[0018] The rising edge sampled data is sent to the local data splicing component using the first first-in-first-out queue based on the preset clock frequency and the first transmission period, and the falling edge sampled data is sent to the local data splicing component using the second first-in-first-out queue based on the preset clock frequency and the second transmission period.
[0019] Optionally, the step of receiving the rising edge sampled data and the falling edge sampled data based on a preset first high-speed clock through the local data splicing component, and splicing the rising edge sampled data and the falling edge sampled data to obtain the target spliced data includes:
[0020] A first high-speed clock frequency corresponding to a preset high-speed clock is determined, so that the rising edge sampling data and the falling edge sampling data are received by the local data splicing component based on the first high-speed clock frequency, and the rising edge sampling data and the falling edge sampling data are spliced together to obtain target spliced data.
[0021] Optionally, the step of sending the target concatenated data to the local decryption component based on the preset first high-speed clock by the local data concatenation component, so that the local decryption component can decrypt the target concatenated data based on the preset second high-speed clock and the encryption cipher, includes:
[0022] The target spliced data is sent to the local decryption component based on the first high-speed clock frequency by the local data splicing component.
[0023] A second high-speed clock frequency corresponding to a preset second high-speed clock is determined, so that the target spliced data can be decrypted by a local decryption component based on the second high-speed clock frequency and the encryption cipher.
[0024] Optionally, the step of decrypting the target concatenated data using a local decryption component based on the second high-speed clock frequency and the encryption cipher includes:
[0025] The target spliced data is decrypted using the encryption cipher based on the second high-speed clock frequency. The decrypted data is then subjected to an XOR operation and an inverse operation to restore the target spliced data back to the target data. The target data is then reported to the target host computer.
[0026] Secondly, this application discloses a data processing acceleration device based on information security, applied to an FPGA chip, comprising:
[0027] A sequence generation module is used to determine the encryption key corresponding to the target data sent by the local central processing unit, and to generate a target gold sequence based on the encryption key and the target data;
[0028] The data sampling module performs bilateral sampling on the target gold sequence to obtain rising edge sampling data and falling edge sampling data, and sends the rising edge sampling data and the falling edge sampling data to a preset first-in-first-out queue.
[0029] The data transmission module is used to transmit the rising edge sampled data and the falling edge sampled data to the local data splicing component through the preset first-in-first-out queue based on a preset phase difference and a preset clock frequency;
[0030] The data splicing module is used to receive the rising edge sampling data and the falling edge sampling data based on a preset first high-speed clock through the local data splicing component, and splice the rising edge sampling data and the falling edge sampling data to obtain target spliced data;
[0031] The data decryption module is used to send the target spliced data to the local decryption component based on the preset first high-speed clock through the local data splicing component, so that the local decryption component can decrypt the target spliced data based on the preset second high-speed clock and the encryption cipher.
[0032] Thirdly, this application discloses an electronic device, comprising:
[0033] Memory, used to store computer programs;
[0034] A processor for executing the computer program to implement the aforementioned information security-based data processing acceleration method.
[0035] Fourthly, this application discloses a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the aforementioned data processing acceleration method based on information security.
[0036] In this application, firstly, it is necessary to determine the encryption code corresponding to the target data sent by the local central processing unit, and generate a target gold sequence based on the encryption code and the target data; then, the target gold sequence is sampled bilaterally to obtain rising edge sampled data and falling edge sampled data, and the rising edge sampled data and the falling edge sampled data are sent to a preset first-in-first-out queue; the preset first-in-first-out queue sends the rising edge sampled data and the falling edge sampled data to a local data splicing component based on a preset phase difference and a preset clock frequency; the local data splicing component receives the rising edge sampled data and the falling edge sampled data based on a preset first high-speed clock, and splices the rising edge sampled data and the falling edge sampled data to obtain target spliced data; finally, the local data splicing component sends the target spliced data to a local decryption component based on the preset first high-speed clock, so that the local decryption component can decrypt the target spliced data based on a preset second high-speed clock and the encryption code. Therefore, the method of this application, upon receiving target data sent by the FPGA chip's local central processing unit, needs to determine the encryption key corresponding to the target data, generate a golden sequence based on the encryption key and the target data, perform bilateral sampling on the golden sequence, and send the sampled data to a preset first-in-first-out (FIFO) queue. The FIFO queue then sends the sampling frequency to a local data splicing component based on a preset phase difference and a preset clock frequency for splicing the sampled data. The spliced data is then sent to a local decryption component based on a first high-speed clock, which decrypts the data using a second high-speed clock. This effectively accelerates the data processing flow while ensuring information security, increases the chip's operating frequency, and thus improves the chip's processing efficiency. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0038] Figure 1 A flowchart of a data processing acceleration method based on information security is provided for this application;
[0039] Figure 2 A timing diagram of the sending end of a data processing acceleration method based on information security provided in this application;
[0040] Figure 3 This application provides a schematic diagram of m-sequence generation;
[0041] Figure 4 This application provides a schematic diagram of an m-sequence XOR operation;
[0042] Figure 5 A schematic diagram of a data transmission frequency provided in this application;
[0043] Figure 6 A timing diagram of the receiver end for a data processing acceleration method based on information security provided in this application;
[0044] Figure 7 A flowchart of a specific data processing acceleration method based on information security is provided in this application;
[0045] Figure 8 A schematic diagram of a data processing acceleration device based on information security is provided for this application;
[0046] Figure 9 This application provides a structural diagram of an electronic device. Detailed Implementation
[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0048] The existing basic peripherals have insufficient clock speeds to meet the demand for higher clock speeds. Furthermore, information security is a crucial aspect of information transmission, and current technologies are insufficient to improve information processing speed while ensuring information security.
[0049] To address the aforementioned technical problems, this application provides a data processing acceleration method, apparatus, device, and medium based on information security, which can effectively accelerate the data processing flow while ensuring information security.
[0050] See Figure 1 As shown, this embodiment of the invention discloses a data processing acceleration method based on information security, applied to an FPGA chip, comprising:
[0051] Step S11: Determine the encryption key corresponding to the target data sent by the local central processing unit, and generate the target gold sequence based on the encryption key and the target data.
[0052] In this embodiment, after the FPGA chip's CPU (Central Processing Unit) sends the target data, the target data needs to be processed to generate a corresponding gold sequence. The specific process is as follows: A first m-sequence is generated based on the target data sent by the local CPU, and the encryption key corresponding to the target data is determined to generate a second m-sequence based on the encryption key; the first m-sequence and the second m-sequence are XORed to encrypt the target data, obtaining the target gold sequence. That is, as shown... Figure 2 As shown, after the CPU sends the target data, it needs to generate two m-sequences based on the target data. These m-sequences are implemented using an LFSR (Linear Feedback Shift Register). This register has the following characteristics: if the initial states are the same, the final output sequence will be the same; the output sequence is close to a random sequence; after a certain number of iterations, the values of the initial states will be the same, and the maximum repetition interval can be calculated using 2^n-1, where n is the number of shift registers. Figure 3 As shown, this illustrates the specific method for generating the m-sequence. Each flip-flop ai (i = 1, 2, ..., r) forms a shift register, representing the XOR operation. C0, C1, C2, ..., C r These are the feedback coefficients, and also the coefficients of the characteristic polynomial. A coefficient value of 1 indicates that the feedback branch is connected, and 0 indicates that the feedback branch is disconnected. For an m-sequence generator, the general expression for its characteristic polynomial is f(x) = C0x. 0 +C1x 1 +C2x 2 +...+C r x r The coefficients of the characteristic polynomial determine the characteristic polynomial of an m-sequence, and thus also determine the m-sequence itself. A 4-bit m-sequence generator can be used. Since C1 and C4 are fixed values, only C2 and C3 need to be assigned values to determine the base. For example, assigning C3 to 0 and C2 to 1 (i.e., C4C3C2C1 = 1011) determines the base as binary. After determining the C values, the data enters the shift register and begins a loop. After the loop completes, the m-sequence is formed. It should be noted that the first m-sequence is generated based on the target data sent by the CPU, and the second m-sequence is the key, which contains the encryption key of the original data. Then, the m-sequence is generated. If the number of shift registers for the two sequences is the same, then the two sequences are... Figure 4 Performing an XOR operation bit by bit as shown will produce a gold sequence, also known as a gold sequence.
[0053] Step 12: Perform bilateral sampling on the target gold sequence to obtain rising edge sampling data and falling edge sampling data, and send the rising edge sampling data and the falling edge sampling data to a preset first-in-first-out queue.
[0054] In this embodiment, after obtaining the gold sequence, bilateral sampling of the gold sequence is required. The specific process is as follows: Bilateral sampling of the target gold sequence is performed based on a preset timer. If the current value of the preset timer is the value of the first timer, rising edge sampling data is collected through the first path; if the current value of the preset timer is the value of the second timer, falling edge sampling data is collected through the second path. The rising edge sampling data is sent to the first first-in-first-out queue and the falling edge sampling data is sent to the second first-in-first-out queue based on a preset communication protocol. That is, it is necessary to form two paths, the first path and the second path, based on the bilateral sampling feature of the SPI (Serial Peripheral interface) bus protocol. The first path collects rising edge sampling data, and the second path collects falling edge sampling data. This is implemented by a counter (cnt), which is a cyclic count of 0101. When the counter is 0, the data is sent to the first path; when the counter is 1, the data is sent to the second path. Path 1 and Path 2 share one clock cycle. It should be noted that the transmission method is the SPI protocol, and data is transmitted through the SPI protocol. Specifically, the rising edge sampling data of the first path needs to be sent to the first first-in-first-out queue FIFO1, and the falling edge sampling data of the second path needs to be sent to the second first-in-first-out queue FIFO2.
[0055] Step S13: The rising edge sampled data and the falling edge sampled data are sent to the local data splicing component through the preset first-in-first-out queue based on the preset phase difference and preset clock frequency.
[0056] In this embodiment, after obtaining rising edge and falling edge sampled data through bilateral sampling, the sampled data needs to be sent to the first-in-first-out (FIFO) queues for processing. The specific process is as follows: a preset clock frequency and a preset phase difference are determined, and a first transmission period corresponding to the first FIFO queue and a second transmission period corresponding to the second FIFO queue are determined based on the preset phase difference. The first FIFO queue sends the rising edge sampled data to the local data splicing component based on the preset clock frequency and the first transmission period, and the second FIFO queue sends the falling edge sampled data to the local data splicing component based on the preset clock frequency and the second transmission period. That is, two FIFO queues, i.e., two FIFOs, are needed for data reception of the first and second paths. After data reception is completed, both FIFO1 and FIFO2 send data to the data acquisition module in a rising edge sampling manner. It should be noted that FIFO1 needs to be one phase ahead of FIFO2, i.e., FIFO1 needs to send data one period ahead. Therefore, the transmission period of the two FIFO queues can be determined by the phase difference, and the transmission clock frequency can be determined according to the SPI protocol. Furthermore, by utilizing the phase difference, the data from FIFO1 and FIFO2 can be cyclically fed into the data splicing function to achieve data splicing.
[0057] Step S14: The local data splicing component receives the rising edge sampling data and the falling edge sampling data based on a preset first high-speed clock, and splices the rising edge sampling data and the falling edge sampling data to obtain the target spliced data.
[0058] In this embodiment, a high-speed clock can be set during data reception, and the sampled data sent by FIFO1 and FIFO2 can be received using the frequency corresponding to the high-speed clock. It should be noted that, to achieve processing acceleration, the clock frequency for data reception, i.e., the frequency corresponding to the high-speed clock, should be as follows: Figure 5 The clock frequency is multiplied by the clock frequency of the data transmission. Then, the rising edge sampled data and the falling edge sampled data are obtained based on the first high-speed clock frequency corresponding to the high-speed clock. The rising edge sampled data and the falling edge sampled data are then spliced together to obtain the target spliced data.
[0059] Step S15: The local data splicing component sends the target spliced data to the local decryption component based on the preset first high-speed clock, so that the local decryption component can decrypt the target spliced data based on the preset second high-speed clock and the encryption cipher.
[0060] In this embodiment, after the data splicing component completes the data splicing, the target spliced data corresponding to the rising edge sampled data and the falling edge sampled data can be obtained. However, both the rising edge sampled data and the falling edge sampled data are obtained by sampling the gold sequence, and the gold sequence is encrypted data. Therefore, the target spliced data also needs to be decrypted to restore the data. Furthermore, since the data splicing component increases the operating frequency, the decryption component can be set to a high-speed clock, using a higher operating frequency for faster decoding. Decryption requires using the encryption cipher corresponding to the second m sequence to decrypt the target spliced data, and further restore the decrypted data to the target data originally sent by the CPU. Further, as... Figure 6 As shown, the original data can be reported to the host computer, thus completing the entire encryption and decryption process. This accelerates data transmission during encrypted information transmission.
[0061] Therefore, this application first needs to determine the encryption code corresponding to the target data sent by the local central processing unit, and generate a target gold sequence based on the encryption code and the target data; then, the target gold sequence is sampled bilaterally to obtain rising edge sampled data and falling edge sampled data, and the rising edge sampled data and the falling edge sampled data are sent to a preset first-in-first-out queue; the preset first-in-first-out queue sends the rising edge sampled data and the falling edge sampled data to a local data splicing component based on a preset phase difference and a preset clock frequency; the local data splicing component receives the rising edge sampled data and the falling edge sampled data based on a preset first high-speed clock, and splices the rising edge sampled data and the falling edge sampled data to obtain target spliced data; finally, the local data splicing component sends the target spliced data to a local decryption component based on the preset first high-speed clock, so that the local decryption component can decrypt the target spliced data based on a preset second high-speed clock and the encryption code. Therefore, the method of this application, upon receiving target data sent by the FPGA chip's local central processing unit, needs to determine the encryption key corresponding to the target data, generate a golden sequence based on the encryption key and the target data, perform bilateral sampling on the golden sequence, and send the sampled data to a preset first-in-first-out (FIFO) queue. The FIFO queue then sends the sampling frequency to a local data splicing component based on a preset phase difference and a preset clock frequency for splicing the sampled data. The spliced data is then sent to a local decryption component based on a first high-speed clock, which decrypts the data using a second high-speed clock. This effectively accelerates the data processing flow while ensuring information security, increases the chip's operating frequency, and thus improves the chip's processing efficiency.
[0062] As can be seen from the foregoing embodiments, in order to accelerate data processing, different high-speed clocks can be set, and data transmission and reception can be performed based on the clock frequency of the high-speed clock. Furthermore, it is necessary to decrypt the spliced data based on encrypted data to restore the data. Therefore, this embodiment provides a detailed explanation of how to achieve accelerated data processing and data decryption. (See [link to documentation]). Figure 5 As shown, this embodiment of the invention discloses a data processing acceleration method based on information security, comprising:
[0063] Step S21: Determine the encryption key corresponding to the target data sent by the local central processing unit, and generate the target gold sequence based on the encryption key and the target data.
[0064] Step 22: Perform bilateral sampling on the target gold sequence to obtain rising edge sampling data and falling edge sampling data, and send the rising edge sampling data and the falling edge sampling data to a preset first-in-first-out queue.
[0065] Step S23: The rising edge sampled data and the falling edge sampled data are sent to the local data splicing component through the preset first-in-first-out queue based on the preset phase difference and preset clock frequency.
[0066] Step S24: Determine the first high-speed clock frequency corresponding to the preset high-speed clock, so as to receive the rising edge sampling data and the falling edge sampling data based on the first high-speed clock frequency through the local data splicing component, and splice the rising edge sampling data and the falling edge sampling data to obtain the target spliced data.
[0067] In this embodiment, a high-speed clock needs to be set in the data splicing component to receive data. In this embodiment, it is called the first high-speed clock. When receiving data, it is necessary to receive data based on the first high-speed clock frequency corresponding to the set first high-speed clock to improve the main frequency of operation. Furthermore, since the first-in-first-out queue needs to send data based on a preset phase difference, the data from the first and second first-in-first-out queues can be cyclically entered into the data splicing component so that the data splicing component can splice the data. It should be noted that the data splicing is to restore the transmitted single-bit data to multi-bit data.
[0068] Step S25: The target spliced data is sent to the local decryption component based on the first high-speed clock frequency by the local data splicing component.
[0069] In this embodiment, after the data splicing process is completed, the spliced data needs to be sent to the decryption component so that the decryption component can decrypt the spliced data and restore the data. Specifically, the spliced data can be sent to the decryption component according to the set first high-speed clock frequency corresponding to the first high-speed clock.
[0070] Step S26: Determine the second high-speed clock frequency corresponding to the preset second high-speed clock, so as to decrypt the target spliced data by the local decryption component based on the second high-speed clock frequency and the encryption cipher.
[0071] In this embodiment, to achieve faster decoding, a high-speed clock can be set in the decryption component, referred to as the second high-speed clock in this embodiment. After receiving the target concatenated data, the data is decrypted using the second high-speed clock frequency corresponding to the second high-speed clock. It should be noted that the local decryption component decrypts the target concatenated data based on the second high-speed clock frequency and the encryption cipher, including: decrypting the target concatenated data using the encryption cipher based on the second high-speed clock frequency, performing an XOR operation and an inverse operation on the decrypted data to restore the target concatenated data to the target data, and then reporting the target data to the target host computer. That is, the data decryption module needs a corresponding key for decryption, and the decryption key is the encryption cipher corresponding to the second m-sequence. Due to the characteristics of XOR, the original sequence can be derived from the result and one set of numbers. Therefore, the first m-sequence is restored using the second m-sequence corresponding to the key. Furthermore, the m-sequence can generate the initial data after a certain number of iterations. Therefore, based on the original key, a comparison can be made, and the m-sequence can be reversed. When the value is the same as the key, the number of registers can be deduced. Then, the number of registers and the register configuration information contained in the key are substituted into the m-sequence of the original data, and the m-sequence is reversed to obtain the original data, which is the target data sent by the CPU. This allows for accelerated data transmission while ensuring data security.
[0072] Therefore, in this embodiment, a first high-speed clock frequency corresponding to a preset high-speed clock is first determined. The local data splicing component receives the rising edge sampled data and the falling edge sampled data based on the first high-speed clock frequency, and splices the rising edge sampled data and the falling edge sampled data to obtain the target spliced data. Then, the local data splicing component sends the target spliced data to the local decryption component based on the first high-speed clock frequency. Finally, a second high-speed clock frequency corresponding to a preset second high-speed clock is determined, and the local decryption component decrypts the target spliced data based on the second high-speed clock frequency and the encryption cipher. In this way, the chip's main frequency efficiency can be further improved by setting a high-speed clock, and the data can be restored to the target data sent by the CPU, i.e., the original data, through data decryption, XOR operation, and inverse operation. This achieves accelerated data transmission while ensuring data security.
[0073] See Figure 8 As shown, this embodiment of the invention discloses a data processing acceleration device based on information security, applied to an FPGA chip, comprising:
[0074] The sequence generation module 11 is used to determine the encryption key corresponding to the target data sent by the local central processing unit, and generate a target gold sequence based on the encryption key and the target data;
[0075] The data sampling module 12 performs bilateral sampling on the target gold sequence to obtain rising edge sampling data and falling edge sampling data, and sends the rising edge sampling data and the falling edge sampling data to a preset first-in-first-out queue.
[0076] Data transmission module 13 is used to transmit the rising edge sampled data and the falling edge sampled data to the local data splicing component through the preset first-in-first-out queue based on a preset phase difference and a preset clock frequency;
[0077] The data splicing module 14 is used to receive the rising edge sampling data and the falling edge sampling data based on a preset first high-speed clock through the local data splicing component, and splice the rising edge sampling data and the falling edge sampling data to obtain target spliced data.
[0078] The data decryption module 15 is used to send the target spliced data to the local decryption component based on the preset first high-speed clock through the local data splicing component, so that the local decryption component can decrypt the target spliced data based on the preset second high-speed clock and the encryption cipher.
[0079] Therefore, this application first needs to determine the encryption code corresponding to the target data sent by the local central processing unit, and generate a target gold sequence based on the encryption code and the target data; then, the target gold sequence is sampled bilaterally to obtain rising edge sampled data and falling edge sampled data, and the rising edge sampled data and the falling edge sampled data are sent to a preset first-in-first-out queue; the preset first-in-first-out queue sends the rising edge sampled data and the falling edge sampled data to a local data splicing component based on a preset phase difference and a preset clock frequency; the local data splicing component receives the rising edge sampled data and the falling edge sampled data based on a preset first high-speed clock, and splices the rising edge sampled data and the falling edge sampled data to obtain target spliced data; finally, the local data splicing component sends the target spliced data to a local decryption component based on the preset first high-speed clock, so that the local decryption component can decrypt the target spliced data based on a preset second high-speed clock and the encryption code. Therefore, the method of this application, upon receiving target data sent by the FPGA chip's local central processing unit, needs to determine the encryption key corresponding to the target data, generate a golden sequence based on the encryption key and the target data, perform bilateral sampling on the golden sequence, and send the sampled data to a preset first-in-first-out (FIFO) queue. The FIFO queue then sends the sampling frequency to a local data splicing component based on a preset phase difference and a preset clock frequency for splicing the sampled data. The spliced data is then sent to a local decryption component based on a first high-speed clock, which decrypts the data using a second high-speed clock. This effectively accelerates the data processing flow while ensuring information security, increases the chip's operating frequency, and thus improves the chip's processing efficiency.
[0080] In some embodiments, the sequence generation module 11 may specifically include:
[0081] A sequence generation unit is used to generate a first m-sequence based on target data sent by a local central processing unit, and to determine the encryption key corresponding to the target data, so as to generate a second m-sequence based on the encryption key;
[0082] A sequence processing unit is used to perform XOR processing on the first m-sequence and the second m-sequence to encrypt the target data and obtain the target gold sequence.
[0083] In some embodiments, the data sampling module 12 may specifically include:
[0084] The data sampling unit is used to perform bilateral sampling on the target gold sequence based on a preset timer. If the current value of the preset timer is the value of the first timer, rising edge sampling data is collected through the first path. If the current value of the preset timer is the value of the second timer, falling edge sampling data is collected through the second path.
[0085] The first data transmission unit is used to send the rising edge sampled data to the first first-in-first-out queue and the falling edge sampled data to the second first-in-first-out queue based on a preset communication protocol.
[0086] In some embodiments, the data sending module 13 may specifically include:
[0087] The period determination unit is used to determine a preset clock frequency and a preset phase difference, and to determine the first transmission period corresponding to the first first-in-first-out queue and the second transmission period corresponding to the second first-in-first-out queue based on the preset phase difference.
[0088] The second data transmission unit is used to send the rising edge sampled data to the local data splicing component using the first first-in-first-out queue based on the preset clock frequency and the first transmission period, and to send the falling edge sampled data to the local data splicing component using the second first-in-first-out queue based on the preset clock frequency and the second transmission period.
[0089] In some embodiments, the data splicing module 14 may specifically include:
[0090] The data splicing unit is used to determine a first high-speed clock frequency corresponding to a preset high-speed clock, so as to receive the rising edge sampling data and the falling edge sampling data based on the first high-speed clock frequency through the local data splicing component, and splice the rising edge sampling data and the falling edge sampling data to obtain target spliced data.
[0091] In some embodiments, the data decryption module 15 may specifically include:
[0092] The third data transmission unit is used to send the target spliced data to the local decryption component based on the first high-speed clock frequency through the local data splicing component;
[0093] The data decryption submodule is used to determine the second high-speed clock frequency corresponding to the preset second high-speed clock, so as to decrypt the target spliced data by the local decryption component based on the second high-speed clock frequency and the encryption cipher.
[0094] In some embodiments, the data decryption submodule may specifically include:
[0095] The data decryption unit is used to decrypt the target spliced data based on the second high-speed clock frequency using the encryption cipher, and to perform XOR operation and inverse operation on the decrypted data to restore the target spliced data to the target data, and to report the target data to the target host computer.
[0096] Furthermore, embodiments of this application also disclose an electronic device, Figure 9 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.
[0097] Figure 9 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the information security-based data processing acceleration method disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.
[0098] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission path between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0099] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0100] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the information security-based data processing acceleration method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include computer programs capable of performing other specific tasks.
[0101] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned data processing acceleration method based on information security. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0102] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0103] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0104] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0105] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0106] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A data processing acceleration method based on information security, characterized in that, Applied to FPGA chips, including: Determine the encryption key corresponding to the target data sent by the local central processing unit, and generate the target gold sequence based on the encryption key and the target data; The target gold sequence is sampled on both sides to obtain rising edge sampled data and falling edge sampled data, and the rising edge sampled data and the falling edge sampled data are sent to a preset first-in-first-out queue. The rising edge sampled data and the falling edge sampled data are sent to the local data splicing component through the preset first-in-first-out queue based on the preset phase difference and preset clock frequency. The local data splicing component receives the rising edge sampling data and the falling edge sampling data based on a preset first high-speed clock, and splices the rising edge sampling data and the falling edge sampling data to obtain the target spliced data. The local data splicing component sends the target spliced data to the local decryption component based on the preset first high-speed clock, so that the local decryption component can decrypt the target spliced data based on the preset second high-speed clock and the encryption cipher. The step of performing bilateral sampling on the target gold sequence to obtain rising edge sampling data and falling edge sampling data, and sending the rising edge sampling data and the falling edge sampling data to a preset first-in-first-out queue, includes: The target gold sequence is sampled bilaterally based on a preset timer. If the current value of the preset timer is the value of the first timer, rising edge sampling data is collected through the first path. If the current value of the preset timer is the value of the second timer, falling edge sampling data is collected through the second path. The rising edge sampled data is sent to the first first-in-first-out queue based on a preset communication protocol, and the falling edge sampled data is sent to the second first-in-first-out queue; the preset communication protocol is the SPI protocol; The step of sending the rising edge sampled data and the falling edge sampled data to the local data splicing component through the preset first-in-first-out queue based on a preset phase difference and a preset clock frequency includes: A preset clock frequency and a preset phase difference are determined, and a first transmission period corresponding to the first first-in-first-out queue and a second transmission period corresponding to the second first-in-first-out queue are determined based on the preset phase difference; the first transmission period is one phase ahead of the second transmission period. The rising edge sampled data is sent to the local data splicing component using the first first-in-first-out queue based on the preset clock frequency and the first transmission period, and the falling edge sampled data is sent to the local data splicing component using the second first-in-first-out queue based on the preset clock frequency and the second transmission period.
2. The data processing acceleration method based on information security according to claim 1, characterized in that, The step of determining the encryption key corresponding to the target data sent by the local central processing unit, and generating the target gold sequence based on the encryption key and the target data, includes: A first m-sequence is generated based on the target data sent by the local central processing unit, and the encryption cipher corresponding to the target data is determined, so as to generate a second m-sequence based on the encryption cipher; The first m-sequence and the second m-sequence are XORed to encrypt the target data, resulting in the target gold sequence.
3. The data processing acceleration method based on information security according to any one of claims 1 or 2, characterized in that, The step of receiving the rising edge sampled data and the falling edge sampled data based on a preset first high-speed clock through the local data splicing component, and splicing the rising edge sampled data and the falling edge sampled data to obtain the target spliced data includes: A first high-speed clock frequency corresponding to a preset high-speed clock is determined, so that the rising edge sampling data and the falling edge sampling data are received by the local data splicing component based on the first high-speed clock frequency, and the rising edge sampling data and the falling edge sampling data are spliced together to obtain target spliced data.
4. The data processing acceleration method based on information security according to claim 3, characterized in that, The step of sending the target concatenated data to the local decryption component via the local data concatenation component based on the preset first high-speed clock, so that the local decryption component can decrypt the target concatenated data based on the preset second high-speed clock and the encryption cipher, includes: The target spliced data is sent to the local decryption component based on the first high-speed clock frequency by the local data splicing component. A second high-speed clock frequency corresponding to a preset second high-speed clock is determined, so that the target spliced data can be decrypted by a local decryption component based on the second high-speed clock frequency and the encryption cipher.
5. The data processing acceleration method based on information security according to claim 4, characterized in that, The step of decrypting the target concatenated data using a local decryption component based on the second high-speed clock frequency and the encryption cipher includes: The target spliced data is decrypted using the encryption cipher based on the second high-speed clock frequency. The decrypted data is then subjected to an XOR operation and an inverse operation to restore the target spliced data back to the target data. The target data is then reported to the target host computer.
6. A data processing acceleration device based on information security, characterized in that, Applied to FPGA chips, including: A sequence generation module is used to determine the encryption key corresponding to the target data sent by the local central processing unit, and to generate a target gold sequence based on the encryption key and the target data; The data sampling module performs bilateral sampling on the target gold sequence to obtain rising edge sampling data and falling edge sampling data, and sends the rising edge sampling data and the falling edge sampling data to a preset first-in-first-out queue. The data transmission module is used to transmit the rising edge sampled data and the falling edge sampled data to the local data splicing component through the preset first-in-first-out queue based on a preset phase difference and a preset clock frequency; The data splicing module is used to receive the rising edge sampling data and the falling edge sampling data based on a preset first high-speed clock through the local data splicing component, and splice the rising edge sampling data and the falling edge sampling data to obtain target spliced data; The data decryption module is used to send the target spliced data to the local decryption component based on the preset first high-speed clock through the local data splicing component, so that the local decryption component can decrypt the target spliced data based on the preset second high-speed clock and the encryption cipher; The data sampling module includes: The data sampling unit is used to perform bilateral sampling on the target gold sequence based on a preset timer. If the current value of the preset timer is the value of the first timer, rising edge sampling data is collected through the first path. If the current value of the preset timer is the value of the second timer, falling edge sampling data is collected through the second path. The first data transmission unit is used to send the rising edge sampled data to the first first-in-first-out queue and the falling edge sampled data to the second first-in-first-out queue based on a preset communication protocol; the preset communication protocol is the SPI protocol. The data sending module includes: The period determination unit is used to determine a preset clock frequency and a preset phase difference, and to determine a first transmission period corresponding to the first first-in-first-out queue and a second transmission period corresponding to the second first-in-first-out queue based on the preset phase difference; the first transmission period is one phase ahead of the second transmission period. The second data transmission unit is used to send the rising edge sampled data to the local data splicing component using the first first-in-first-out queue based on the preset clock frequency and the first transmission period, and to send the falling edge sampled data to the local data splicing component using the second first-in-first-out queue based on the preset clock frequency and the second transmission period.
7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the information security-based data processing acceleration method as described in any one of claims 1 to 5.
8. A computer-readable storage medium, characterized in that, Used to store computer programs, which, when executed by a processor, implement the data processing acceleration method based on information security as described in any one of claims 1 to 5.