Quantum device verification complexity determination method and device, electronic device and medium

Abstract

The present disclosure provides a method, apparatus, electronic device, computer-readable storage medium and computer program product for determining the complexity of quantum device performance verification, which relates to the field of quantum computers, and in particular to the field of quantum local verification technology. The implementation scheme is as follows: obtaining the target quantum state that needs to be generated by the quantum device to be verified; obtaining the initial value of the first matrix Ω used to characterize the performance verification strategy of the quantum device; based on the first matrix Ω and the target quantum state, determining the target optimization function corresponding to the performance verification strategy, the target optimization function includes the target function and the constraint function, the target function is determined based on the second largest eigenvalue of the first matrix Ω, and the constraint function includes the first function for constraining the performance verification strategy to be a positive partial transposition operation; optimizing the first matrix Ω based on the target optimization function, so as to determine the lower limit of the number of experiments required to perform performance verification on the quantum device through the performance verification strategy based on the value of the optimized first matrix Ω.

Description

Technical Field

[0001] The present disclosure relates to the field of quantum computers, in particular to the field of quantum local verification technology, and specifically to a method, apparatus, electronic device, computer-readable storage medium and computer program product for determining the complexity of quantum device performance verification. Background Art

[0002] Quantum entanglement has very important applications in the fields of quantum computing and quantum information processing. Inaccurate quantum entangled states will significantly affect the results of quantum computing and quantum information processing. Therefore, before using quantum devices to generate entangled states, it is necessary to complete quantum device performance verification to ensure the quality of entanglement. Performance verification of quantum devices requires a large number of repeated experiments to reduce the probability of false assertions. The more experiments are conducted, the more time and quantum state resources are consumed. Summary of the invention

[0003] The present disclosure provides a method, apparatus, electronic device, computer-readable storage medium, and computer program product for determining the complexity of quantum device performance verification.

[0004] According to one aspect of the present disclosure, a method for determining the complexity of quantum device performance verification is provided, including: obtaining a target quantum state that needs to be generated by a quantum device to be verified; obtaining an initial value of a first matrix Ω used to characterize a performance verification strategy of the quantum device, wherein the first matrix Ω has the same dimension as the target quantum state, and 0≤Ω≤I, and I is a unit matrix; determining a target optimization function corresponding to the performance verification strategy based on the first matrix Ω and the target quantum state, wherein the target optimization function includes an objective function and a constraint function, wherein the objective function is determined based on the second largest eigenvalue of the first matrix Ω, and the constraint function includes a first function for constraining the performance verification strategy to be a positive partial transpose (PPT) operation; optimizing the first matrix Ω based on the objective optimization function to determine the value of the optimized first matrix Ω; and determining a lower limit of the number of experiments required for performance verification of the quantum device through the performance verification strategy based on the value of the optimized first matrix Ω.

[0005] According to another aspect of the present disclosure, a complexity determination apparatus for quantum device performance verification is provided, comprising: a first acquisition unit, configured to acquire a target quantum state that needs to be generated by a quantum device to be verified; a second acquisition unit, configured to acquire an initial value of a first matrix Ω used to characterize a performance verification strategy of the quantum device, wherein the first matrix Ω has the same dimension as the target quantum state, and 0≤Ω≤I, where I is a unit matrix; a first determination unit, configured to determine a target optimization function corresponding to the performance verification strategy based on the first matrix Ω and the target quantum state, wherein the target optimization function includes a target function and a constraint function, wherein the target function is determined based on the second largest eigenvalue of the first matrix Ω, and the constraint function includes a first function for constraining the performance verification strategy to be a positive partial transpose (PPT) operation; an optimization unit, configured to optimize the first matrix Ω based on the target optimization function to determine a value of the optimized first matrix Ω; and a second determination unit, configured to determine a lower limit of the number of experiments required for performance verification of the quantum device through the performance verification strategy based on the value of the optimized first matrix Ω.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method described in the present disclosure.

[0007] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method described in the present disclosure.

[0008] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements the method described in the present disclosure when executed by a processor.

[0009] According to one or more embodiments of the present disclosure, the number of experiments required for quantum device performance verification can be efficiently estimated, and the estimated number of experiments given is also an effective estimate of the resource consumption for quantum state verification while meeting preset confidence requirements. This is crucial in actual verification scenarios and facilitates effective adjustment of the number of experiments to achieve effective savings in computing resources while meeting preset confidence requirements.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings exemplarily illustrate the embodiments and constitute a part of the specification, and together with the text description of the specification, are used to explain the exemplary implementation of the embodiments. The embodiments shown are for illustrative purposes only and do not limit the scope of the claims. In all drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0012] Figure 1 A flowchart of a method for determining the complexity of quantum device performance verification according to an embodiment of the present disclosure is shown;

[0013] Figure 2 A schematic diagram showing performance verification of a quantum device according to an embodiment of the present disclosure is shown;

[0014] Figure 3 A structural block diagram of a complexity determination apparatus for quantum device performance verification according to an embodiment of the present disclosure is shown; and

[0015] Figure 4 A structural block diagram of an exemplary electronic device that can be used to implement the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0016] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0017] In the present disclosure, unless otherwise specified, the use of the terms "first", "second", etc. to describe various elements is not intended to limit the positional relationship, timing relationship, or importance relationship of these elements, and such terms are only used to distinguish one element from another element. In some examples, the first element and the second element may refer to the same instance of the element, and in some cases, based on the description of the context, they may also refer to different instances.

[0018] The terms used in the description of various examples in this disclosure are only for the purpose of describing specific examples and are not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element can be one or more. In addition, the term "and / or" used in this disclosure covers any one of the listed items and all possible combinations.

[0019] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0020] So far, all the different types of computers in use are based on classical physics as the theoretical basis for information processing, and are called traditional computers or classical computers. Classical information systems use binary data bits, which are the easiest to implement physically, to store data or programs. Each binary data bit is represented by 0 or 1, called a bit or bit, as the smallest unit of information. Classical computers themselves have inevitable weaknesses: one is the most basic limitation of energy consumption in the computing process. The minimum energy required for logic elements or storage units should be several times more than kT to avoid misoperation due to thermal expansion and fall; the second is information entropy and heat energy consumption; the third is that when the wiring density of computer chips is very high, according to the Heisenberg uncertainty relation, when the uncertainty of the electron position is very small, the uncertainty of the momentum will be very large. Electrons are no longer bound, and there will be quantum interference effects, which may even destroy the performance of the chip.

[0021] A quantum computer is a physical device that follows the properties and laws of quantum mechanics to perform high-speed mathematical and logical operations, store and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Quantum computers follow the unique laws of quantum dynamics (especially quantum interference) to achieve a new mode of information processing. For parallel processing of computational problems, quantum computers have an absolute advantage in speed over classical computers. The transformation of each superposition component by a quantum computer is equivalent to a classical calculation. All these classical calculations are completed at the same time and superimposed according to a certain probability amplitude to give the output result of the quantum computer. This calculation is called quantum parallel computing. Quantum parallel processing greatly improves the efficiency of quantum computers, allowing them to complete tasks that classical computers cannot complete, such as factoring a large natural number. Quantum coherence is essentially used in all quantum ultra-fast algorithms. Therefore, quantum parallel computing, which replaces classical states with quantum states, can achieve computing speeds and information processing functions that are incomparable to classical computers, while saving a lot of computing resources.

[0022] Quantum computing based on quantum computers is the core of the next generation of computing technology. More and more emerging quantum technologies are emerging, the technology of quantum hardware is improving year by year, and quantum communication and quantum Internet are also developing. One of the most important resources of quantum technology is quantum entanglement, which is the core resource and basic component of quantum computing and quantum information processing. It is the core part of many famous quantum information processing cases, such as quantum key distribution, quantum superdense coding, and quantum teleportation.

[0023] Taking quantum super-dense coding as an example, the relevant quantum protocol is as follows: Alice and Bob, the two parties in the protocol communication, pre-share a pair of highly entangled Bell states; Alice performs corresponding quantum coding operations on the quantum bits she holds according to the two bits of classical information that need to be transmitted, and then transmits the quantum bit after the operation to Bob through an ideal quantum channel; Bob performs Bell measurement on the received quantum bits and the quantum bits originally held, and decodes the two bits of classical information transmitted by Alice. Quantum super-dense coding cleverly uses the properties of quantum entanglement to transmit two classical bits of information through one quantum bit, thereby achieving a communication method with greater capacity and higher efficiency.

[0024] It can be seen from the quantum super-dense coding protocol that how to efficiently verify whether an unknown quantum device accurately produces Bell quantum states is a core problem in quantum computing (hereinafter referred to as the Bell state local verification problem). In addition, considering that the verification process itself cannot consume more and more stringent resources than the object to be verified (Bell state), the two parties involved in the verification are required to use only local quantum operations and classical communication (Local Operations and Classical Communication, LOCC) to complete the verification process through classical data post-processing.

[0025] Quantum entanglement has very important applications in the fields of quantum computing and quantum information processing. Inaccurate quantum entangled states will significantly affect the results of quantum computing and quantum information processing. Therefore, before using quantum devices, it is necessary to complete quantum device performance verification to ensure the quality of the generated entangled states. Quantum device performance verification requires a large number of repeated experiments to reduce the probability of false assertions. The more experiments are conducted, the more time and quantum state resources are consumed.

[0026] Therefore, according to an embodiment of the present disclosure, a method for determining the complexity of quantum device performance verification is provided. Figure 1 A flowchart of a method for determining the complexity of quantum device performance verification according to an embodiment of the present disclosure is shown, as shown in FIG. Figure 1As shown, method 100 includes: obtaining a target quantum state that needs to be generated by a quantum device to be verified (step 110); obtaining an initial value of a first matrix Ω used to characterize a performance verification strategy of the quantum device, wherein the first matrix Ω has the same dimension as the target quantum state, and 0≤Ω≤I, and I is a unit matrix (step 120); determining a target optimization function corresponding to the performance verification strategy based on the first matrix Ω and the target quantum state, wherein the target optimization function includes a target function and a constraint function, wherein the target function is determined based on the second largest eigenvalue of the first matrix Ω, and the constraint function includes a first function for constraining the performance verification strategy to be a positive partial transpose (PPT) operation (step 130); optimizing the first matrix Ω based on the target optimization function to determine a value of the optimized first matrix Ω (step 140); and determining a lower limit of the number of experiments required to perform performance verification on the quantum device through the performance verification strategy based on the value of the optimized first matrix Ω (step 150).

[0027] According to the embodiments of the present disclosure, the number of experiments required for quantum device performance verification can be efficiently estimated, and the estimated number of experiments given is also an effective estimate of the resource consumption for quantum state verification while meeting preset confidence requirements. This is crucial in actual verification scenarios and facilitates effective adjustment of the number of experiments to achieve effective savings in computing resources while meeting preset confidence requirements.

[0028] For example, for a quantum device that distributes quantum entangled states, and the quantum state distributed by the quantum device is nominally within an error of ε from |Ψ>, the quantum device can be experimentally verified through this information to determine whether it satisfies the nominal information. In this context, the method described in the embodiment of the present disclosure can give the number of experiments required for the experimental verification, and the number of experiments determines the minimum resource consumption required to verify the quantum device, that is, the complexity of verifying the problem.

[0029] It is understandable that the performance verification strategy for verifying the performance of the quantum device can be described by a corresponding verification matrix, wherein the verification matrix can characterize its verification process. For example, the performance verification strategy can be: generating a preset quantum state located on two quantum systems by the quantum device, and measuring the corresponding parts of the preset quantum state on the two quantum systems to obtain corresponding measurement results and transmitting the corresponding measurement results to each other through classical communication. The verification process is the method of using local quantum operations and classical communication (LOCC) as described above.

[0030] For example, for a quantum device D, each call to the device can generate a quantum state σ AB (It can be the quantum state of any quantum bit). It can be guaranteed that the device must belong to one of the following two cases: Good Case - the quantum device D accurately produces the target quantum state |Ψ>; Bad Case - the fidelity of the quantum state produced by the quantum device D and the target quantum state is less than or equal to 1-ε, that is, <Ψ|σ AB |Ψ>≤1-ε, where ε is the error value preset by the equipment manufacturer.

[0031] Before Alice and Bob perform quantum operations through the quantum device, they need to verify the performance of the quantum device D, that is, whether it is a Good Case or a Bad Case. Figure 2 A schematic diagram of quantum device performance verification according to an embodiment of the present disclosure is shown. In the above performance verification strategy, Alice and Bob perform verification by means of local quantum operations and classical communication (LOCC).

[0032] It is understandable that, in the embodiment according to the present disclosure, the initial value of the first matrix Ω obtained for characterizing the performance verification strategy of the quantum device can be any value, such as a unit matrix, as long as the dimension of the first matrix Ω is the same as that of the target quantum state and 0≤Ω≤I. The elements in the first matrix Ω can be adjusted. After the optimization is completed, the first matrix Ω obtained after optimization corresponds to a performance verification strategy, and verification of the quantum device by the performance verification strategy usually requires minimum resource consumption. Therefore, the lower limit of the number of experiments required for performance verification of the quantum device is determined by the method described in the present disclosure.

[0033] In some examples, in order to accurately determine whether the unknown quantum device produces the target quantum state |Ψ> through the above performance verification strategy, the following constraints can be further set: if the unknown quantum device does produce |Ψ>, the communicating parties Alice and Bob must always assert a Good Case (to ensure that it is not regarded as a bad product); if the unknown quantum measurement device does not produce |Ψ>, the probability of Alice and Bob mistakenly asserting a Good Case is as small as possible (to ensure that the probability of being regarded as a good product is as small as possible).

[0034] In some examples, Alice and Bob use random quantum measurements to further ensure the accuracy of the verification. If the quantum measurements are not randomly selected, the manufacturer can customize the quantum state that always passes the test based on the quantum measurement information used by Alice and Bob, thereby deceiving Alice and Bob.

[0035] Therefore, for a quantum device verification strategy Ω (a matrix that satisfies the condition 0≤Ω≤I, where I is the unit matrix), if it is a Bad Case, the probability that Alice and Bob mistakenly assert a Good Case can be expressed as 1-[1-β(Ω)]ε, where β(Ω) is the second largest eigenvalue of Ω and ε is the error tolerance of the preset quantum device. After N repeated experiments, the probability that Alice and Bob make a mistake will be [1-[1-β(Ω)]ε] N .

[0036] If the confidence level of errors in verifying the performance of quantum devices is set to δ, the confidence level of accepting errors is recorded. Then at least N experiments are required to complete the verification, where

[0037]

[0038] in, It represents the rounding of the real number x. Obviously, we hope that the number of experiments is as small as possible while verifying that the pre-selected confidence requirement is met. Considering that N is positively correlated with β(Ω), β(Ω) needs to be as small as possible.

[0039] It is hoped that the number of experiments is as small as possible under the condition that the verification meets the pre-selected confidence requirement. Considering that N is positively correlated with β(Ω), it is necessary that β(Ω) is as small as possible. Continuing with the above embodiment as an example, if we want to find the optimal performance verification strategy, that is:

[0040] β opt =minβ(Ω)

[0041] Satisfies: Ω|Ψ>=|Ψ>

[0042] 0≤Ω≤I

[0043] {Ω,I-Ω}∈LOCC

[0044] Among them, β opt This is the optimal solution for the above optimized performance verification strategy. The first condition above ensures that if it is a good case, Alice and Bob can always make correct assertions; the second condition ensures that Ω is a legal quantum verification strategy; the third condition is to limit the performance verification strategy to LOCC operation.

[0045] However, since LOCC is a very complex operation, it is very challenging to find the optimal strategy through the above optimization problem and obtain an estimate of the optimal number of experiments.

[0046] Therefore, in the embodiment according to the present disclosure, the LOCC operation is scaled to a positive partial transpose (PPT) operation with better characterization. Specifically, if a quantum operation X of Alice and Bob satisfies Then X is called PPT operation. It means to transpose the quantum system held by Bob, that is:

[0047]

[0048] Among them, |i> B ,|j> B Represents the computational basis vector in the Hilbert space where the quantum system held by Bob is located.

[0049] It can be proved that if a quantum operation Ω is a LOCC operation, then it must also be a PPT operation, so the range of PPT operations is wider than that of LOCC operations. This means that if we replace the LOCC operation of the restriction condition in the original optimization problem with the PPT operation, we will give a lower bound for the original optimization problem.

[0050] Therefore, the above performance verification strategy optimization problem can be rewritten as:

[0051] β opt =minβ(Ω)

[0052] Satisfies: Ω|Ψ>=|Ψ>

[0053] 0≤Ω≤I

[0054]

[0055]

[0056] Therefore, according to some embodiments, the lower limit M of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy may be determined based on the following formula:

[0057]

[0058] Among them, ε is the error tolerance of the quantum device, δ is the preset confidence level of errors in verifying the performance of the quantum device, and β(Ω) is the second largest eigenvalue of the optimized first matrix Ω.

[0059] According to some embodiments, a lower bound of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy may be determined using a solution algorithm for a semidefinite programming problem.

[0060] It can be understood that the reference value M of the number of experiments determined according to the above embodiment is the lower bound of the number of experiments required for any quantum device verification using the LOCC quantum strategy. The solution according to the above embodiment is applicable to quantum device verification of any two quantum states.

[0061] In addition, note the restriction condition Ω|Ψ>=|Ψ>, which means |Ψ> is an eigenvector of Ω, and the corresponding eigenvalue is 1. Then the second largest eigenvalue of the matrix Ω can be rewritten as:

[0062] β(Ω)=λ(Ω-|Ψ><Ψ|)

[0063] The right side of the equation represents the maximum eigenvalue of the matrix (Ω-|Ψ><Ψ|). On the other hand, it is noted that the maximum eigenvalue of a semi-positive definite matrix can be expressed using the following semi-positive definite optimization:

[0064] λ(Ω-|Ψ><Ψ|)=min{p:Ω-|Ψ><Ψ|≤p·I}

[0065] Therefore, the above performance verification strategy optimization problem can be further rewritten as:

[0066] κ opt =min p

[0067] Satisfies: Ω|Ψ>=|Ψ>

[0068] 0≤Ω≤I

[0069] Ω-|Ψ><Ψ|≤p·I

[0070]

[0071]

[0072] Therefore, according to some embodiments, the objective function is used to minimize a real number p, wherein the real number p is determined based on the second largest eigenvalue of the first matrix Ω. And, the constraint function further includes the following second function:

[0073] Ω-|Ψ><Ψ|≤p·I

[0074] Among them, |Ψ> is the eigenvector of the first matrix Ω.

[0075] According to some embodiments, a lower limit M of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy is determined based on the following formula:

[0076]

[0077] Where ε is the error tolerance of the quantum device, δ is the confidence level of the error in verifying the performance of the quantum device, and κ opt is the optimal solution obtained after minimizing the real number p.

[0078] Therefore, in an exemplary embodiment according to the present disclosure, it can be used to manufacture a device for unknown quantum states. The performance of the device is verified to meet the Good Case / Bad Case assumptions mentioned above to verify the device The minimum number of experiments required to determine whether it is a Good Case or a Bad Case. In addition, the error value ε is preset, which is determined by the device given by the manufacturer; and used to characterize the device The performance non-confidence δ, which is pre-selected by the verifier, records the confidence level of accepting an incorrect judgment. Then, perform the following steps:

[0079] Step 1: Based on the input information, select an algorithm to solve any semi-positive definite optimization problem and calculate the optimal value κ of the performance verification strategy optimization problem opt ;

[0080] Step 2: Calculate the number of local verification schemes

[0081] Step 3: Output the reference value M of the number of experiments.

[0082] The performance of quantum devices will significantly affect the results of quantum computing. Therefore, efficient evaluation of the performance of quantum devices can help device users make better choices and judgments, and then use these quantum devices to achieve more valuable applications. Quantum device verification requires a large number of repeated experiments to reduce the probability of false assertions. The more experiments are performed, the more time and resources such as quantum states are consumed. The estimated number of experiments given is also an estimate of the resource consumption of quantum state verification, and a reference value standard is given in the actual verification scenario. For example, if the number of experiments required for the verification scheme found by the verifier is very close to the reference value given by the scheme according to the embodiment of the present disclosure, it means that the verification scheme is very close to the optimal scheme; on the other hand, if the verification scheme found is smaller than the reference value given by the scheme according to the embodiment of the present disclosure, it means that there must be loopholes in the verification scheme and it needs to be checked or redesigned.

[0083] According to the embodiments of the present disclosure, Figure 3As shown, a complexity determination device 300 for quantum device performance verification is also provided, including: a first acquisition unit 310, configured to obtain a target quantum state that needs to be generated by a quantum device to be verified; a second acquisition unit 320, configured to obtain an initial value of a first matrix Ω used to characterize a performance verification strategy of the quantum device, wherein the first matrix Ω has the same dimension as the target quantum state, and 0≤Ω≤I, and I is a unit matrix; a first determination unit 330, configured to determine a target optimization function corresponding to the performance verification strategy based on the first matrix Ω and the target quantum state, wherein the target optimization function includes a target function and a constraint function, wherein the target function is determined based on the second largest eigenvalue of the first matrix Ω, and the constraint function includes a first function for constraining the performance verification strategy to be a positive partial transpose (PPT) operation; an optimization unit 340, configured to optimize the first matrix Ω based on the target optimization function to determine the value of the optimized first matrix Ω; and a second determination unit 350, configured to determine a lower limit of the number of experiments required for performance verification of the quantum device through the performance verification strategy based on the value of the optimized first matrix Ω.

[0084] Here, the operations of the above-mentioned units 310-350 of the apparatus 300 for determining the complexity of quantum device performance verification are similar to the operations of steps 110-150 described above, and are not described in detail here.

[0085] According to an embodiment of the present disclosure, an electronic device, a readable storage medium and a computer program product are also provided.

[0086] refer to Figure 4 , a block diagram of an electronic device 400 that can be used as a server or client of the present disclosure will now be described, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workbenches, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0087] like Figure 4As shown, the electronic device 400 includes a computing unit 401, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 402 or a computer program loaded from a storage unit 408 into a random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the electronic device 400 can also be stored. The computing unit 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0088] Multiple components in the electronic device 400 are connected to the I / O interface 405, including: an input unit 406, an output unit 407, a storage unit 408, and a communication unit 409. The input unit 406 can be any type of device that can input information to the electronic device 400. The input unit 406 can receive input digital or character information and generate key signal input related to user settings and / or function control of the electronic device, and can include but is not limited to a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and / or a remote controller. The output unit 407 can be any type of device that can present information, and can include but is not limited to a display, a speaker, a video / audio output terminal, a vibrator, and / or a printer. The storage unit 408 can include but is not limited to a disk, an optical disk. The communication unit 409 allows the electronic device 400 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks, and can include but is not limited to a modem, a network card, an infrared communication device, a wireless communication transceiver, and / or a chipset, such as a Bluetooth device, an 802.11 device, a WiFi device, a WiMax device, a cellular communication device, and / or the like.

[0089] The computing unit 401 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 401 performs the various methods and processes described above, such as method 100. For example, in some embodiments, the method 100 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 400 via the ROM 402 and / or the communication unit 409. When the computer program is loaded into the RAM 403 and executed by the computing unit 401, one or more steps of the method 100 described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform the method 100 in any other appropriate manner (e.g., by means of firmware).

[0090] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0091] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0092] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0093] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0094] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), the Internet, and a blockchain network.

[0095] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0096] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0097] Although the embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it should be understood that the above-mentioned methods, systems and devices are merely exemplary embodiments or examples, and the scope of the present invention is not limited by these embodiments or examples, but only by the claims after authorization and their equivalent scope. Various elements in the embodiments or examples can be omitted or replaced by their equivalent elements. In addition, each step can be performed in an order different from that described in the present disclosure. Further, the various elements in the embodiments or examples can be combined in various ways. It is important that with the evolution of technology, many elements described herein can be replaced by equivalent elements that appear after the present disclosure.

Claims

1. A method for determining the complexity of quantum device performance verification, comprising: Obtain the target quantum state that needs to be generated by the quantum device to be verified; Obtaining an initial value of a first matrix Ω for characterizing a performance verification strategy of the quantum device, wherein the first matrix Ω has the same dimension as the target quantum state, and 0≤Ω≤I, where I is a unit matrix; Based on the first matrix Ω and the target quantum state, determining a target optimization function corresponding to the performance verification strategy, wherein the target optimization function includes an objective function and a constraint function, wherein the objective function is determined based on the second largest eigenvalue of the first matrix Ω, and the constraint function includes a first function for constraining the performance verification strategy to be a positive partial transpose (PPT) operation; Optimizing the first matrix Ω based on the target optimization function to determine a value of the optimized first matrix Ω; and Based on the optimized value of the first matrix Ω, a lower limit of the number of experiments required for performing performance verification on the quantum device using the performance verification strategy is determined.

2. The method of claim 1, wherein: The lower limit M of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy is determined based on the following formula: Among them, ε is the error tolerance of the quantum device, δ is the preset confidence level of errors in verifying the performance of the quantum device, and β(Ω) is the second largest eigenvalue of the optimized first matrix Ω.

3. The method of claim 1, wherein: The objective function is used to minimize a real number p, wherein the real number p is determined based on the second largest eigenvalue of the first matrix Ω, and The constraint function also includes the following second function: Ω-|Ψ><Ψ|≤p·I Among them, |Ψ> is the eigenvector of the first matrix Ω.

4. The method of claim 3, wherein: The lower limit M of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy is determined based on the following formula: Where ε is the error tolerance of the quantum device, δ is the confidence level of the error in verifying the performance of the quantum device, and κ opt is the optimal solution obtained after minimizing the real number p.

5. The method according to claim 1 or 3, wherein: The first matrix Ω is optimized by using a solution algorithm for a semi-positive definite programming problem.

6. A complexity determination device for quantum device performance verification, comprising: A first acquisition unit is configured to acquire a target quantum state that needs to be generated by the quantum device to be verified; A second acquisition unit is configured to acquire an initial value of a first matrix Ω for characterizing a performance verification strategy of the quantum device, wherein the first matrix Ω has the same dimension as the target quantum state, and 0≤Ω≤I, where I is a unit matrix; A first determining unit is configured to determine a target optimization function corresponding to the performance verification strategy based on the first matrix Ω and the target quantum state, wherein the target optimization function includes an objective function and a constraint function, wherein the objective function is determined based on the second largest eigenvalue of the first matrix Ω, and the constraint function includes a first function for constraining the performance verification strategy to be a positive partial transpose (PPT) operation; an optimization unit, configured to optimize the first matrix Ω based on the target optimization function to determine a value of the optimized first matrix Ω; and The second determining unit is configured to determine, based on the optimized value of the first matrix Ω, a lower limit of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy.

7. The device according to claim 6, wherein: The lower limit M of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy is determined based on the following formula: Among them, ε is the error tolerance of the quantum device, δ is the preset confidence level of errors in verifying the performance of the quantum device, and β(Ω) is the second largest eigenvalue of the optimized first matrix Ω.

8. The device of claim 6, wherein: The objective function is used to minimize a real number p, wherein the real number p is determined based on the second largest eigenvalue of the first matrix Ω, and The constraint function also includes the following second function: Ω-|Ψ><Ψ|≤p·I Among them, |Ψ> is the eigenvector of the first matrix Ω.

9. The device of claim 8, wherein: The lower limit M of the number of experiments required to perform performance verification on the quantum device using the performance verification strategy is determined based on the following formula: Where ε is the error tolerance of the quantum device, δ is the confidence level of the error in verifying the performance of the quantum device, and κ opt is the optimal solution obtained after minimizing the real number [.

10. The device according to claim 6 or 8, wherein: The first matrix Ω is optimized by using a solution algorithm for a semi-positive definite programming problem.

11. An electronic device, comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 5.

12. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-5.

13. A computer program product comprising a computer program, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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