Display device

Abstract

The present application provides a display device, which can improve the inhibitory effect of burn-in caused by the residual voltage of the pixel electrode after the power is turned off. At a first time (t1) of the power-off timing, after a first power voltage signal (PSIG1) is supplied to the scan line (SCL), a common potential (VCOM) is supplied to the common electrode (COML), and a (GND) potential is supplied to the signal line (DTL), at a second time (t2) after the first time (t1), the (GND) potential is supplied to the scan line (SCL), and at a third time (t3) after the second time (t2), the (GND) potential is supplied to the common electrode (COML).

Description

TECHNICAL FIELD

[0001] The present application relates to a display device. BACKGROUND

[0002] In the past, a liquid crystal display device has been disclosed in which, at the time of power-off, a pixel transistor is turned on by short-circuiting a common electrode and a source line, and a GND potential of the source line is written to the pixel, and thus a residual image can be quickly eliminated by setting a potential of a pixel electrode to the GND potential, and burn-in of liquid crystal caused by a residual voltage can be prevented (for example, refer to Patent Document 1). In addition, a liquid crystal display device has been disclosed in which, at the time of transition from an active state to an inactive state, a gate of all TFTs (Thin-Film Transistor) is turned on, and a liquid crystal driving power source is set to a GND potential, and a liquid crystal driving voltage stored in the liquid crystal and a holding capacitor is discharged (for example, refer to Patent Document 2).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: Japanese Patent Application Publication No. 2008-299253

[0006] Patent Document 2: Japanese Patent Application Publication No. 2001-22326 SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] In the above-described prior art, the fact that, after the potential of the pixel electrode is set to the GND potential, the potential of the pixel electrode changes via a drain-gate capacitance of the pixel transistor when the gate signal potential becomes an off potential, and a residual voltage is generated in the pixel electrode, has not been considered. Therefore, sometimes the effect of suppressing generation of burn-in caused by the residual voltage of the pixel electrode cannot be sufficiently exerted.

[0009] An object of the present application is to provide a display device capable of reducing a residual voltage of a pixel electrode generated in a timing of power-off.

[0010] A display device according to an embodiment of the present application includes a pixel including a pixel transistor and a pixel electrode connected to a first electrode (e.g., drain) of the pixel transistor, a scan line connected to a gate of the pixel transistor, a signal line connected to a second electrode (e.g., source) of the pixel transistor, and a drive circuit supplied with a first power supply voltage signal of a positive value and a second power supply voltage signal of a negative value and configured to drive the pixel transistor, the drive circuit including a gate driver configured to supply a scan signal to the scan line, a signal line selection circuit configured to supply a pixel signal to the signal line, and a display control circuit configured to control the gate driver and the signal line selection circuit, the pixel electrode including a holding capacitor between the pixel electrode and a common electrode supplied with a common potential lower than a GND potential, the display control circuit configured to supply the first power supply voltage signal to the scan line, the common potential to the common electrode, and the GND potential to the signal line at a first time in a power-off timing, supply the GND potential to the scan line at a second time after the first time, and supply the GND potential to the common electrode at a third time after the second time. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 FIG. 1 is a diagram illustrating one example of a schematic structure of a display device according to an embodiment.

[0012] Figure 2 FIG. 2 is a diagram illustrating one example of a pixel arrangement in a display region.

[0013] Figure 3 FIG. 3 is a cross-sectional view showing a schematic cross-sectional structure of a display device.

[0014] Figure 4 FIG. 4 is a top view showing a structure example of a pixel.

[0015] Figure 5A FIG. 5 is a diagram showing a first example of a cross section along the A1-A2 line of FIG. 4. Figure 4

[0016] Figure 5B FIG. 6 is a diagram showing a second example of a cross section along the A1-A2 line of FIG. 4. Figure 4

[0017] Figure 6 FIG. 7 is a diagram showing one example of a drive circuit structure of a display device according to an embodiment.

[0018] Figure 7 FIG. 8 is a timing chart showing one example of a power-off timing according to a comparative example.

[0019] Figure 8 FIG. 9 is a diagram showing a first example of a cross section along the A1-A2 line of FIG. 4. Figure 7 ​​An enlarged view of the potential variation of the pixel electrode after reset of the power-off timing shown.

[0020] Figure 9 A timing chart showing one example of the power-off timing according to the embodiment.

[0021] Figure 10 is a timing chart showing one example of the power-off timing based on Figure 9 An enlarged view of the potential variation of the pixel electrode after reset of the power-off timing shown. DETAILED DESCRIPTION

[0022] Embodiments for carrying out the present application will be explained in detail with reference to the accompanying drawings. The present application is not limited by the contents described in the following embodiments. In addition, the following described constituent elements include those which can be easily conceived by those skilled in the art, substantially the same elements. Furthermore, the following described constituent elements can be appropriately combined. Moreover, the disclosure is merely one example, and appropriate modifications which can be easily conceived by those skilled in the art to maintain the gist of the present application are of course included in the scope of the present application. In addition, the drawings are sometimes schematically represent the width, thickness, shape, and the like of each part in comparison with the actual embodiment, but are merely one example, and do not limit the explanation of the present application. In addition, in the present specification and each drawing, with respect to the drawings already appeared, the same reference numerals are attached to the same elements as described above, and sometimes detailed explanation is appropriately omitted.

[0023] Figure 1 is a diagram showing one example of a schematic structure of a display device according to the embodiment. Figure 2 is a diagram showing one example of a pixel arrangement in a display region.

[0024] The display device 1 according to the present embodiment is, for example, a liquid crystal display device using a liquid crystal display element as a display element. In addition, in the present application, the display device 1 can employ, for example, a column inversion driving method, a frame inversion method, or the like as a driving method. As the driving method in the display device 1, the column inversion driving method, the frame inversion method, or the like is not limited.

[0025] The display device 1 is provided with a display region AA on a display panel 11, and a driver circuit 40 is provided in a peripheral region of the display region AA. The display device 1 is supplied with electric power from a power supply device 12.

[0026] The drive circuit 40 includes a gate driver 42, a signal line selection circuit 43, and a display control circuit 44. The gate driver 42 and the signal line selection circuit 43 are thin film transistor (TFT) circuits formed in a peripheral region of the display region AA. The display control circuit 44 is included in a driver IC (Integrated Circuit) 4 mounted in a peripheral region of the display region AA. The driver IC 4 is connected to the control device 13, for example, via a relay substrate composed of a flexible printed substrate (FPC) or the like.

[0027] The control device 13 controls the supply of electric power from the power supply device 12 to the display device 1. In addition, the control device 13 controls the power-on and power-off of the display device 1. The power supply device 12 and the control device 13 are mounted, for example, on an apparatus (not shown) on which the display device 1 is mounted.

[0028] A plurality of pixels Pix arranged in a Dx direction (first direction) and a Dy direction (second direction) are provided in the display region AA. In addition, a scan line (gate line) SCL that supplies a scan signal (gate signal) GATE to the pixels Pix, a signal line DTL that supplies a pixel signal SIG to the pixels Pix, and a common electrode COML that supplies a common potential VCOM to the pixels Pix are provided in the display region AA. In the present embodiment, the scan line SCL is provided so as to extend in the Dx direction. In addition, in the present embodiment, the signal line DTL is provided so as to extend in the Dy direction.

[0029] As shown in FIG. 1, the pixel Pix includes a pixel transistor Tr and a pixel electrode PX. Figure 2 The pixel transistor Tr is composed of a thin film transistor (TFT), for example, an n-channel MOS (Metal Oxide Semiconductor) type TFT (hereinafter, also referred to as "n-type TFT"). The source of the pixel transistor Tr is connected to the signal line DTL, the gate is connected to the scan line (gate line) SCL, and the drain is connected to the pixel electrode PX. A holding capacitor CS is formed between the pixel electrode PX and the common electrode COML.

[0030] The scan signal (gate signal) GATE (1, 2, ···, m, ···, M) is supplied to the gate of the pixel transistor Tr of the pixel Pix arranged in the row direction (Dx direction) via the scan line (gate line) SCL, and the pixel signal SIG (1, 2, ···, n, ···, N) is supplied to the source of the pixel transistor Tr of the pixel Pix arranged in the column direction (Dy direction) via the signal line DTL. In Figure 2In the present embodiment, an example is shown in which M pixels Pix are arranged in the column direction (Dy direction) and N pixels Pix are arranged in the row direction (Dx direction), but the present embodiment is not limited thereto. Hereinafter, a row in which the pixels Pix are arranged in the row direction (Dx direction) will also be referred to as a pixel row. In addition, a column in which the pixels Pix are arranged in the column direction (Dy direction) will also be referred to as a pixel column.

[0031] In the present application, the pixel Pix includes, for example, a red pixel for displaying red (R), a green pixel for displaying green (G), and a blue pixel for displaying blue (B). As the pixel arrangement, for example, a stripe arrangement in which the respective pixels of RGB are arranged in the row direction (Dx direction) is exemplified, but the pixel arrangement is not limited to the stripe arrangement of RGB. Specifically, for example, as the pixel Pix, a white pixel for displaying white (W) can be arranged, a stripe arrangement in which the row direction (Dx direction) and the column direction (Dy direction) have a predetermined angle in the oblique direction can be provided, or an arrangement in which a plurality of pixel groups displaying different colors are periodically arranged in any one of the row direction (Dx direction) and the column direction (Dy direction) can be provided.

[0032] The power supply device 12 generates a first power supply voltage signal PSIG1 of a positive value and a second power supply voltage signal PSIG2 of a negative value, which are supplied to the display device 1. The first power supply voltage signal PSIG1 is controlled to a first potential (VGH) when the display device 1 is operated. The second power supply voltage signal PSIG2 is controlled to a second potential (VGL) when the display device 1 is operated. The first potential (VGH) is set to 7 [V], for example. The second potential (VGL) is set to -7 [V], for example. The first potential (VGH) supplied when the display device 1 is operated is not limited to 7 [V]. In addition, the second potential (VGL) supplied when the display device 1 is operated is not limited to -7 [V].

[0033] The control device 13 transmits an original signal of an image displayed on the display device 1, that is, an image signal Source, to the display device 1. In addition, the control device 13 transmits a first power supply control signal PCTRL1 for controlling the power supply on and the power supply off of the display device 1 to the display device 1. In addition, the control device 13 transmits a second power supply control signal PCTRL2 for controlling the power supply from the power supply device 12 to the display device 1 to the power supply device 12.

[0034] The control device 13 includes, for example, a CPU (Central Processing Unit) and a storage device such as a memory. The control device 13 uses these hardware resources, such as the CPU and storage device, to execute a program, thereby enabling the display function of the display device 1. Based on the execution result of the program, the control device 13 controls the driver IC4 to process the image displayed on the display device 1 as image input grayscale information.

[0035] The display control circuit 44 controls the display operation in the display area AA by controlling the gate driver 42 and the signal line selection circuit 43. The display control circuit 44 receives various control signals from the control device 13, such as the image signal Source and the first power control signal PCTRL1. Furthermore, the display control circuit 44 converts the image signal Source from the control device 13 into an image signal Vsig and outputs it. The image signal Vsig is, for example, a signal obtained by time-division multiplexing the pixel signal Sig corresponding to the RGB pixel arrangement. Additionally, the display control circuit 44 supplies a common potential VCOM to the common electrode COML.

[0036] Furthermore, the display control circuit 44 serves as an interface (I / F) between the signal line selection circuit 43 and the control device 13, and also functions as a timing generator. Additionally, the driver IC4, which includes the display control circuit 44, may not be mounted on the display panel 11, but rather on a relay substrate connected to the display panel 11. Furthermore, the gate driver 42 and the signal line selection circuit 43 may also be included in the driver IC4.

[0037] Next, refer to Figures 3 to 5B A brief description of the structure of the display device 1 according to the embodiment will be provided. Figure 3 It is a cross-sectional view showing a simplified cross-sectional structure of the display device. Figure 4 This is a top view showing an example of the structure of a pixel. Figure 5A It shows along Figure 4 The first example of a cross-section along line A1-A2. In Figure 5A The first example shown illustrates an instance where a bottom-gate transistor is used as a pixel transistor Tr. Figure 5B It means along Figure 4 The second example of the cross-section of line A1-A2 is shown in the figure. Figure 5B The second example shown illustrates an instance where a top-gate transistor is used as the pixel transistor Tr.

[0038] The array substrate 2 includes a first substrate 21 made of glass or a transparent resin, a plurality of pixel electrodes PX, a common electrode COML, and an insulating layer 24 that insulates the pixel electrodes PX and the common electrode COML. The plurality of pixel electrodes PX are arranged, for example, in a row and column (matrix) shape above the first substrate 21. The common electrode COML is provided between the first substrate 21 and the pixel electrodes PX.

[0039] The pixel electrode PX is provided corresponding to each pixel Pix. A pixel signal SIG for performing a display operation is supplied from the signal line selection circuit 43 to the pixel electrode PX via the signal line DTL and the pixel transistor Tr. In addition, a common potential VCOM for display as a voltage signal is supplied from the driver IC 4 to the common electrode COML at the time of the display operation. The common potential VCOM is preferably a potential different from the GND (ground) potential, and is set to, for example, about -0.7 [V]. The set value of the common potential VCOM is set to an optimum value at which flicker does not occur in a driving method such as a column inversion driving method, a frame inversion driving method, or the like. In addition, the common potential VCOM is preferably a fixed potential, but can be a structure having a waveform composed of an alternating-current rectangular wave.

[0040] The pixel electrode PX and the common electrode COML are composed of, for example, a conductive material having a light-transmitting property such as ITO (Indium Tin Oxide). On the lower side of the first substrate 21, a polarizing plate 35B is provided via an adhesive layer (not shown).

[0041] The counter substrate 3 includes a second substrate 31 made of glass or a transparent resin, and a color filter 32 and a light-shielding layer (not shown) formed on one surface of the second substrate 31. In addition, on the upper side of the second substrate 31, a polarizing plate 35A is provided via an adhesive layer (not shown).

[0042] The array substrate 2 and the counter substrate 3 are disposed in opposition to each other at a predetermined interval (cell gap). As a display function layer, a liquid crystal layer 6 is provided in a space between the first substrate 21 and the second substrate 31. The liquid crystal layer 6 changes the orientation state of liquid crystal molecules for each pixel Pix in accordance with the state of an electric field between each pixel electrode PX and the common electrode COML, thereby modulating light passing through the liquid crystal layer 6. In the present embodiment, for example, IPS (In Plane Switching) or the like suitable for a lateral electric field mode including FFS (Fringe Field Switching) is used.

[0043] The array substrate 2 has a pixel transistor Tr of each pixel Pix, a signal line DTL that supplies a pixel signal SIG to each pixel electrode PX, a wiring such as a scan line (gate line) SCL that supplies a gate signal GATE for driving each pixel transistor Tr. The signal line DTL and the scan line (gate line) SCL extend in a plane parallel to the surface of the first substrate 21.

[0044] As shown in FIG. 1, a region surrounded by the scan line (gate line) SCL and the signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip electrodes 22a and a connection portion 22b. Figure 4

[0045] As shown in FIG. 1, a region surrounded by the scan line (gate line) SCL and the signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip electrodes 22a and a connection portion 22b. Figure 4

[0046] As shown in FIG. 1, a region surrounded by the scan line (gate line) SCL and the signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip electrodes 22a and a connection portion 22b. Figure 5A As shown in FIG. 1, a region surrounded by the scan line (gate line) SCL and the signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip electrodes 22a and a connection portion 22b.

[0047] Figure 5B As shown in FIG. 1, a region surrounded by the scan line (gate line) SCL and the signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip electrodes 22a and a connection portion 22b.

[0048] As shown in FIG. 1, a region surrounded by the scan line (gate line) SCL and the signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip electrodes 22a and a connection portion 22b.

[0049] As shown in FIG. 1, a region surrounded by the scan line (gate line) SCL and the signal line DTL is a pixel Pix. The pixel electrode PX has a plurality of strip electrodes 22a and a connection portion 22b.​​​Figure 4 and Figure 5A (Or Figure 5B ) as illustrated, the pixel electrode PX is connected with the drain electrode 63 of the pixel transistor Tr via the contact hole Hl l. The drain electrode 63 is connected with the semiconductor 61 via the contact hole H12. The semiconductor 61 is intersected with the gate electrode 64 in plan view. The gate electrode 64 is provided to be connected with the scan line (gate line) SCL, and protrudes from one side of the scan line (gate line) SCL. The semiconductor 61 extends to a position overlapping with the source electrode 62, and is electrically connected with the source electrode 62 via the contact hole H13. The source electrode 62 is connected with the signal line DTL, and protrudes from one side of the signal line DTL.

[0050] As a material of the semiconductor 61, a known material such as polysilicon, an oxide semiconductor, or the like can be used. For example, since TAOS (Transparent Amorphous Oxide Semiconductor) is used, the ability to maintain the voltage for image display (retention rate) is good for a long time, and the display quality can be improved. In addition, the oxide semiconductor including the TAOS has a small leakage current when the pixel transistor Tr is turned off.

[0051] The gate electrode 64 (scan line (gate line) SCL) is composed of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof. The drain electrode 63 and the source electrode 62 (signal line DTL) are composed of, for example, an alloy of titanium and aluminum, i.e., titanium aluminum (TiAl).

[0052] As a material of the insulating layer 24, 58a, 58c, 58d, 58e, 58f, a known insulating material can be used. In addition, for example, as a material of the insulating layer 58c, a silicon oxide film (SiO2) can be used. As a material of the insulating layer 58d, an organic insulating film such as an acrylic resin is used. Thereby, planarization of a surface on which the common electrode COML is provided can be achieved.

[0053] As a material of the auxiliary wiring layer 54, similarly to the gate electrode 64 (scan line (gate line) SCL), for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), or an alloy thereof is used.

[0054] In the display device 1 of the above-described simple configuration, in addition to the hold capacitor CS formed between the pixel electrode PX and the common electrode COML, a parasitic capacitor is generated between the pixel electrode PX and other conductive members.

[0055] In the liquid crystal display device, since the output of the drive circuit becomes high impedance at the time of power-off, it is necessary to reset (discharge) the potential held to the pixel electrode at the time of power-off. The control step at the time of resetting the potential held to the pixel electrode at the time of power-off is also called "power-off timing".

[0056] Hereinafter, the specific structure of the drive circuit 40 of the display device 1 according to the embodiment and the power-off timing will be described.

[0057] Figure 6 is a view showing one example of the drive circuit structure of the display device according to the embodiment. In Figure 6 , the circuit structure example corresponding to one pixel Pix(m, n) is shown. In Figure 2 , the pixel arrangement shown in the pixel arrangement shown in Figure 6 , the parasitic capacitance CP generated between the pixel electrode PX and the scan line (gate line) SCL is shown by a broken line.

[0058] The first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 are supplied from the power supply device 12 to each circuit element constituting the drive circuit 40 to make it operate. The potential (first potential VGH) of the first power supply voltage signal PSIG1 supplied from the power supply device 12 at the time of operation of the display device 1 is set to the high potential of the scan signal (gate signal) GATE(m) supplied to the gate of the pixel transistor Tr. In addition, the potential (second potential VGL) of the second power supply voltage signal PSIG2 supplied from the power supply device 12 at the time of operation of the display device 1 is set to the low potential of the scan signal GATE(m) supplied to the gate of the pixel transistor Tr.

[0059] The display control circuit 44 (driver IC 4) controls the gate driver 42 and the signal line selection circuit 43. Specifically, the display control circuit 44 supplies the gate driver 42 with a start pulse STV, a synchronization signal such as a shift clock CKV, a scan line drive signal ENB. In addition, the display control circuit 44 supplies the signal line selection circuit 43 with a signal line selection control signal ASW(n), XASW(n).

[0060] Further, in the present application, the display control circuit 44 performs on / off control of the pixel transistor Tr of all the pixels Pix in the display region AA in the power-off timing, and supplies a reset signal XReset for resetting the potential of the pixel electrode PX to the gate driver 42. The reset signal XReset is a signal that is set to a high potential (first potential VGH) during the display operation (display period) and is set to a low potential (second potential VGL) in the power-off timing.

[0061] As a main circuit element for performing the display operation, the gate driver 42 includes a shift register circuit 421 and a scan line drive circuit 422. Further, in the present application, the gate driver 42 includes an AND circuit 424 that outputs a low potential (second potential VGL) to the scan line drive circuit 422 at least when the reset signal XReset is a low potential (second potential VGL).

[0062] The shift register circuit 421 is a circuit that generates a signal that becomes a high potential (first potential VGH) at the time of selection of the m-th column of pixel rows, based on a synchronization signal such as a start pulse STV and a shift clock CKV output from the display control circuit 44.

[0063] Specifically, the shift register circuit 421, for example, takes in the output of the previous stage shift register S / R (or the start pulse STV) when the shift clock CKV is a high potential, and cuts off the path of taking in the output of the previous stage shift register S / R (or the start pulse STV) when the shift clock CKV is a low potential, and holds the value by a latch operation in the shift register S / R.

[0064] The output signal of the shift register circuit 421 is logically inverted by an inverter circuit 423. The output signal of the inverter circuit 423 is input to the scan line drive circuit 422 via the AND circuit 424 at the time of the display operation, that is, when the reset signal XReset is a high potential (first potential VGH).

[0065] The scan line drive circuit 422 is a circuit that generates a scan signal GATE(m) supplied to the gate of the pixel transistor Tr, based on a signal output from the AND circuit 424 and a scan line drive signal ENB output from the display control circuit 44. The high potential of the scan line drive signal ENB is set to the first potential VGH.

[0066] Specifically, the scan line drive circuit 422, at the time of display operation, when the signal output from the AND circuit 424 is at a high level (first potential VGH), controls the first transistor Trl constituted by a p-channel MOS type TFT (hereinafter, also referred to as "p-type TFT") and the second transistor Tr2 constituted by an n-type TFT to be turned off, and controls the third transistor Tr3 constituted by an n-type TFT to be turned on. Thereby, the output potential of the scan line drive circuit 422 becomes the second potential VGL, and the pixel transistor Tr of the pixel Pix(m, n) is controlled to be turned off.

[0067] In addition, the scan line drive circuit 422, at the time of display operation, when the signal output from the AND circuit 424 is at a low level (second potential VGL), controls the first transistor Trl and the second transistor Tr2 to be turned on, and controls the third transistor Tr3 to be turned off. Thereby, the output potential of the scan line drive circuit 422 becomes the high level of the scan line drive signal ENB, i.e., the first potential VGH, and the pixel transistor Tr of the pixel Pix(m, n) is controlled to be turned on.

[0068] The signal line selection circuit 43 is a switching circuit that selectively outputs the image signal Vsig output from the display control circuit 44 as a pixel signal SIG at the time of selection of the pixel column of the nth row. Specifically, the signal line selection circuit 43 is provided with a switching transistor ASWTr constituted by an n-type TFT and a switching transistor XASWTr constituted by a p-type TFT.

[0069] The signal line selection circuit 43, when the signal line selection control signal ASW(n) output from the display control circuit 44 is at a high level and the signal line selection control signal XASW(n) is at a low level, controls the switching transistors ASWTr, XASWTr to be turned on. In addition, the signal line selection circuit 43, when the signal line selection control signal ASW(n) output from the display control circuit 44 is at a low level and the signal line selection control signal XASW(n) is at a high level, controls the switching transistors ASWTr, XASWTr to be turned off.

[0070] The signal line selection control signal ASW(n) and the signal line selection control signal XASW(n) are complementary signals that are logically inverted from each other. The signal line selection control signal XASW(n) can also be generated by logically inverting the signal line selection control signal ASW(n). In addition, the signal line selection control signal ASW(n) can also be generated by logically inverting the signal line selection control signal XASW(n). Furthermore, the signal line selection circuit 43 can also be configured by only the switching transistor composed of the n-type TFT or the p-type TFT. In the case where the switching transistor is composed of the n-type TFT, the signal line selection control signal XASW is not needed. In addition, in the case where the switching transistor is composed of the p-type TFT, the signal line selection control signal ASW is not needed.

[0071] Through the operation of each circuit element of the above-described drive circuit 40, at the time of selection of the pixel Pix(m, n) at the time of display operation, the pixel transistor Tr of the pixel Pix(m, n) is controlled to be turned on, and the pixel signal SIG is written to the pixel electrode PX of the pixel Pix(m, n). Thereafter, during the period until the pixel transistor Tr of the pixel Pix(m, n) is controlled to be turned off and the pixel Pix(m, n) is again controlled to be turned on in the next frame, the potential of the pixel signal SIG is held in the holding capacitor CS. By performing the above-described control on all the pixels Pix within the display region AA in a selection order corresponding to a predetermined drive method (for example, a column inversion drive method, a frame inversion method), it is possible to perform the display operation in the display region AA.

[0072] In the above-described power-off timing, the display control circuit 44 sets the reset signal XReset to the low potential (the second potential VGL). Thereby, the scan line drive circuit 422 is supplied with the low potential (the second potential VGL), the potential of all the scan lines SCL becomes the high potential (the first potential VGL), the pixel transistor Tr of all the pixels Pix within the display region AA is controlled to be turned on, and the potential of the pixel electrode PX is reset. Thereby, it is possible to suppress the burn-in of the liquid crystal caused by the residual voltage of the pixel electrode PX.

[0073] Figure 7 is a timing chart showing one example of the power-off timing related to the comparative example. In the present application, the display control circuit 44 performs the power-off timing of the display device 1 based on the first power control signal PCTRL1 output from the control device 13. In the comparative example, the display control circuit 44 performs the power-off timing of the display device 1 based on the second power control signal PCTRL2 output from the control device 13. Figure 7 In the example shown in FIG. 10, an example in which the power-off timing is started at time t0 is shown. Before time t0, the above-described normal display operation is performed.

[0074] If the power-off sequence is started at time t0, the display device 1 performs black display. Specifically, the display control circuit 44 performs display operation with the grayscale of the image signal Vsig corresponding to all the pixels Pix in the display area AA set to "0". Thus, the potential held at the pixel electrode PX can be set to the minimum value. Hereinafter, the period during which black display is performed is also referred to as "black insertion period". Note that the black insertion period is not necessarily provided.

[0075] If the black insertion period is ended at time t1, the display control circuit 44 supplies the GND potential as the potential supplied to the signal line DTL. At this time, the display control circuit 44 sets the signal line selection control signal ASW corresponding to all the signal lines DTL to the high potential and sets the signal line selection control signal XASW corresponding to all the signal lines DTL to the low potential. Thus, the switching transistors ASWTr, XASWTr are controlled to be turned on to supply the GND potential to the signal line DTL, and the potential of the signal line DTL is set to the GND potential.

[0076] In addition, at time t1, the display control circuit 44 stops supplying the common potential VCOM to the common electrode COML. Thus, the potential of the common electrode COML converges to the GND potential before time t4 is reached. In addition, at time t1, the display control circuit 44 sets all the scan line drive signals ENB to the high potential (the first potential VGH). In addition, the display control circuit 44 sets the reset signal XReset to the low potential (the second potential VGL). Thus, the potential of the output signal of the AND circuit 424 becomes the low potential (the second potential VGL). As a result, the first transistor Tr1 and the second transistor Tr2 of the scan line drive circuit 422 are controlled to be turned on, the third transistor Tr3 is controlled to be turned off, the potential of all the scan lines SCL becomes the first potential VGH supplied as the high potential of the scan line drive signal ENB, and the pixel transistor Tr of all the pixels Pix is controlled to be turned on. Thus, the pixel electrode PX of all the pixels Pix is electrically connected to the signal line DTL of the GND potential via the pixel transistor Tr controlled to be turned on, and the potential of the pixel electrode PX of all the pixels Pix is reset to the GND potential.

[0077] At time t4 after the potential of the pixel electrode PX of all the pixels Pix is reset, the power supply device 12 stops supplying the first power voltage signal PSIG1 and the second power voltage signal PSIG2 to the display device 1 based on the second power control signal PCTRL2 output from the control device 13. Thus, the driver IC 4 stops control, and the potential of the synchronization signal such as the start pulse STV and the shift clock CKV, the control signal such as the entire scan line drive signal ENB, the reset signal XReset, the signal line selection control signal ASW, XASW corresponding to all the signal lines DTL, and the like becomes the GND potential.

[0078] Furthermore, the potentials of the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 gradually decrease through the power smoothing capacitor (not shown) provided in the power supply device 12. Therefore, the potentials of the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2 converge to the GND potential after each control signal becomes GND. In other words, the potentials of each control signal output from the driver IC converge to the GND potential more rapidly than the first power supply voltage signal PSIG1 and the second power supply voltage signal PSIG2.

[0079] At this time, a rapid potential change occurs on the scan line SCL, from the high potential (first potential VGH) of the scan line drive signal ENB of the scan signal GATE to the GND potential. As mentioned above, a parasitic capacitance CP is formed between the drain and gate of the pixel transistor Tr. However, the rapid voltage change of the scan line SCL affects this parasitic capacitance CP, causing the potential of the pixel electrode PX to drop from its original reset potential (GND potential).

[0080] Here, we will explain in more detail the principle of the potential drop of the pixel electrode PX. Figure 8 Based on Figure 7 The image shows an enlarged view of the potential changes of the pixel electrode after reset following the power-off timing sequence. Figure 8 The solid line shown indicates the potential of the pixel electrode PX. Figure 8 The dashed line shown indicates the potential of the scan line SCL. Furthermore, in this comparative example, at time t4, the common electrode COML converges to GND potential, and the signal line DTL also converges to GND potential, becoming a high-impedance state (floating state).

[0081] like Figure 8 As shown, if the gate potential of the pixel transistor Tr connected to the scan line SCL changes from the first potential VGH to the GND potential, the parasitic capacitance CP discharges accordingly. During the period when the pixel transistor Tr remains in the on-state before its potential falls below the threshold voltage Vth, the parasitic capacitance CP is recharged from the signal line DTL via the pixel transistor Tr. However, when the gate potential of the pixel transistor Tr changes drastically, the discharge rate of the parasitic capacitance CP exceeds its recharge rate. This results in a decrease in the potential of the pixel electrode PX.

[0082] Furthermore, as described above, during the brief period when the pixel transistor Tr remains in the on state, the signal line selection control signals ASW and XASW become GND potential. This causes the signal line DTL, which serves as the charge supply source for recharging the pixel electrode PX, to be in a high-impedance state (floating state). Therefore, through the charge supply for recharging the pixel electrode PX, the potential of the signal line DTL decreases from the GND potential. Consequently, the potential decrease of the pixel electrode PX recharged from the signal line DTL becomes more significant. Then, if the potential of the pixel transistor Tr falls below the threshold voltage Vth, the pixel transistor Tr becomes off, maintaining the state where the potential of the pixel electrode PX is below the GND potential.

[0083] The result is, as Figure 7 as well as Figure 8 As shown, the potential difference ΔV between the pixel electrode PX and the reset potential (GND) after the control of driver IC4 stops at time t4 is a negative value. This residual voltage is referred to as GND-ΔV. Here, it is considered that this residual voltage gradually disappears over time due to the leakage current when the pixel transistor Tr is turned off. However, especially when using semiconductors such as TAOS (transparent amorphous oxide semiconductor) or oxide semiconductors with good voltage retention for image displays, or with very small leakage current when turned off, as the semiconductor material 61, the residual potential difference ΔV at the pixel electrode PX may be maintained for a long time, potentially causing screen burn-in. Furthermore, it is also considered that the optimal value of the common potential VCOM may change due to screen burn-in, which could potentially become a cause of flickering based on column inversion driving methods, frame inversion driving methods, etc.

[0084] Figure 9 This is a timing diagram illustrating an example of the power disconnection timing involved in the implementation. Figure 10 Based on Figure 9 The image shows an enlarged view of the potential changes of the pixel electrode after reset following the power-off timing sequence. Figure 10 The solid line shown represents the potential of the pixel electrode PX. Figure 10 The dashed line shown indicates the potential of the scan line (gate line) SCL. Figure 10 The dotted line indicates the potential of the common electrode COML. Here, for... Figure 7 as well as Figure 8 The points where the power disconnection timing differs in the comparative examples shown are explained in detail, and sometimes repeated explanations are omitted.

[0085] In the power-off timing according to the embodiment, if the black insertion period ends at time t1 (first time), the image signal Vsig becomes the GND potential. At this time, the display control circuit 44 sets the signal line selection control signal ASW corresponding to all the signal lines DTL to the high potential and sets the signal line selection control signal XASW corresponding to all the signal lines DTL to the low potential. Thus, the potential of the pixel signal SIG of the signal line DTL becomes the potential of the image signal Vsig, that is, the GND potential.

[0086] In addition, at time t1 (first time), the display control circuit 44 sets all the scan line drive signals ENB to the high potential (first potential VGH) and sets the reset signal XReset to the low potential (second potential VGL). Thus, the potential of the output signal of the AND circuit 424 becomes the low potential (second potential VGL). As a result, the first transistor Trl and the second transistor Tr2 of the scan line drive circuit 422 are controlled to be turned on, the third transistor Tr3 is controlled to be turned off, the potential of all the scan lines (gate lines) SCL becomes the first potential VGH supplied as the high potential of the scan line drive signal ENB, and the pixel transistor Tr of all the pixels Pix is controlled to be turned on. Thus, the pixel electrode PX of all the pixels Pix is electrically connected to the signal line DTL of the GND potential via the pixel transistor Tr controlled to be turned on, and the pixel electrode PX of all the pixels Pix is reset.

[0087] After the potential of the pixel electrode PX of all the pixels Pix is reset, the potential of all the scan line drive signals ENB is set to the GND potential at time t2 (second time). Thus, a potential variation from the first potential VGH of the scan line drive signal ENB of the scan signal GATE to the GND potential occurs in the scan line SCL, and a voltage variation of the scan line (gate line) SCL overlaps the pixel electrode PX via the parasitic capacitance CP generated between the drain and the gate of the pixel transistor Tr. Therefore, as shown in FIG. 6, a potential difference AV1 of a negative value occurs in the potential of the pixel electrode PX after time t2 (second time) with respect to the potential after the reset, that is, the GND potential, as a residual voltage (GND - AV1). Figure 9 Figure 10

[0088] In the power-off timing according to the embodiment, the control states of the signal line selection control signals ASW and XASW are maintained at time t2. Specifically, the potential of the signal line selection control signal ASW is maintained at the high potential, and the potential of the signal line selection control signal XASW is maintained at the low potential. Therefore, the potential of the signal line DTL, which is a charge supply source for the recharging of the pixel electrode PX, decreases with respect to the potential of the signal line DTL at time t1 (first time) before the reset of the pixel electrode PX. Figure 7 Figure 8 ​​​The potential drop at time t4 of the power-off timing of the comparative example shown is suppressed. Thus, as Figure 10 shown, the potential difference ΔV1 generated at the pixel electrode PX is smaller than Figure 7 and Figure 8 the potential difference ΔV (ΔV1< ΔV) at time t4 of the power-off timing of the comparative example shown. In this embodiment, the common electrode COML still maintains the state of being supplied with the common potential VCOM until time t2.

[0089] At time t3 (third time) immediately after time t2, the display control circuit 44 stops supplying the common potential VCOM to the common electrode COML. Thus, the common electrode COML generates a potential change from the common potential VCOM to the GND potential. The potential change of the common electrode COML is superimposed on the pixel electrode PX via the holding capacitor CS, and as a result, as Figure 9 and Figure 10 shown, the potential of the pixel electrode PX after time t3 rises to a value (GND- ΔV1+ ΔV2) obtained by adding a positive potential difference ΔV2 to the potential (GND- ΔV1) after time t2. Thus, the potential of the pixel electrode PX after time t3 is smaller than Figure 7 and Figure 8 the potential difference ΔV generated at the power-off timing of the comparative example shown. This makes it possible to reduce the potential difference |ΔV1- ΔV2| (GND- (ΔV1- ΔV2)) with respect to the potential after reset, i.e., the GND potential. Further, as Figure 10 shown, the positive potential difference ΔV2 superimposed on the potential (GND- ΔV1) generated at the pixel electrode PX after time t2 is equal to or smaller than the magnitude of the common potential VCOM (ΔV2≤ |VCOM|).

[0090] After that, if the driver IC 4 stops control at time t4 (fourth time), the potentials of the synchronization signals such as the start pulse STV and the shift clock CKV, the reset signal XReset, each control signal such as the signal line selection control signal ASW, XASW corresponding to all the signal lines DTL become the GND potential.

[0091] The power-off timing according to the above-described embodiment makes the potential remaining at the pixel electrode PX after time t4 at which the driver IC 4 stops control smaller than Figure 7 and Figure 8 the power-off timing according to the comparative example shown. Thus, it is possible to suppress the generation of burn-in of the liquid crystal caused by the residual voltage of the pixel electrode PX after the power-off. In addition, it is possible to suppress the generation of flicker caused by the variation of the optimum value of the common potential VCOM due to the burn-in.

[0092] Furthermore, the display device 1 is not limited to a liquid crystal display device, and can be, for example, an organic EL display using an organic light emitting diode (OLED: Organic Light Emitting Diode) as a display element. In addition, the display device 1 can be an inorganic EL display using an inorganic light emitting diode (micro LED) as a display element. In addition, the display device 1 can be an electrophoretic display (EPD: Electrophoretic Display), and can also be a transparent display that displays an image on a display surface having transparency.

[0093] The preferred embodiments of the present application have been described above, but the present application is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various modifications can be made without departing from the spirit of the present application. Appropriate modifications made within the scope of the spirit of the present application are naturally included in the technical scope of the present application.

[0094] Explanation of Reference Numerals

[0095] 1, display device; 4, driver IC; 11, display panel; 12, power supply device; 13, control device; 40, drive circuit; 42, gate driver; 43, signal line selection circuit; 44, display control circuit; AA, display area; COML, common electrode; CS, hold capacitor; CP, parasitic capacitor; DTL, signal line; ENB, scan line drive signal; GATE, scan signal (gate signal); PCTRL1, first power supply control signal; PCTRL2, second power supply control signal; Pix, pixel; PSIG1, first power supply voltage signal; PSIG2, second power supply voltage signal; PX, pixel electrode; Source, image signal; SCL, scan line (gate line); SIG, pixel signal; Tr, pixel transistor; VCOM, common potential; VGH, first potential; VGL, second potential; Vsig, image signal; XReset, reset signal.

Claims

1. A display device, wherein, The display device includes: A pixel has a pixel transistor and a pixel electrode connected to a first electrode of the pixel transistor; The scan line is connected to the gate of the pixel transistor; The signal line is connected to the second electrode of the pixel transistor; as well as The driving circuit is supplied with a positive first power supply voltage signal and a negative second power supply voltage signal, and is used to drive the pixel transistor. The driving circuit includes: A gate driver supplies a scan signal to the scan line; A signal line selection circuit supplies pixel signals to the signal lines; as well as The display control circuit controls the gate driver and the signal line selection circuit. During display operation, the pixel electrode is provided with a holding capacitor between itself and a common electrode that is supplied with a common potential lower than the GND potential. At the first moment of the power-off sequence, the display control circuit supplies the first power supply voltage signal to the scan line, the common potential to the common electrode, and the GND potential to the signal line. At a second time point following the first time point, a GND potential is supplied to the scan line. At a third time point following the second time point, a GND potential is supplied to the common electrode.

2. The display device according to claim 1, wherein, The display control circuit maintains a state of supplying GND potential to the signal line until the fourth time after the third time.

3. The display device according to claim 1, wherein, The display device includes at least a driver IC comprising the display control circuit.

4. A display device, wherein, The display device includes: transistor; The pixel electrode is connected to the first electrode of the transistor; The signal line is connected to the second electrode of the transistor and is input with an image signal. The scan line is connected to the gate electrode of the transistor and inputs the scan signal to the gate electrode; as well as The common electrode coincides with the pixel electrode. During the display, a common potential is applied to the common electrode. Following the aforementioned display period, the first period, the second period, and the third period are presented in the order of a first period, a second period, and a third period. During the first period, the pixel electrode is given a GND potential, the common electrode is given a common potential, and the scan line is given a potential that turns on the transistor. During the second period, the common electrode is applied with the common potential, and the scan line is applied with the GND potential. During the third period, the common electrode is given a GND potential and the scan line is given a GND potential.

5. The display device according to claim 4, wherein, After the third period, the display device becomes disconnected.

6. The display device according to claim 4, wherein, The display device also includes a drive circuit that is supplied with a power supply voltage signal. Following the third period, a fourth period occurs where the power supply voltage signal becomes the GND potential.

7. The display device according to claim 6, wherein, The driving circuit is supplied with at least one of the following signals: a synchronization signal, a scan line drive signal that controls the scan signal, and a signal line selection control signal that controls the image signal. During the fourth period, the at least one signal becomes the GND potential.

8. The display device according to claim 7, wherein, During the fourth period, the synchronization signal, the scan line drive signal, and the signal line selection control signal become the GND potential.

9. The display device according to claim 4, wherein, The display device also includes a drive circuit that is supplied with a power supply voltage signal. Following the third period, there is a fourth period in which the power supply voltage signal is not supplied to the drive circuit.

10. The display device according to claim 4, wherein, The display device also includes a drive circuit that is supplied with a first power supply voltage signal and a second power supply voltage signal. The first polarity of the first power supply voltage signal is different from the second polarity of the second power supply voltage signal. Following the third period, a fourth period occurs where the first power supply voltage signal and the second power supply voltage signal become the GND potential.

11. The display device according to claim 4, wherein, The display device also includes a drive circuit that is supplied with a reset signal for switching between the display period and the first period. The reset signal is a first reset signal having a first polarity during the display period, a second reset signal having a second polarity different from the first polarity during the first period, and a third reset signal as the GND potential during the fourth period after the third period.

12. The display device according to claim 4, wherein, During the second period, the pixel electrode is applied a first pixel potential that is different from the GND potential. During the third period, the pixel electrode is applied a second pixel potential that is different from the first pixel potential. The first potential difference between the GND potential and the first pixel potential is greater than the second potential difference between the GND potential and the second pixel potential.

13. The display device according to claim 12, wherein, The pixel electrode and the common electrode form a first capacitor. The pixel electrode and the scan line form a second capacitor.

14. The display device according to claim 4, wherein, The common potential is smaller than the GND potential.

15. The display device according to claim 4, wherein, Between the display period and the first period, an image signal that is displayed as black is input to the pixel electrode.

16. The display device according to claim 4, wherein, The image signal includes multiple grayscale signals with different grayscale levels. Between the display period and the first period, the grayscale signal with the lowest potential among the plurality of grayscale signals is input to the pixel electrode.

17. The display device according to claim 4, wherein, The display device also has multiple pixels. The plurality of pixels have corresponding plurality of pixel electrodes. The pixel electrode includes the pixel electrode. The image signal includes multiple grayscale signals with different grayscale levels. Between the display period and the first period, the grayscale signal with the lowest potential among the plurality of grayscale signals is input to all the pixel electrodes.

18. The display device according to claim 4, wherein, The display device also includes multiple pixels and multiple scan lines, including the scan lines. The plurality of pixels have corresponding plurality of pixel electrodes. The pixel electrode includes the pixel electrode. During the first period, the GND potential is applied to all the pixel electrodes, and the potential that turns on the transistors is applied to all the plurality of scan lines.

19. A display device, wherein, The display device has multiple pixels. Each of the plurality of pixels has: transistor; The pixel electrode is connected to the first electrode of the transistor; The signal line is connected to the second electrode of the transistor and receives the input image signal. The scan line is connected to the gate electrode of the transistor and inputs the scan signal to the gate electrode; as well as The common electrode coincides with the pixel electrode. During the display, a common potential is applied to the common electrode. After the display period, it has: At the first moment, the potential applied to the pixel electrode switches from the image signal to the GND potential, and the scan line is applied with the potential of the scan signal; At a second time after the first time, the potential applied to the scan line switches from the scan signal to the GND potential; as well as At a third time after the second time, unlike the first and second time, the potential applied to the common electrode switches from the common potential to the GND potential.

20. The display device according to claim 19, wherein, The display device also includes a drive circuit that is supplied with a power supply voltage signal. Following the display period, there is a fourth moment when the power supply voltage signal switches from a potential different from GND to GND. The first time point to the third time point is between the display period and the fourth time point.

Images