Drive circuit and power conversion device

Abstract

Provided is a drive circuit capable of driving a collector gate of a CG-IGBT according to the same PWM signal as a general IGBT with a low-cost structure, and a power conversion device provided with the same. A drive circuit drives a collector gate control IGBT, which is an IGBT provided with an emitter, a collector, an emitter gate as a gate on the emitter side, and a collector gate as a gate on the collector side, wherein the drive circuit has a first gate driver that drives the gate on the emitter side, and a second gate driver that drives the gate on the collector side, the same drive command signal is input to the first gate driver and the second gate driver, and the second gate driver has a high-voltage diode that is input a signal based on the drive command signal.

Description

Technical Field

[0001] This invention relates to drive circuits and power conversion devices. Background Technology

[0002] Insulated gate bipolar transistors (IGBTs) are used, for example, in inverter circuits with inductive loads.

[0003] A typical IGBT has a collector terminal and an emitter terminal for cutting off voltage or turning on current, and a gate terminal for controlling the IGBT's off and on states.

[0004] To reduce the resistance of IGBTs during conduction, it is effective to inject carriers at high density into the drift layer to promote conductivity modulation. On the other hand, with high-density carrier injection, the speed of the cutoff switching action from the conduction state to the cutoff state slows down, resulting in increased cutoff losses. Therefore, there is a trade-off between reducing conduction losses and reducing cutoff losses.

[0005] In recent years, as a means to improve this compromise, collector gate control IGBTs (CG-IGBT, see Non-Patent Document 1 below) and collector gate control reverse conduction IGBTs (CG-RC-IGBT, see Non-Patent Document 2 below) have been disclosed, which have an N-type MOSFET (NMOS) structure added to the collector section and have a collector gate terminal for controlling the NMOS of the collector section.

[0006] As in Non-Patent Document 1, CG-IGBT is sometimes referred to as BC-IGBT (Back-Gate-Controlled IGBT). Additionally, as in Non-Patent Document 2, the collector-gate (CG) is sometimes referred to as ATG (Anode Trench Gate).

[0007] An RC-IGBT (reverse-conducting IGBT) is an IGBT with a built-in diode that allows current to flow in the reverse direction of the IGBT. While conventional IGBTs require an anti-parallel diode for return current, RC-IGBTs offer the advantage of not needing this anti-parallel diode. Based on Non-Patent Document 2 and our experimental results, by turning on the collector-gate slightly (e.g., by 1 μs) earlier than the conventional gate OFF, the carrier density in the IGBT can be dynamically reduced, thereby lowering the cutoff loss.

[0008] In this specification, the term "collector-gate controlled IGBT" (CG-IGBT) is explained as referring to an IGBT that includes an emitter, a collector, an emitter gate (a conventional gate) serving as the emitter-side gate, and a collector gate serving as the collector-side gate. Furthermore, a type of collector-gate controlled IGBT (CG-IGBT) including a collector-gate controlled reverse conduction IGBT (CG-RC-IGBT) will also be explained.

[0009] Existing technical documents

[0010] Non-patent literature 1: T.Saraya, K.Itou, T.Takakura, M.Fukui, S.Suzuki, K.Takeuchi, M.Tsukuda, K.Satoh, T.Matsudai, K.Ka kushima, T.Hoshii, K.Tsutsui, H.Iwai, A.Ogura, W.Saito, S.Nishizawa, I.Omura, H.Ohashi, T.Hiramoto, "3.3kV Back-Gate-ControlledIGBT(BC-IGBT)Using Manufacturable Double-Side Process Technology”, IEDM2020pp.IEDM20-87-IEDM20-90.

[0011] Non-patent literature 2: J.Wei, Devices, VOL.66pp.533-538(2019). Summary of the Invention

[0012] However, in the aforementioned Non-Patent Documents 1 and 2, a new collector gate control is required in addition to the conventional gate, which complicates the control process. Furthermore, when the CG-IGBT is in the off state, the collector gate potential needs to rise along with the collector potential, thus requiring insulation from conventional gate drive circuitry. While using an isolated DC-DC converter can isolate the input signal from the output to the collector gate, this increases the number of components and thus the cost.

[0013] Therefore, a gate drive circuit is needed that can drive not only the conventional gate but also the collector gate, based on a typical complementary PWM signal.

[0014] The present invention was made to solve the above-mentioned problems, and its object is to provide a drive circuit that can drive the collector and gate of a CG-IGBT with the same PWM signal as a conventional IGBT using a low-cost structure, and a power conversion device having the drive circuit.

[0015] One aspect of the present invention for solving the above-mentioned problems is a driving circuit that drives a collector-gate controlled IGBT. The collector-gate controlled IGBT is an IGBT having an emitter, a collector, an emitter gate serving as the emitter-side gate, and a collector gate serving as the collector-side gate. The driving circuit has a first gate driver that drives the emitter-side gate and a second gate driver that drives the collector-side gate. The same driving command signal is input to the first gate driver and the second gate driver, and the second gate driver has a high-voltage diode that receives a signal based on the driving command signal.

[0016] A more specific structure of the present invention is described in the claims.

[0017] According to the present invention, a drive circuit capable of driving the collector gate of a CG-IGBT with the same PWM signal as a conventional IGBT using a low-cost structure, and a power conversion device having the drive circuit, are provided.

[0018] Other issues, structures, and effects beyond those described above will become clear through the following description of the implementation methods. Attached Figure Description

[0019] Figure 1 This is a partial cross-sectional view showing a portion of the CG-IGBT of Embodiment 1.

[0020] Figure 2 (a) is the equivalent circuit diagram of the CG-IGBT of Example 1, and (b) is the notation of the CG-IGBT of Example 1.

[0021] Figure 3 (a) is a diagram showing a portion of the CG-IGBT and its driving circuit of Embodiment 1, (b) is a timing diagram of the CG-IGBT and its driving circuit of Embodiment 1, and (c) is the cutoff waveform of the CG-IGBT of Embodiment 1.

[0022] Figure 4 This is a circuit diagram showing a first variation of Embodiment 1.

[0023] Figure 5 This is a circuit diagram showing a second variation of Embodiment 1.

[0024] Figure 6 (a) is a circuit diagram showing the third variation of Embodiment 1, and (b) is... Figure 6 Timing diagram of CG-IGBT (a).

[0025] Figure 7 This is a timing diagram of the PWM signal, gate voltage (Vg), and collector-gate voltage (Vcg) in Example 1 when this branch is in recirculation operation.

[0026] Figure 8 (a) is a diagram showing a portion of the CG-IGBT and its driving circuit of Embodiment 2, and (b) is a timing diagram of the CG-IGBT of Embodiment 2.

[0027] Figure 9 (a) is a circuit diagram showing an example of the CG-IGBT and its driving circuit of Embodiment 3, and (b) is a timing diagram of the CG-IGBT of Embodiment 3. Detailed Implementation

[0028] The following is a reference to the appendix. Figure 1 The present invention will be described in detail below.

[0029] Example 1

[0030] Figure 1 This is a partial cross-sectional structural diagram showing a portion of the CG-IGBT of Embodiment 1. (See diagram below.) Figure 1 As shown, a buried oxide film 2 is formed on a support substrate 1 made of Si. A p-base region 4 is selectively formed on the surface layer of the n-type semiconductor layer 3. An n-emitter region 5 is formed on a portion of the surface layer of the p-base region 4, and a p-anode region 6 is formed adjacent to the n-emitter region 5. In addition, n-buffer regions 7 are selectively formed in different regions within the surface layer of the n-type semiconductor layer 3. A p-base region 8 is formed on a portion of the surface layer of the n-buffer region 7. An n-cathode region 9 is formed on a portion of the surface layer of the p-base region. A p-collector region 10 is formed on another portion of the surface layer of the p-base region.

[0031] Furthermore, a gate electrode 13, connected to the gate terminal (G), is disposed on the surface of the channel region 11 of the surface layer of the p-base region 4, with a gate oxide film 12 in between. A collector gate electrode 16, connected to the collector gate terminal (CG), is disposed on the surface of the channel region 14 of the surface layer of the p-base region 8, with a gate oxide film 15 in between. Additionally, an emitter electrode 17, which is in common contact with the surfaces of the n-emitter region 5 and the p-anode region 6, and a collector electrode 18, which is in common contact with the surfaces of the p-collector region 10 and the n-cathode region 9, are respectively connected to the emitter terminal (E) and the collector terminal (C).

[0032] Here, as an example of CG-IGBT, we will use CG-RC-IGBT for illustration, but it is not limited to this. CG-IGBTs that are not reverse-conducting IGBTs can also be used.

[0033] Figure 2 (a) is the equivalent circuit diagram of the CG-IGBT in Example 1. Figure 2 (b) is a notation indicating the CG-IGBT of Embodiment 1 of the present invention. Figure 2 As shown in (a), the CG-IGBT of the present invention is characterized by including an NMOS 101 and a built-in diode 102, compared to a conventional IGBT. The NMOS 101 is normally-off, and its on / off state is controlled by the collector-gate CG.

[0034] When the collector gate CG is off (NMOS101 is off), it operates the same as a typical IGBT. If the collector gate CG is off and the gate G (although still called the emitter-side gate, it is simply referred to as "gate" since it is equivalent to the conventional gate) is off, the collector-emitter connection is cut off in the positive direction. If the collector gate CG is off and the gate G is on, it conducts in a bipolar manner, just like a typical IGBT.

[0035] With gate G on and collector gate CG on (NMOS 101 on), the base-emitter junction of pnp transistor 103 is short-circuited, and pnp transistor 103 is turned off. Therefore, the CG-IGBT operates as a unipolar device through which only electron current flows via channel region 11, n-type semiconductor layer 3, and channel region 14. When the on-current increases and the voltage drop between the drain and source of NMOS 101 increases, a voltage occurs between the base and emitter of pnp transistor 103, and pnp transistor 103 turns on, thus enabling bipolar operation. Furthermore, when operating as a unipolar device, the losses are greater compared to when operating bipolarly.

[0036] Furthermore, in the case of CG-RC-IGBT, when the collector gate CG is on, the gate G is off, and the NMOS 103 is on, reverse conduction current can flow through the built-in diode 102 and the NMOS 101. If the collector gate CG is on, and the gate G is on when reverse conduction current flows, the anode-cathode of the built-in diode 102 is short-circuited, and no current flows through the built-in diode 102, performing unipolar operation where only electron current flows through the channel region 11, the n-type semiconductor layer 3, and the channel region 14.

[0037] In this embodiment, the following uses Figure 2 The notation shown in (b) is used to describe CG-IGBT.

[0038] Figure 3 Figure (a) is a diagram showing a portion of the CG-IGBT and its drive circuit of Embodiment 1. A PWM-based drive command signal is input to the drive command signal input section (sig). In this embodiment, for example, 0V is input when off and 15V is input when on. Vdd is the power supply for the gate drive circuit.

[0039] The portion including the structure of symbols 201 to 204 is a first gate driver that drives the gate (G) on the emitter side, and the portion including the structure of symbols 205 to 209 is a second gate driver that drives the gate (CG) on the collector side.

[0040] In this embodiment, the same drive command signal is input to the first gate driver and the second gate driver, and the second gate driver has a high-voltage diode 206 that receives a signal based on the drive command signal.

[0041] The drive command signal is input to the CMOS inverter circuit 201 of the first gate driver. After the signal is inverted, the phase of the signal is changed by the delay generation unit 202. The delay generation unit is composed of resistors, etc. Then, after the signal is inverted by the CMOS inverter circuit 203, it is input to the gate (G) via the gate resistor (Rge) 204.

[0042] Additionally, the same drive command signal is input to the anode of the high-voltage diode 206 via the CMOS inverter circuit 205 of the second gate driver. The cathode of the high-voltage diode 206 is connected to the collector terminal (C) via resistor 207, and the cathode of the high-voltage diode is connected to the collector gate terminal (CG) via collector gate resistor (Rcg) 208. Furthermore, the collector gate terminal and the collector terminal are connected via Zener diode 209 to prevent overvoltage from being applied to the collector gate terminal. In this embodiment, for return current operation, an external return current diode 210 is connected in anti-parallel to the CG-IGBT. Therefore, it is also possible to omit the use of... Figure 1 The CG-RC-IGBT shown is not the CG-IGBT used; instead, a CG-IGBT that is not a reverse-conducting IGBT is used.

[0043] The actions will be explained next. Figure 3 (b) is a timing diagram illustrating an example of the CG-IGBT and its driving circuit of Embodiment 1. Figure 3 (b) shows the PWM signals (paired branch (RA) and local branch (OA)), gate voltage (Vg), and collector-gate voltage (Vcg) from the turn-on operation to the turn-off operation. The gate voltage is expressed with reference to the emitter potential, but the collector-gate voltage is expressed with reference to the collector voltage.

[0044] When the drive command signal for this branch is input as an open signal, the gate voltage (Vg) of this branch is 0V or a negative voltage, and the gate is in an open state. At this time, the potentials of the collector (C) and collector-gate (CG) become high voltages. The potential of the cathode of the high-voltage diode 206 is higher than the potential of the anode (maximum Vdd), so the signal based on the drive command signal is not transmitted to CG. CG and C are connected through resistors 207 and Rcg208, so the potentials of CG and C are equal, and the collector gate CG is in an open state. Next, when the drive command signal for this branch is input as an on signal, the gate voltage Vg rises through the first gate driver, and the gate of this branch becomes on. When the gate of CG-IGBT is on, the potentials of C and CG decrease, so the collector gate can be controlled by the drive command signal. The drive command signal (on at this time) is inverted by the CMOS inverter circuit 205 through the second gate driver to obtain a signal (open), which is then applied to the collector gate CG, so the collector gate CG remains in an open state. Therefore, CG-IGBTs can carry current in the same way as ordinary IGBTs. By reducing the turn-on voltage through conductance modulation based on bipolar operation, conduction losses can be reduced.

[0045] Next, when the drive command signal in this branch switches from on to off, the signal (on) obtained by inverting the drive command signal (which is off at this time) using the CMOS inverter circuit 205 via the second gate driver is applied to the collector gate CG, so Vcg rises and the collector gate CG turns on. On the other hand, in the first gate driver, the drive command signal delayed by the delay generation unit 202 is input to the gate G, so for example, after 1μs, the gate G turns off and the CG-IGBT turns off. The period from the rise of Vcg to the fall of Vcg can be arbitrarily adjusted by the delay generation unit 202. By making Vcg rise, thereby Figure 2 When the built-in NMOS 101 is turned on, the conductivity modulation of the built-in PNP transistor 103 is suppressed, and the carrier density in the CG-IGBT is reduced. By turning on the collector gate CG before the CG-IGBT is turned off (turning on the collector gate before turning off the emitter gate), the carrier density is reduced, thereby reducing the cutoff loss when the CG-IGBT turns off as Vg decreases.

[0046] Figure 3 (c) shows the cutoff waveform of the CG-IGBT in Example 1. The horizontal axis represents time, showing the current Ic1 and voltage Vc1 when the CG is turned on 1 μs before cutoff, and the current Ic2 and voltage Vc2 when the CG is always off without synchronous control. The integral of the product of current and voltage is the loss, but by turning on the CG earlier than cutoff, the carrier density is reduced, so the current Ic1 becomes 0 earlier than the current Ic2, thus reducing the cutoff loss. After cutoff, the potentials of C and CG become high voltages. Due to the high-voltage diode 206, no signal based on the drive command signal is input to the collector-gate CG, so through the discharge via Rcg208 and resistor 207, CG becomes the same potential as C.

[0047] This example shows the CG being turned on earlier than the cutoff point, but it is also possible to turn on the collector-side gate when the emitter-side gate is turned off, without using the delay generation unit 202 for delay. In this case, the effect is smaller compared to the case of turning on the CG earlier than the cutoff point, but the cutoff loss can be reduced compared to the case where the CG is always off without synchronous control of the CG.

[0048] As explained above, in this embodiment, the second gate driver has a high-voltage diode 206 that receives a signal based on the drive command signal, thus preventing the signal based on the drive command signal from being transmitted to the collector gate CG when the potentials of the collector (C) and collector gate (CG) are high. Therefore, it is possible to configure the first gate driver and the second gate driver to receive the same drive command signal for control.

[0049] Figure 4 This is the first variation of Example 1. Figure 3 In (a), when the capacitance of the high-voltage diode 206 is large, the charge accumulated in CG through the recovery current flowing through the high-voltage diode 206 is discharged when the CG-IGBT is turned off, potentially causing CG to disconnect during the turn-off process. To reduce turn-off losses, it is preferable that CG is in the on state before the turn-off is complete. Therefore, Figure 4 This illustrates a structure where the CG is not easily disconnected when the CG-IGBT is in cutoff mode. (Compared to...) Figure 3 The difference lies in the fact that a diode 301 is connected between C and the cathode of the high-voltage diode 206. When the CG-IGBT is turned off, a recovery current can flow from C through diode 301 to the high-voltage diode 206, thus suppressing the discharge of the charge accumulated in CG and keeping CG in the on state during the off period. That is, when the gate on the emitter side is turned off, the gate on the collector side can be kept on.

[0050] Figure 5 This is the second variation of Example 1. Compared to Figure 4 Its characteristic lies in its ability to further suppress the discharge of charge accumulated in CG. (And) Figure 4 The difference lies in the fact that a diode 302 is connected between the cathode of the high-voltage diode 206 and Rcg208. When the CG-IGBT is off, in... Figure 4 In this structure, the cathode potential of the high-voltage diode 206 is lower than the voltage drop of diode 301 relative to the potential of C. CG and the cathode of the high-voltage diode 206 are connected via Rcg208, so the charge of CG is discharged according to the capacitance of CG and the CR time constant of Rcg208. Figure 5 In this circuit, a diode 302 is placed between the cathode of the high-voltage diode 206 and Rcg208, so the diode 302 can be used to suppress the discharge of the charge accumulated in CG.

[0051] Figure 6 Example (a) is a third variation of Example 1. This is also an implementation for maintaining the CG in the on state during the off period of the CG-IGBT. Compared to Figure 3In (a), the focus is on the fact that Vdd is connected to C via a high-voltage diode 401 and a capacitor 402, and that a drive command signal is input to CG from the cathode of the high-voltage diode 206 via CMOS inverter circuits 403, 404 and Rcg208, and a resistor 405 is used to connect the cathode of the high-voltage diode 206 and C.

[0052] When the CG-IGBT is on, or when the potential of C is low during the return current operation, charge can be supplied to capacitor 402 from Vdd. When the drive command signal of this branch switches from on to off, the drive command signal inverted by the second gate driver is applied to the collector gate, Vcg rises, and the collector gate CG is on. At this time, voltage is supplied to CG from capacitor 402 via CMOS inverter circuit 404 and Rcg208. Afterwards (for example, after 1μs), the gate G is turned off by the delay generation unit 202, and the CG-IGBT is turned off. Charge can also be supplied to CG from capacitor 402 during the off period, so CG can remain on during the off period. When the CG-IGBT is off and the potential of C rises, the drive command signal is cut off by the high-voltage diode 206, so by discharging through resistor 405, the cathode of the high-voltage diode 206 becomes the same potential as C, the output of CMOS inverter 404 becomes low, and CG is off.

[0053] Figure 6 (b) is Figure 6 The timing diagram for (a) is shown. Figure 6 The graph shows the PWM signal, gate voltage (Vg), and collector-gate voltage (Vcg) during the turn-on and turn-off operations of (a). In conjunction with... Figure 3 Compared to (b), the difference is that after the cutoff, the collector gate CG is turned off after maintaining the on state for a certain period of time.

[0054] Example 2

[0055] Figure 7 This is a timing diagram of the PWM signal, gate voltage (Vg), and collector-gate voltage (Vcg) during the recirculation operation in Embodiment 1. Embodiment 2 further discloses a structure that provides optimal gate and collector-gate control during recirculation. Figure 7 As shown, during the final failure time (Td) of the return current period (RP), Vg is off and Vcg is on. The built-in diode 102 of the CG-RC-IGBT... Figure 2 Since (a) is turned on, when the circuit transitions from the return state to the off state, not only the return diode 210, but also the recovery current of the built-in diode 102 flows, so the total recovery current may increase.

[0056] Therefore, a circuit structure is disclosed that can autonomously provide optimal gate and collector gate control during forward conduction (IGBT on) and reverse conduction (return current), respectively. To this end, a return current detection circuit is provided that detects the return current and controls it by keeping the gate on the collector side in an open state throughout the return current period. Figure 8 Figure (a) is a diagram showing a portion of the drive circuit of Embodiment 2. It is characterized by... Figure 5 The difference lies in that the emitter is connected to the collector via diode 501 and high-voltage diode 502; the emitter (E) is connected to the non-inverting input terminal of comparator 503; the cathode of diode 501 is connected to the inverting input terminal; Vdd is connected to the positive power supply; and a drive command signal input (sig) is connected to the negative power supply. The output (O) of comparator 503 is connected to the input of the CMOS inverter circuit 205 used to drive CG. Furthermore, this is applied to... Figure 5 The examples provided illustrate this, but are not limited to this; they can also be applied to... Figure 3 , Figure 4 The structure is as described in the diagram. When the collector-emitter voltage Vce is above 0V, i.e., not in a reflux state, the output O of comparator 503 becomes the same potential as the drive command signal input to sig, thus operating in the same manner as in Embodiment 1. When Vce is negative, i.e., in reflux operation, due to the voltage sharing between diode 501 and the high-voltage diode 502, the cathode potential of diode 501 becomes lower than E, and the output O of comparator 503 becomes Vdd. Therefore, CG is fixed in the off state.

[0057] Figure 8 (b) is the timing diagram of the CG-IGBT in Example 2. Figure 8 (b) shows the timing diagram of the PWM signal, gate voltage (Vg), and collector-gate voltage (Vcg) when this branch is in return current operation. The key feature is that Vcg remains off during the entire return current operation (FW). Therefore, the CG-IGBT does not conduct in reverse during the entire return current operation (FW), so no recovery current caused by the CG-IGBT occurs when transitioning from the return current state to the off state. This reduces the total recovery current.

[0058] Thus, in Embodiment 2, by controlling the CG-RC-IGBT in a manner that prevents reverse conduction during reflow, it is possible to operate as a CG-IGBT that is not reverse-conducting.

[0059] Example 3

[0060] In Embodiment 3, the following structure is disclosed: during the reflow operation, the built-in diode 102 is used as a reflow diode and is used as a CG-RC-IGBT. Figure 7 The diagram shows the timing of the PWM signal, gate voltage (Vg), and collector-gate voltage (Vcg) during the return current operation in Embodiment 1. During the return current period, the gate is turned on according to the PWM signal. Conversely, the collector-gate is off for a longer period during the return current period. During the return current period, the built-in diode 102 is turned on; for use as a CG-RC-IGBT, it is preferable that the gate is off and the collector-gate is on during the return current period.

[0061] Therefore, in embodiment 3, a reflow detection circuit is provided that detects the reflow and controls the reflow by keeping the gate on the emitter side open throughout the reflow.

[0062] Figure 9 (a) is a circuit diagram showing an example of the CG-IGBT and its driving circuit of Embodiment 3.

[0063] and Figure 8 The difference in (a) is that the return diode 210 is removed, the emitter is connected to the inverting input terminal of comparator 503, the cathode of diode 501 is connected to the non-inverting input terminal, a drive command signal input section (sig) is connected to the positive power supply, and the emitter terminal is connected to the negative power supply. The output (O) of comparator 503 is connected to the input section of the CMOS inverter circuit 201 for gate driving and the input section of the CMOS inverter circuit 205 for collector-gate driving. Furthermore, this description uses the removal of the return diode 210 as an example, but the return diode 210 can also be provided.

[0064] When Vce is above 0V, i.e., not in a return current state, the comparator output becomes the same potential as sig, thus operating in the same manner as in Example 1. When Vce is negative, i.e., in return current operation, due to the voltage sharing between diode 501 and high-voltage diode 502, the cathode potential of diode 501 becomes lower than E, and the comparator output becomes potential E. Therefore, G is fixed in the off state, while CG is fixed in the on state. Figure 9 (b) is the timing diagram of the CG-IGBT in Example 3. Figure 9(b) shows the timing diagram of the PWM signal, gate voltage (Vg), and collector-gate voltage (Vcg) when this branch is in the return current operation. The key feature is that during the entire return current period (FW), Vg remains off, while Vcg remains on. When the paired branch is on and this branch transitions from the return current operation to the off state, the potentials of C and CG rise, the signal from the comparator output O is cut off, and CG becomes the same potential as C through discharge via resistor 207. Therefore, according to this embodiment, the gate can be kept off and the collector-gate on during the return current period, thus enabling it to be used as a CG-RC-IGBT that also operates as a reverse-biased IGBT during the return current operation.

[0065] As described above, according to the present invention, a drive circuit is provided that can drive the collector and gate of a CG-IGBT using the same PWM signal as a conventional IGBT with a low-cost structure.

[0066] The drive circuit for the CG-IGBT of the present invention described above can be applied to power conversion devices (inverters, etc.) that incorporate CG-IGBTs. The drive circuit for the CG-IGBT of the present invention can simultaneously achieve low turn-on voltage and low switching losses, thus enabling the realization of a power conversion device with high efficiency.

[0067] Furthermore, the present invention is not limited to the above embodiments, but includes various modifications.

[0068] For example, the embodiments described above are examples provided to illustrate the present invention in detail for ease of understanding, and are not limited to possessing all the structures described. Furthermore, a portion of the structure of one embodiment can be replaced with the structure of another embodiment, and the structure of another embodiment can be added to the structure of one embodiment. Additionally, the structure of each embodiment can be supplemented, deleted, or replaced with other structures.

[0069] Explanation of symbols

[0070] 1: Support substrate made of Si; 2: Buried oxide film; 3: n-type semiconductor layer; 4: p-base region; 5: n-emitter region; 6: p-anode region; 7: n-buffer region; 8: p-base region; 9: n-cathode region; 10: p-collector region; 11: Channel region; 12: Gate oxide film; 13: Gate electrode; 14: Channel region; 15: Gate oxide film; 16: Collector electrode; 17: Emitter electrode; 18: Collector electrode; 101: NMOS; 102: Built-in diode; 103: pnp transistor; 201: CMOS inverter Inverter circuit; 202: Delay generation section; 203: CMOS inverter circuit; 204: Gate resistor; 205: CMOS inverter circuit; 206: High-voltage diode; 207: Resistor; 208: Collector-gate resistor; 209: Zener diode; 210: Return current diode; 301: Diode; 302: Diode; 401: High-voltage diode; 402: Capacitor; 403: CMOS inverter circuit; 404: CMOS inverter circuit; 405: Resistor; 501: Diode; 502: High-voltage diode; 503: Comparator.

Claims

1. A driving circuit for driving a collector-gate controlled IGBT, wherein the collector-gate controlled IGBT is an IGBT having an emitter, a collector, an emitter gate serving as the emitter-side gate, and a collector gate serving as the collector-side gate, the driving circuit being characterized in that... The driving circuit has a first gate driver that drives the gate on the emitter side and a second gate driver that drives the gate on the collector side. The same drive command signal is input to the first gate driver and the second gate driver, and, The second gate driver has a high-voltage diode that is input with a signal based on the drive command signal.

2. The driving circuit according to claim 1, characterized in that, The first gate driver and the second gate driver turn on the collector-side gate before turning off the emitter-side gate.

3. The driving circuit according to claim 1, characterized in that, The first gate driver and the second gate driver turn on the collector-side gate when the emitter-side gate is turned off.

4. The driving circuit according to any one of claims 1 to 3, characterized in that, One of the first gate driver and the second gate driver has an inverting circuit that inverts the drive command signal.

5. The driving circuit according to any one of claims 1 to 3, characterized in that, The drive circuit includes a backflow detection circuit that detects backflow and controls the circuit to keep the gate on the emitter side open throughout the backflow period.

6. The driving circuit according to any one of claims 1 to 3, characterized in that, The collector-gate controlled IGBT is a collector-gate controlled reverse conduction IGBT.

7. The driving circuit according to claim 6, characterized in that, The driving circuit has: An external return diode is connected to the collector-gate controlled reverse-biased IGBT; and The return current detection circuit detects the return current and controls it to keep the gate on the collector side off throughout the return current process.

8. A power conversion device, characterized in that, have: The driving circuit according to any one of claims 1 to 3; and Collector-gate control IGBT.

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