Method, system, and non-transitory computer-readable storage medium for corrective programming and power loss management

Abstract

The present application relates to a method, system, and non-transitory computer-readable storage medium for corrective programming and power loss management. Exemplary methods, apparatus, and systems are included for controlling a program manager for writing data bits to a memory device. The program manager receives a first set of data bits for programming to a memory. During a first programming pass, the program manager writes a first subset of data bits to a first word line. The program manager writes a second subset of data bits in the first set of data bits to a buffer. The program manager receives a second set of data bits for programming. The program manager writes the second subset of data bits in the first set of data bits to the first word line during a second programming pass in response to receiving the second set of data bits to increase the bit density of memory cells in the first word line.

Description

Technical Field

[0001] The present disclosure relates generally to corrective programming and power loss management of memory devices, and more specifically to two-pass corrective programming of memory cells that each store multiple bits and power loss management of the two-pass corrective programming. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] An embodiment of the present disclosure provides a method, which includes: receiving a first group of data bits for programming to a memory; writing a first subset of the data bits of the first group to a first word line of the memory during a first programming pass; writing a second subset of data bits in the first group of data bits to a buffer, wherein the second subset of data bits is different from the first subset of data bits; receiving a second group of data bits for programming, wherein the second group of data bits are to be programmed to a second word line; and in response to receiving the second group of data bits, writing the second subset of data bits in the first group of data bits to the first word line during a second programming pass, the writing of the second subset of data bits comprising an increase in the bit density of memory cells in the first word line.

[0004] Another embodiment of the present disclosure provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform the following operations: receive a first set of data pages for programming to a memory, wherein the first set of pages includes four pages; write a first subset of pages to a first word line during a first programming pass; write a selected page of the first set of pages to a buffer, wherein the selected page is different from each page of the first subset of pages; receive a second set of pages for programming; and write the selected page of the first set of pages to the first word line during a second programming pass, wherein the writing of the selected page includes applying an adjustment voltage to the selected page using the second set of pages, wherein the writing of the selected page includes increasing the bit density of memory cells in the first word line.

[0005] Yet another embodiment of the present disclosure provides a system comprising: a memory device; and a processing device operably coupled to a plurality of memory devices to: receive a first set of data bits for programming into a memory; write a first subset of the data bits to a first word line during a first programming pass; write a second subset of data bits in the first set of data bits to a buffer, wherein the second subset of data bits is different from the first subset of data bits; receive a second set of data bits for programming; and write the second subset of data bits to the first word line during a second programming pass, wherein writing the second subset of data bits includes applying an adjustment voltage to a threshold voltage of the second subset of data bits using the second set of data bits, wherein writing the second subset of data bits includes increasing the bit density of memory cells in the first word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1 An example computing system including a memory subsystem that performs programming passes according to some embodiments of the present disclosure is described.

[0008] Figure 2 An example of a process of performing programming passes according to an embodiment of the present disclosure is described.

[0009] Figure 3 is an example of applying an adjustment voltage to one or more bits of a word line according to some embodiments of the present disclosure.

[0010] Figure 4 is a flowchart of an example method to perform programming passes according to an embodiment of the present disclosure.

[0011] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0012] Aspects of the present disclosure relate to two-pass corrective programming in a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0013] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The die in the package can be assigned to one or more channels for communicating with the memory subsystem controller. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0014] Depending on the cell type, a cell can store one or more bits of binary information and have various logic states related to the number of bits stored. The logic state can be represented by a binary value, such as "0" and "1", or a combination of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), three-level cells (TLCs), and four-level cells (QLCs). For example, an SLC can store one bit of information and have two logic states.

[0015] The use of four-level cells improves memory storage, but generally results in large buffer requirements to buffer data bits, such as with 16-16 two-pass programming. In the 16-16 two-pass programming, the first pass includes coarse data programming, while the second pass includes fine data programming. For example, the coarse data programming programs the QLC to 16 threshold voltage (Vt) states (representing 16 different combinations of 4 bits), but leaves the data in an unreadable state. To prevent data loss and otherwise provide access to the data, the corresponding data is also stored in a buffer until the fine data second-pass programming is completed, which leaves the data in a readable 16Vt state. This large buffer requirement incurs an over-provisioning penalty (extra storage beyond the user-accessible storage space).

[0016] Aspects of the present disclosure address the above and other deficiencies by writing a subset of data bits to memory in a readable state in a first pass and buffering the remainder of the set of data bits for writing to memory in a second pass. By writing only a subset of the data bits to memory, the first pass is written in a readable state and the buffer size for the data bits written in the second pass is reduced. During the second pass, the buffered bits are written to increase the bit density of the previously written memory cells. For example, the buffered subset of data bits may represent a selected page, such as a "top page" (TP) of a group of four pages written to a QLC memory.

[0017] Figure 1An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0018] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0019] Computing system 100 may be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other vehicle), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0020] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0021] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, the host system 120 uses the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0022] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Small Computer System Interface (SCSI), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130) when the memory subsystem 110 is coupled to the host system 120 through a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0023] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0024] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in body resistance in conjunction with a stackable cross-grid data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, where non-volatile memory cells can be programmed without having to erase the non-volatile memory cells in advance. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0025] Although nonvolatile memory devices such as NAND-type memories (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of nonvolatile memory cells are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0026] The memory subsystem controller 115 (or controller 115 for simplicity) may communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations (e.g., in response to commands dispatched by the controller 115 on a command bus). The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0027] The memory subsystem controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store various processes, operations, logic flows, and routines for executing control of the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0028] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem 110).

[0029] In general, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 120.

[0030] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0031] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0032] Memory subsystem 110 includes a program manager 113 that can select subsets of received data bits for first and second pass programming of cells of memory device 130. In some embodiments, controller 115 includes at least a portion of program manager 113. For example, controller 115 may include processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, program manager 113 is part of host system 120, application program, or operating system.

[0033] Program manager 113 controls how received data bits are written to the memory device in multiple programming passes. In doing so, program manager 113 reduces the amount of data buffered per pass. For example, if program manager 113 receives a first set of data bits for programming to the memory. In an example, the first set of data bits includes four pages of data, and program manager 113 may write a subset of the data to the memory device in a readable state (e.g., three pages of data are written to the word line of the memory cell in an 8Vt state). Program manager 113 may write the remaining subset of bits (e.g., the last page of data) to a buffer, such as a NAND latch, an SLC block, or a volatile memory. Program manager 113 may write the remaining subset of bits stored in the buffer to the memory device in a second programming pass (e.g., a full four pages of data are written to the word line of the memory cell in a sixteen Vt state). In one embodiment, after receiving a second set of data bits (e.g., another four pages of data), the program manager performs a second programming pass. Additional details regarding the operation of program manager 113 are described below.

[0034] Figure 2 An example of a process for performing a programming pass according to an embodiment of the present disclosure is described. Method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by Figure 1 The processes are executed by the programming manager 113 of the embodiment. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0035] At operation 205, program manager 113 receives a first set of data pages for programming. Program manager 113 is configured to receive a number of sets of data bits for programming to the memory device. For example, program manager 113 may receive a data stream from host system 120, the data stream comprising multiple sets of data pages. In some embodiments, program manager 113 receives at least four data pages for writing to a QLC word line. The examples stated herein refer to QLC word lines and a number of sets of data pages, but other subdivisions of memory and other sets / groupings of data may be used.

[0036] At operation 210, program manager 113 writes a first subset of pages to a first word line during a first programming pass. Program manager 113 selects a number of pages to write to the QLC on the first word line. For example, program manager selects three pages of the first set of pages received in operation 205 to write to memory (e.g., similar to programming an 8Vt readable state of TLC memory). Because program manager 113 only writes a subset of pages (e.g., three pages) to memory, the memory cells of the word line are written in a readable 8Vt state. In another embodiment, program manager 113 selects two pages and writes them to memory (e.g., similar to programming an MLC memory at a 4Vt readable state).

[0037] At operation 215, program manager 113 writes the selected page of the first set of pages to the buffer. In the above example where program manager 113 writes a first subset of data consisting of three pages to the first word line, a second subset of data consisting of the remaining one page (e.g., a fourth page, such as TP) is written by program manager 113 to the buffer location. In event recovery, the fourth page may be accessed from the buffer or a read is required before writing the fourth page to the first word line. In an embodiment, program manager 113 writes a first subset of two pages to the first word line, and program manager 113 writes a second subset of the remaining two pages to the buffer.

[0038] At operation 220, program manager 113 receives a second set of pages for programming. Similar to the description above regarding operation 205, program manager 113 is configured to receive multiple sets of data bits for programming to the memory device. Program manager 113 receives a second set of four data pages for writing to a second QLC word line.

[0039] At operation 225, the program manager uses the second set of pages to determine an adjustment to the threshold voltage value for programming the selected page to the first word line. For example, after receiving the second set of pages for programming, the program manager determines an adjustment voltage for writing the selected page in the second programming pass, resulting in a word line programmed in the 16Vt state. The adjustment voltage may, for example, take into account interference or other parasitic effects that the program manager 113 estimates will result from programming the second set of pages to the adjacent second word line. In some embodiments, the program manager adjusts the threshold voltage by a first adjustment voltage for a number of pages in the second set of pages to be programmed in the first programming pass. In other cases, the program manager adjusts the threshold voltage by a different adjustment voltage for a different (e.g., more or fewer pages) number of pages in the second set of pages to be programmed in the first programming pass. The program manager is configured to determine the adjustment voltage according to design parameters of the memory device. In one embodiment, when the number of pages of the second set of pages to be programmed in the first pass is small, the program manager applies a larger adjustment voltage (larger increase).

[0040] At operation 230, the program manager 113 writes the selected page to the first word line during a second programming pass. The second programming pass increases the bit density of the cells of the first word line. For example, after receiving the second set of pages for programming, the program manager 113 writes the last page from the buffer to the first word line using the determined adjustment to the threshold voltage value, thereby completing programming of the first set of data pages in a final programmed state (e.g., a 16Vt readable state for each QLC of the QLC word line) for a particular type of memory cell.

[0041] Figure 3 is an example of applying an adjustment voltage to one or more bits of a word line according to some embodiments of the present disclosure. As described above, program manager 113 writes a first QLC word line in memory device 130 by programming the word line to an 8Vt state during a first programming pass. After receiving a second set of data bits (including four pages of data to be written to the second QLC word line), program manager 113 may perform a second programming pass on the first QLC word line. The examples set forth herein relate to QLC word lines, 8Vt states, and 16Vt states, however, other numbers of Vt states may be used depending on the initial and final programming states of each type of memory cell.

[0042] As in Figure 3, QLC word line 300 has a distribution of voltage values ​​302-306 representing 8Vt states of binary values ​​000, 001, 010, 011, 100, 101, 110, and 111. Although the binary values ​​are shown adjacent to each other, other arrangements or different locations, such as using Gray code, are possible. A second programming pass increases the possible distribution of voltage values ​​to 16 Vt states representing binary values ​​0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, and 1111. As bits are added, each binary value in the 8Vt state can be shifted to represent two different binary values ​​in the 16Vt state. For example, if a first programming pass programs the QLC to binary value 001 (represented by voltage distribution value 304), then a second programming pass updates the QLC to binary value 0010 or 0011 (represented by the distribution of voltage values ​​308), depending on the value of the bit added by the buffered page (e.g., top page TP).

[0043] As discussed with reference to operations 220 and 225, the program manager 113 may apply an adjustment to the threshold voltage for the second programming pass before writing the fourth page to the QLC word line. For example, when three pages are written to the first QLC word line in the first programming pass, the fourth page is written to the buffer. After receiving the second set of four pages, the program manager may adjust the threshold voltage before writing the four pages to the QLC word line depending on the second pass state of the second set of four pages. In one embodiment, the program manager adjusts the threshold voltage of the final programmed state by a first amount for a number of pages to be programmed in the first pass of the second set of four pages, and adjusts the threshold voltage by a different amount (i.e., adding a larger second amount to the threshold voltage) for a different number of pages to be programmed in the first pass of the second set of four pages. Thus, the program manager 113 takes into account any interference or parasitic effects of programming the second word line that may shift the voltage value of the first word line. After the program manager 113 programs the second word line, the voltage value of the first word line should fall within the expected voltage distribution of the expected 16Vt state.

[0044] Figure 4 is a flow chart of an example method 400 for performing programming passes according to an embodiment of the present disclosure. The method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1The processes are executed by the programming manager 113 of the embodiment. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0045] At operation 405, program manager 113 receives a first set of data bits for programming to memory. As described above with respect to operation 205, program manager 113 is configured to receive several sets of data bits for programming to the memory device. In some embodiments, program manager 113 receives four pages of data for writing to a word line. In other embodiments, program manager receives any number of data bits that can be programmed to memory by the memory subsystem.

[0046] At operation 410, program manager 113 writes a first subset of data bits to a first word line during a first programming pass. From the first set of data bits received at operation 405, program manager 113 selects a first subset of data bits for writing to the first word line and a second subset of data bits for writing to the buffer. As described with respect to operation 210 above, program manager 113 performs a first programming pass writing the first subset of data bits to the first word line in a readable state.

[0047] At operation 415, the programming manager 113 writes a second subset of the first set of data bits to the buffer. For example, the second subset of data bits are data bits in the first set of data bits that were not programmed to the first word line during the first programming pass. As described above with respect to operation 215, the programming manager writes the second subset of data bits to a memory location different from the first word line, such as a buffer or a non-volatile memory location. Because the programming manager 113 writes the second subset of data bits to the buffer instead of the entire first set of data bits, the buffer size is reduced from the complete first set of data bits to the second subset of data bits. In the QLC word line example, for a four-page group of data bits, the first subset includes three pages written to the word line, and a fourth page of data bits is written to the buffer, reducing the buffer size by 75% compared to buffering the complete first set of data bits.

[0048] At operation 420, program manager 113 receives a second set of data bits for programming to the memory.As described above with respect to operation 220, program manager 113 receives a second set of pages for programming to a second word line.

[0049] At operation 425, the program manager writes a second subset of the data bits in the first set of data bits to the first word line during the second programming pass. As described above with respect to operation 225, program manager 113 writes the selected page or other subset of the buffered bits to the first word line during the second programming pass to increase the bit density of the memory cells of the first word line. Continuing with the previous example, in response to receiving the second set of four pages for programming to the memory, program manager 113 writes the fourth page stored in the buffer to the first word line. As described above with respect to operation 225, program manager 113 can use the value of each bit included in the second data bits to apply an adjustment to the threshold voltage to compensate for disturb or other parasitic effects of programming the second word line.

[0050] Figure 5 An example machine illustrating a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 500 may correspond to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or may be used to execute operations of the controller (eg, execute an operating system to execute operations corresponding to Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The computer may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0051] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0052] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 518, which communicate with each other via a bus 530.

[0053] The processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. The computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0054] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 526 or software embodying any one or more of the methodologies or functions described herein. During execution of the instructions 526 by the computer system 500, the instructions 526 may also reside, in whole or in part, within the main memory 504 and / or within the processing device 502, which also constitute machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 Memory subsystem 110.

[0055] In one embodiment, instructions 526 include instructions to implement instructions corresponding to a program manager (e.g., Figure 1 The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0056] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is generally considered here to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common sense reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0057] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve the actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into physical quantities similarly represented as within the computer system's memories or registers or other such information storage systems.

[0058] The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specifically constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. For example, a computer system or other data processing system such as controller 115 may perform computer-implemented methods 200 and 400 in response to its processor executing a computer program (e.g., sequence of instructions) contained in a memory or other non-transitory machine-readable storage medium. Such a computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0059] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. The structures of various these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0060] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0061] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: receiving a first set of data bits for programming into a memory; writing a first subset of data bits of the first group to a first word line of the memory during a first programming pass; writing a second subset of data bits in the first set of data bits to a buffer, wherein the second subset of data bits is different from the first subset of data bits; receiving a second set of data bits for programming, wherein the second set of data bits are to be programmed to a second word line; as well as The second subset of data bits in the first set of data bits is written to the first word line during a second programming pass in response to receiving the second set of data bits, the writing of the second subset of data bits comprising an increase in bit density of memory cells in the first word line.

2. The method of claim 1, wherein the writing the second subset of data bits comprises using the second set of data bits to determine an adjustment voltage for a threshold voltage of one or more bits in the second subset of data bits.

3. The method of claim 2, wherein the adjusting comprises: increasing the threshold voltage by a first amount for a number of bits in the second set of data bits to be programmed in a first programming pass; as well as The threshold voltage is increased by a second amount for a different number of bits in the second set of data bits to be programmed in a first programming pass.

4. The method of claim 1, further comprising writing a third subset of data bits from the second set of data bits to the second word line, wherein writing the third subset of data bits results in a shift in voltage of one or more bits of the first word line.

5. The method of claim 1, wherein the first set of data bits comprises four pages, and wherein the first subset of data bits comprises three pages. The method of claim 1 , wherein the first subset of data bits are written in a readable state.

7. The method of claim 1, wherein the buffer is a NAND latch, an SLC block, or a volatile memory.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving a first set of data pages for programming into a memory, wherein the first set of data pages comprises four pages; During a first programming pass, writing a first subset of pages to a first word line; writing a selected page of the first set of pages to a buffer, wherein the selected page is different from each page of the first subset of pages; receiving a second set of pages for programming; as well as Writing the selected page of the first set of pages to the first word line during a second programming pass, wherein the writing of the selected page includes applying an adjustment voltage to the selected page using the second set of pages, wherein the writing of the selected page includes increasing a bit density of memory cells in the first word line.

9. The non-transitory computer-readable storage medium of claim 8, wherein writing the selected pages is performed in response to receiving the second set of pages for programming.

10. The non-transitory computer-readable storage medium of claim 8, wherein applying the adjustment voltage comprises: increasing a threshold voltage by a first amount for a number of pages in the second set of pages to be programmed in a first programming pass; as well as The threshold voltage is increased by a second amount for a different number of pages in the second set of pages to be programmed in a first programming pass, wherein the second amount is greater than the first amount.

11. The non-transitory computer-readable storage medium of claim 8, the instructions further causing the processing device to write a third subset of pages from the second set of pages to a second word line, wherein writing the third subset of pages causes a shift in voltage of one or more bits of the first word line.

12. The non-transitory computer-readable storage medium of claim 8, wherein the first set of pages includes four pages, and wherein the first subset of pages is three pages.

13. The non-transitory computer-readable storage medium of claim 8, wherein the first subset of pages are written in a readable state.

14. The non-transitory computer-readable storage medium of claim 8, wherein the buffer is a NAND latch, an SLC block, or a volatile memory.

15. A system comprising: Memory device; and A processing device operatively coupled to a plurality of memory devices to: receiving a first set of data bits for programming into a memory; writing a first subset of data bits to a first word line during a first programming pass; writing a second subset of data bits in the first set of data bits to a buffer, wherein the second subset of data bits is different from the first subset of data bits; receiving a second set of data bits for programming; as well as The second subset of data bits is written to the first word line during a second programming pass, wherein writing the second subset of data bits includes applying an adjustment voltage to a threshold voltage of the second subset of data bits using the second group of data bits, wherein writing of the second subset of data bits includes increasing a bit density of memory cells in the first word line.

16. The system of claim 15, wherein the buffer is a NAND latch, an SLC block, or a volatile memory.

17. The system of claim 15, wherein applying said adjusting voltage to said threshold voltage of said second subset of data bits using said second set of data bits comprises: increasing the threshold voltage by a first amount for a number of bits in the second set of data bits to be programmed in a first programming pass; as well as The threshold voltage is increased by a second amount for a different number of bits in the second set of data bits to be programmed in a first programming pass, wherein the second amount is greater than the first amount.

18. The system of claim 15, wherein the processing device is further caused to write a third subset of data bits from the second set of data bits to a second word line, wherein writing the third subset of data bits results in a shift in the voltage of one or more bits of the first word line.

19. The system of claim 15, wherein the first set of data bits includes four pages, and wherein the first subset of data bits includes three pages.

20. The system of claim 15, wherein the first subset of data bits are written in a readable state.

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