FPGA-based high-throughput two-dimensional DCT phase unwrapping method

By deploying a two-dimensional DCT phase unwrapping method on an FPGA, and combining phase difference compensation and parallel processing techniques, the efficiency and accuracy issues of two-dimensional phase unwrapping under noise interference are solved, achieving efficient and low-power phase unwrapping.

CN117647179BActive Publication Date: 2026-07-24NANJING UNIV OF SCI & TECH
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Patent Information

Application Number
CN202311588999.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-11-24
Publication Date
2026-07-24
Estimated Expiration
2043-11-24

AI Technical Summary

Technical Problem

Existing technologies are inefficient and inaccurate in handling two-dimensional phase unwrapping under noise interference, and consume a lot of power when deployed on CPU/GPU. The complexity of neural network models also increases time costs.

Method used

A high-throughput two-dimensional DCT phase unpacking method based on FPGA is adopted. The unpacked phase data is obtained by a four-step phase shift method. Combined with phase difference compensation and parallel processing technology, the phase data is processed by FFT/IP and IFFT to achieve efficient unpacking.

Benefits of technology

It improves the accuracy and efficiency of package understanding, reduces power consumption, is more adaptable, and is suitable for the field of optical interferometry.

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Abstract

The application discloses a high-throughput two-dimensional DCT phase unwrapping method based on FPGA, and specifically relates to the following steps: carrying out gray processing and fixed-point number conversion on an original interference map to generate phase data information to be processed; carrying out data transmission after data cropping and splicing to obtain wrapped phase data containing noise; carrying out phase difference compensation on the wrapped phase data; carrying out mirror surface expansion on the wrapped phase data in a row direction, calling an FFT IP to carry out parallel processing, and carrying out mirror surface expansion in a column direction to obtain a forward two-dimensional DCT processing result; calling a divider IP to process the forward two-dimensional DCT data; carrying out mirror surface expansion on the data in the column direction, calling an IFFT IP to obtain a continuous one-dimensional IDCT processing result, then carrying out IDCT processing in the row direction to obtain unwrapped phase information. The application improves the phase unwrapping efficiency and the correctness of the unwrapping result, reduces the power consumption of algorithm execution, and is highly adaptable.
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