Read disturb scan merge

Abstract

This disclosure relates to read interference scan merging. A processing device in a memory system determines whether a first read count of a first data block on a first plane of a memory component satisfies a first threshold criterion. The processing device further determines whether a second read count of a second data block on a second plane of the memory component satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is less than the first threshold criterion. In response to the second read count satisfying the second threshold criterion, the processing device performs a multi-plane scan to determine a first error rate of the first data block and a second error rate of the second data block in parallel.

Description

[0001] Information related to divisional application

[0002] This application is a divisional application of Chinese invention patent application No. 201980077691.6, filed on October 23, 2019, entitled "Reading Interference Scan Merging". Technical Field

[0003] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to managing memory subsystems that include memory components with different characteristics. Background Technology

[0004] The memory subsystem can be a storage system, such as a solid-state drive (SSD) or a hard disk drive (HDD). The memory subsystem can also be a memory module, such as a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem can contain one or more memory components for storing data. These memory components can be, for example, non-volatile and volatile memory components. Generally, a host system can utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the Invention

[0005] In one aspect, this disclosure relates to a system comprising: a memory device; and a processing means operatively coupled to the memory device to perform the following operations: determining whether a first metric of a first memory cell on a first plane of the memory device satisfies a first threshold criterion; determining whether a second metric of a second memory cell on a second plane of the memory device satisfies a second threshold criterion and does not satisfy the first threshold criterion; and in response to the second metric satisfying the second threshold criterion and not satisfying the first threshold criterion, performing a multi-plane data integrity operation to determine, in parallel, a first reliability statistic of the first memory cell and a second reliability statistic of the second memory cell.

[0006] On the other hand, this disclosure relates to a method comprising: identifying a first memory cell on a first plane among a plurality of planes of a memory device, wherein a first metric of the first memory cell satisfies a first threshold criterion; identifying a second memory cell on a second plane among the plurality of planes, wherein a second metric of the second memory cell satisfies a second threshold criterion and does not satisfy the first threshold criterion; and, as part of a multi-plane data integrity operation, jointly reading data from the first memory cell and the second memory cell to determine whether a reliability statistic of the first memory cell or the second memory cell satisfies the error correction capability of the memory device.

[0007] In another aspect, this disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to: determine whether a first metric of a first memory cell on a first plane of the memory means satisfies a first threshold criterion; determine whether a second metric of a second memory cell on a second plane of the memory means satisfies a second threshold criterion and does not satisfy the first threshold criterion; and in response to the second metric satisfying the second threshold criterion and not satisfying the first threshold criterion, perform a multi-plane data integrity operation to determine, in parallel, a first reliability statistic of the first memory cell and a second reliability statistic of the second memory cell. Attached Figure Description

[0008] This disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments thereof.

[0009] Figure 1 This describes an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0010] Figure 2A and 2B A diagram illustrating read interference scan merging across multiple planes of a memory component according to some embodiments of the present disclosure.

[0011] Figure 3 This is a flowchart of an example method for merging read interference scans in a multi-plane scan performed simultaneously across multiple planes of a memory component, according to some embodiments of this disclosure.

[0012] Figure 4 This is a flowchart of an example method for merging read interference scans in a multi-plane scan performed simultaneously across multiple planes of a memory component, according to some embodiments of this disclosure.

[0013] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may operate. Detailed Implementation

[0014] This disclosure relates to read interference scan merging across multiple planes of a memory component, used to minimize system bandwidth penalties in a memory subsystem. The memory subsystem is also referred to hereinafter as a "memory device." Examples of memory subsystems are storage devices coupled to a central processing unit (CPU) via peripheral interconnects (e.g., input / output buses, memory area networks). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to the CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), etc. In some embodiments, the memory subsystem may be a hybrid memory / storage subsystem. Typically, a host system may utilize a memory subsystem comprising one or more memory components. The host system can provide data to be stored at the memory subsystem and can request retrieval of data from the memory subsystem.

[0015] A memory component in a memory subsystem may contain memory cells, which may contain one or more memory pages (also referred to herein as “pages”) for storing one or more bits of binary data corresponding to data received from a host system. One or more memory cells of the memory component may be grouped together to form data blocks. One or more data blocks may be grouped together to form planes of the memory component to allow concurrent operations on each plane. Memory cells may degrade as data is written to them for storage. Therefore, each memory cell of the memory component can handle a finite number of write operations performed before the memory cell can no longer reliably store data. Data stored in the memory cells of the memory component can be read from the memory component and transferred to the host system. When data is read from a memory cell of the memory component, nearby or adjacent memory cells may experience an event known as read interference. Read interference is the result of continuous reads from one memory cell without interventional erase operations, causing other nearby memory cells to change over time (e.g., become programmed). If too many read operations are performed on a memory cell, data stored in adjacent memory cells may become corrupted or incorrectly stored. This can lead to a higher error rate in the data stored at the memory cell. This can increase the use of error detection and correction operations (e.g., error control operations) for subsequent operations performed on the memory cell (e.g., reads and / or writes). Increased use of error control operations can degrade the performance of the conventional memory subsystem. Furthermore, as the error rate of a memory cell or data block continues to increase, it may even exceed the error correction capabilities of the memory subsystem, resulting in irreparable data loss. Moreover, because more resources of the memory subsystem are used for error control operations, fewer resources are available for performing other read or write operations.

[0016] The error rate associated with the data stored at the data block can increase due to read interference. Therefore, after performing a threshold number of read operations on the data block, the memory subsystem can perform a data integrity check (also referred to herein as a "scan") to verify that the data stored at the data block does not contain any errors. During the data integrity check, one or more reliability statistics are determined for the data stored at the data block. One example of a reliability statistic is the raw bit error rate (RBER). RBER corresponds to the number of bit errors encountered per unit time by the data stored at the data block.

[0017] Conventionally, if the reliability statistics of a data block exceed a threshold indicating a high error rate associated with the data stored at the data block, at least in part attributable to read interference, the data stored at the data block is relocated to a new data block in the memory subsystem (also referred to herein as "folding"). Folding data stored at the data block to other data blocks may involve writing data to other data blocks to refresh the data stored in the memory subsystem. This counteracts the effects of read interference associated with the data and erases the data at the data block. However, as previously discussed, read interference can affect memory cells adjacent to the memory cell being read. Therefore, if a particular memory cell is read more frequently, read interference can cause uneven stress on the memory cells of the data block. For example, memory cells adjacent to frequently read memory cells in a data block may have a high error rate, while memory cells not adjacent to said memory cells may have a lower error rate because read interference has a smaller impact on these memory cells.

[0018] Conventional memory subsystems perform data integrity checks using single-plane scan operations at the block level. Because the scan operation is performed at the block level, the memory subsystem monitors the number of read operations performed on a specific data block and performs a single-plane scan operation when the read count (i.e., the number of read operations) meets or exceeds a specific read threshold. A single-plane scan is limited to reading data from a data block on only one plane of the memory component. Scanning a block takes a certain amount of time (e.g., 100 microseconds), and transferring the data to the controller may take a certain amount of transfer time (e.g., 10 microseconds). If another data block on the same plane or another plane of the memory component has the same read count that meets or exceeds the read threshold, the memory subsystem initiates a separate single-plane scan operation after the previous scan operation has completed. Performing individual scans in this manner can result in the memory subsystem performing excessive memory management operations. This can degrade the performance of the memory subsystem and increase its power consumption. System bandwidth and other resources may also be occupied for extended periods, preventing those resources from being used for other functionalities.

[0019] This disclosure addresses the above and other drawbacks by incorporating a memory subsystem that utilizes read interference scan merging across multiple planes of the memory component to minimize system bandwidth penalties within the memory subsystem. In one embodiment, when the memory subsystem determines that the read count of a memory block on one plane of the memory component reaches a first threshold (i.e., indicating that a scan or other integrity check should be performed), the memory subsystem determines whether any corresponding blocks in other planes of the memory component (e.g., those blocks in stripes across the planes of the memory component) have a corresponding read count that is about to exceed the first threshold. These other blocks may not have a count value reaching the first threshold and are therefore generally not eligible for a scan operation, but may be close enough to the first threshold that the block's count value meets or exceeds a second threshold that is approximately 10% to 20% smaller than the first threshold. These other blocks may rapidly reach the first threshold, thereby triggering their own separate corresponding scan operation. In one embodiment, the memory subsystem may perform multi-plane scan operations on data blocks across multiple or even all planes of the memory component, instead of waiting to perform separate scan operations. When performing a multi-plane scan, the scan time and transfer time are not significantly increased compared to performing a single-plane scan, and time and resources are greatly saved compared to performing multiple single-plane scans sequentially. For example, performing a multi-plane scan of four planes of a memory component and scanning blocks takes a certain amount of time (e.g., 110 microseconds), and transferring data to the controller may take a certain amount of transfer time (e.g., 10 microseconds per plane). Therefore, the total time for a multi-plane scan of all four planes can be approximately 150 microseconds, which is significantly less than the time to perform even two individual single-plane scans (e.g., 110 microseconds per scan). Therefore, when performing read interference scans, the memory controller is occupied less time, allowing the controller more time to handle other data access operations of the memory component.

[0020] Figure 1 This description describes an example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as memory components 112A to 112N. Memory components 112A to 112N may be volatile memory components, non-volatile memory components, or combinations of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. Generally, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to and read data from the memory subsystem 110.

[0021] Host system 120 may be a computing device, such as a desktop computer, notebook computer, network server, mobile device, or such computing device including memory and processing. Host system 120 may include or be coupled to memory subsystem 110, such that host system 120 can read data from or write data to memory subsystem 110. Host system 120 may be coupled to memory subsystem 110 via a physical host interface. As used herein, “coupled to” generally refers to a connection between components, which may be an indirect or direct communication connection (e.g., without intermediate components), whether wired or wireless, including connections such as electrical, optical, and magnetic connections. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the NVM High Speed ​​(NVMe) interface to access the memory components 112A to 112N. The physical host interface provides an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0022] Memory components 112A to 112N may comprise any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND flash memory. Each of memory components 112A to 112N may comprise one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC) or four-level cells (QLC)). In some embodiments, a particular memory component may comprise both SLC and MLC portions of memory cells. Each memory cell may store one or more data bits (e.g., data blocks) used by the host system 120. While non-volatile memory components such as NAND flash memory have been described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase-change memory (PCM), magnetic random access memory (MRAM), NOR flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in bulk resistance by combining with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, cross-point non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without pre-erasing them. Additionally, the memory cells of memory components 112A to 112N can be grouped into memory pages or data blocks, which can refer to cells of a memory component used for storing data. Data blocks can be further divided into one or more planes on each of the memory components 112A to 112N, wherein operations can be performed on each of the planes simultaneously. Corresponding data blocks from different planes can be associated with each other in the form of stripes spanning multiple planes.

[0023] Memory system controller 115 (hereinafter referred to as the "controller") can communicate with memory components 112A to 112N to perform operations, such as reading, writing, or erasing data at memory components 112A to 112N, and other such operations. Controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. Controller 115 may be a microcontroller, application-specific logic circuitry (e.g., field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), etc.), or other suitable processor. Controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of memory subsystem 110 (including handling communication between memory subsystem 110 and host system 120). In some embodiments, local memory 119 may include memory registers that store memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including controller 115, but in another embodiment of the present disclosure, memory subsystem 110 may not include controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0024] Generally, controller 115 can receive commands or operations from host system 120 and can translate these commands or operations into instructions or appropriate commands to enable desired access to memory components 112A to 112N. Controller 115 may handle other operations such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with memory components 112A to 112N. Controller 115 may further include host interface circuitry for communication with host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory components 112A to 112N, and translate responses associated with memory components 112A to 112N into information for host system 120.

[0025] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the controller 115 and decode the addresses to access memory components 112A to 112N.

[0026] The memory subsystem 110 includes a scan determination component 113 for determining when to perform a scan or other data integrity check on data blocks of memory components 112A to 112N. In one embodiment, the scan determination component 113 determines that a first read count of a first data block on a first plane of memory component 112A exceeds a first read threshold. The scan determination component 113 further determines whether a second read count of a second data block on a second plane of memory component 112A exceeds a second read threshold, wherein the second block is associated with the first block (e.g., as part of a block stripe or superblock spanning multiple planes), and wherein the second read threshold is less than the first read threshold (e.g., 10% to 20% smaller). In response to the second read count exceeding the second read threshold, the scan determination component 113 may perform a multi-plane scan to determine, in parallel, a first error rate of the first data block and a second error rate of the second data block. Depending on the embodiment, as part of the multi-plane scan operation, the scan determination component 113 may determine the error rate of data blocks on a subset or all planes of memory component 112A, even if all those data blocks do not have a read count exceeding the first read threshold. After determining the corresponding error rates, the scan determination component 113 can determine whether any of the error rates exceeds an error threshold, and can relocate the data from those data blocks and reset the read counts of those data blocks. Further details regarding the operation of the scan determination component 113 are described below.

[0027] Figure 2A and 2B A diagram illustrating read interference scan merging across multiple planes of a memory component according to some embodiments of the present disclosure. Figure 2AFigure 200 illustrates read count values ​​205 for a set of associated data blocks spanning several planes across one of memory components 112A to 112N (e.g., memory component 112A). In one embodiment, an associated data block is part of a strip of data blocks spanning multiple planes of memory component 112A. This strip may also be referred to as a superblock. In the illustrated embodiment, memory component 112A has four separate planes P0, P1, P2, and P3. As described above, each plane is a set of data blocks from memory component 112A, which are separated to allow simultaneous operation on each plane. In other embodiments, the memory component may contain a different number of planes, such as two planes, six planes, eight planes, etc. In Figure 200, read count values ​​205 are plotted to illustrate the relative read count of a block on each of planes P0, P1, P2, and P3. For example, value P0 A This describes the specific read count of the data block on plane P0, value P1. A This describes the specific read count of the data block on plane P1, value P2. A This describes the specific read count of the data block on plane P2, and the value P3. A This describes a specific read count for data blocks on plane P3, where each of these blocks is part of a stripe or superblock. In one embodiment, controller 115 maintains an individual read count value for each data block on each of planes P0, P1, P2, and P3 of memory component 112A. For example, controller 115 may include a counter corresponding to each data block, which increments each time a read operation is performed on the corresponding data block. Thus, read count value 205 indicates the number of times each corresponding data block has been read since a previous scan operation was performed on the data block, at which point the counter is reset to its initial value (e.g., 0).

[0028] In one embodiment, the scan determination component 113 monitors the read counts of each block on each of the planes P0, P1, P2, and P3 of the memory component 112A. The scan determination component 113 can compare those read counts to a first threshold criterion (i.e., a first read threshold 210). The first read threshold 210 can represent the number of read operations performed on a given memory block before a scan or other data integrity check should be performed. The number of read operations on a data block is an indicator of the potential increase in the error rate of the data block, and therefore, after a certain number of read operations, the error rate can be determined by performing a scan operation. In one embodiment, the first read threshold 210 is a configurable number that can be determined based on the physical characteristics of the underlying memory component, customer requirements, etc. The first read threshold 210 can be set to an amount by which the expected error rate after a certain number of read operations is approaching but still below the error correction capability of the memory component. For ease of explanation, the first read threshold 210 can be set to one million (1M) reads, but in practice, any other value can be used. Figure 2A In chart 200, value P1 A If the first read threshold 210 is exceeded, this indicates that the corresponding first data block on plane P1 has a read count value exceeding the first read threshold 210.

[0029] After determining that at least one read count exceeds a first read threshold 210, the scan determination component 113 may determine the read counts of other data blocks associated with the first data block on plane P1. These other data blocks may be part of the same stripe of a superblock. The scan determination component 113 may compare those read counts with both the first read threshold 210 and a second threshold criterion (e.g., a second read threshold 220). The second read threshold 220 may represent the number of read operations on a given memory block that itself does not trigger a scan but indicates that the number of read operations is approaching the level. In one embodiment, the second read threshold 220 is a configurable number that may, for example, be 10% to 20% smaller than the first read threshold 210. The difference between the first read threshold 210 and the second read threshold 220 may be referred to as an overkill window 230. In other embodiments, the overkill window may represent 5%, 25%, 30%, 50%, or some other amount of the first read threshold 210. For ease of explanation, the second read threshold 220 can be set to 900,000 (900k), but in practice any other value can be used. Figure 2A In chart 200, the value P0 A P2 A Or P3 ANone of them meet or exceed the first read threshold 210 or the second read threshold 220. Therefore, the scan determination component 113 may perform a single-plane scan to determine the first error rate of the data blocks on plane P1. In other embodiments, the scan determination component 113 may instead perform a multi-plane scan to determine the error rate of the data blocks in the current stripe on two or more planes P0, P1, P2, and P3.

[0030] Figure 2B Figure 250 illustrates read count values ​​255 for the same set of associated data blocks spanning planes P0, P1, P2, and P3 in memory component 112A. Read count values ​​255 can indicate read counts at later points in time, such that one or more of the read count values ​​255 may have been relative to... Figure 2A The read count value 205 shown in Figure 200 increases. For the embodiment illustrated in Figure 250, the value P1... B The first reading threshold 210 has been exceeded. Scan determination component 113 can further determine the value P0. B and P2 B The value is less than the first reading threshold 210 but meets or exceeds the second reading threshold 220 (i.e., the value P0). B and P2 B Within the transition window 230, this indicates that corresponding data blocks on planes P0 and P2 have read count values ​​exceeding the second read threshold 220. In response, the scan determination component 113 may perform a multi-plane scan to determine the error rate of data blocks in stripes in at least planes P0, P1, and P2. In one embodiment, the multi-plane scan includes data blocks in stripes whose corresponding read count values ​​255 meet or exceed the second read threshold 220 (even if those read count values ​​do not meet or exceed the first read threshold 210). In another embodiment, the multi-plane scan includes data blocks in each of planes P0, P1, P2, and P3 on memory component 112A, even if the read count value P3... B It may not even meet the second read threshold 220. In one embodiment, read count values ​​205 and 255, the first read threshold 210 and the second read threshold 220, and the error threshold are all stored in the local memory 119 of the controller 115, where these values ​​are accessible by the scan determination component 113.

[0031] As part of a multi-plane scan, all blocks across a strip spanning planes P0, P1, P2, and P3 can be scanned in parallel. The multi-plane scan itself may take a certain amount of time (e.g., 110 microseconds), and transmitting data to the controller may take a certain amount of transmission time (e.g., 10 microseconds per plane). Therefore, the total time for a multi-plane scan of all four planes P0, P1, P2, and P3 can be approximately 150 microseconds, which is significantly less than the time required to perform even two individual single-plane scans (e.g., 110 microseconds per scan).

[0032] Figure 3 This is a flowchart illustrating an example method for merging read interfering scans in a multi-plane scan performed simultaneously across multiple planes of a memory component, according to some embodiments of this disclosure. Method 300 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The scanning and determination component 113 is executed. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0033] At operation 310, the processing device determines the first read count P1 of the first data block on the first plane P1 of the memory component 112A. A Or P1 B Does it meet the first threshold criterion (i.e., meet or exceed the first read threshold 210)? First read count P1 A Or P1 B This represents the number of times the first data block on plane P1 has been read since a previous scan operation or data integrity check was performed on the first data block; at this time, the first read count P1 is... A Or P1 B The read threshold 210 may represent the number of read operations performed on a given memory block before a scan or other data integrity check should be performed. In one embodiment, the scan determination component 113 sets the first read count P1. A Or P1 B The first read count P1 is determined by comparing it with the first read threshold 210. A Or P1 B Does it meet or exceed the first read threshold 210? If the first read count P1... A Or P1B If the first read threshold 210 is not met or exceeds, the processing device returns to operation 310 and continues to monitor the read count value 205 or 255 of the data block on the memory component 112A. In another embodiment, the first threshold criterion includes a first read count P1. A Or P1 B If the first read count P1 is less than the first read threshold 210, then... A Or P1 B If the first threshold criterion is not met, the processing device continues to operate 320.

[0034] If the first read count P1 A Or P1 B If the first read threshold 210 is met or exceeded, then at operation 320, the processing device determines the second read count P2 of the second data block on the second plane P2 of the memory component 112A. A or P2 B Does it meet the second threshold criterion (i.e., meet or exceed the second read threshold 220)? Second read count P2 A or P2 B This indicates the number of times the second data block on plane P2 has been read since a previous scan operation or data integrity check was performed on the second data block; at this time, the second read count P2 is... A or P2 B The system has been reset. The second read threshold 220 can represent the number of read operations on a given memory block that itself does not trigger a scan but indicates that the number of read operations is approaching the level. In one embodiment, the scan determination component 113 sets the second read count P2... A or P2 B The second read count P2 is determined by comparing it with the second read threshold 220. A or P2 B Whether the second read threshold 220 is met or exceeded. In another embodiment, the second threshold criterion includes a first read count P1. A Or P1 B If the first read count P1 is less than the second read threshold 220, then... A Or P1 B If the second threshold criterion is not met, the processing device continues to operate 330.

[0035] If the second read count P2 BIf the read count value 255 meets or exceeds the second read threshold 220, then at operation 330, the processing device performs a multi-plane scan on at least the associated data blocks on planes P1 and P2 to determine, in parallel, the first error rate of the first data block and the second error rate of the second data block. In one embodiment, the multi-plane scan includes data blocks in stripes whose corresponding read count values ​​255 meet or exceed the second read threshold 220 (even if those read count values ​​do not meet or exceed the first read threshold 210). In another embodiment, the multi-plane scan includes data blocks in each of planes P0, P1, P2, and P3 on the memory component 112A, even if the read count value P3... B It may not even meet the second read threshold 220. In one embodiment, during a scan, the scan determination component 113 reads a raw codeword (i.e., a sequence of a fixed number of bits) from each plane of the memory component 112A. The scan determination component 113 may apply the codeword to an error correction code (ECC) decoder to produce a decoded codeword and compare the decoded codeword with the raw codeword. The scan determination component 113 may count the number of flipped bits between the decoded codeword and the raw codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the raw bit error rate (RBER). The scan determination component 113 may repeat this process for additional codewords until the entire memory component 112A has been scanned.

[0036] At operation 340, the processing device determines whether a first error rate or a second error rate meets an error threshold criterion (i.e., meets or exceeds an error threshold). The error rate associated with the data stored at the data block may increase due to read interference. Therefore, after performing a threshold number of read operations on the data block, the memory subsystem 110 may perform a scan or other data integrity check to verify that the data stored at the data block does not contain any errors, or that the number of errors is appropriately small. During the scan, the scan determination component 113 identifies one or more reliability statistics, such as the raw bit error rate (RBER), which represents the number of bit errors experienced per unit time by the data stored at the data block. In one embodiment, the scan determination component 113 compares the error rate with an error threshold representing the error correction capability of the memory component 112A. If neither the first error rate nor the second error rate meets or exceeds the error threshold, the processing device returns to operation 310 and continues to monitor the read count value 205 or 255 of the data block on the memory component 112A. In another embodiment, the error threshold criterion includes a first error rate or a second error rate that is less than a first error threshold, such that if the first error rate or the second error rate does not meet the error threshold criterion, then the processing device continues to operate 350.

[0037] If the first error rate or the second error rate (or the error rate of the data block on any of the scanned planes P1, P2, P3, or P4) meets or exceeds the error threshold, then at operation 350, the processing device relocates the data stored in the corresponding data block in the first data block or the second data block to another data block, and sets the first read count P1B or the second read count P2B to the correct value. B A corresponding read count reset is performed. In one embodiment, the scan determination component 113 reads data stored in a corresponding data block (i.e., a data block whose error rate meets or exceeds an error threshold) and writes the data to another data block. Once the data has been written to the other data block, the data stored in the initial data block is erased, and the initial data block can be used for programming with the new data. Depending on the embodiment, the data may be relocated to another data block on the same plane of the same memory component, relocated to another plane on the same memory component, or relocated to a different memory component of the memory subsystem 110.

[0038] If at operation 320, the second read count P2 A If the second read threshold 220 is not met or exceeds, then at operation 360, the processing device performs a single-plane scan on the first data block on plane P1 to determine the first error rate of the first data block. This single-plane scan works in a similar manner to the multi-plane scan described above, except that in the single-plane scan, only the first data block on plane P1 is scanned.

[0039] Figure 4 This is a flowchart illustrating an example method for merging read interfering scans in a multi-plane scan performed simultaneously across multiple planes of a memory component, according to some embodiments of this disclosure. Method 400 may be executed by processing logic, which may include hardware (e.g., processing means, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on a processing means), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The scanning and determination component 113 is executed. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0040] At operation 410, the processing device identifies a first data block on a first plane P1 of a plurality of planes P1, P2, P3, and P4 of the memory assembly 112A, wherein the first read count of the first data block is P1. BThe first threshold criterion is met (i.e., the first read threshold 210 is met or exceeded). First read count P1 B This represents the number of times the first data block on plane P1 has been read since a previous scan operation or data integrity check was performed on the first data block; at this time, the first read count P1 is... B The read threshold 210 may represent the number of read operations performed on a given memory block before a scan or other data integrity check should be performed. In one embodiment, the scan determination component 113 sets the first read count P1. B The first read count P1 is determined by comparing it with the first read threshold 210. B Does it meet or exceed the first reading threshold of 210?

[0041] At operation 420, the processing device identifies a second data block on the second plane P2 of the plurality of planes P1, P2, P3, and P4 of the memory assembly 112A, wherein the second read count of the second data block is P2. B The second threshold criterion is met (i.e., the second read threshold 220 is met or exceeded) but the first threshold criterion is not met (i.e., the first read threshold 210 is not met or exceeded). Second read count P2 B This indicates the number of times the second data block on plane P2 has been read since a previous scan operation or data integrity check was performed on the second data block; at this time, the second read count P2 is... B The system has been reset. The second read threshold 220 can represent the number of read operations on a given memory block that itself does not trigger a scan but indicates that the number of read operations is approaching the level. In one embodiment, the scan determination component 113 sets the second read count P2... B The second read count P2 is determined by comparing it with the second read threshold 220. B Does it meet or exceed the second reading threshold of 220?

[0042] At operation 430, as part of a multi-plane scan operation, the processing device optionally jointly reads data from a first data block and a second data block to determine whether the error rate of the first data block or the second data block meets or exceeds the error correction capability of the memory component 112A. In one embodiment, the multi-plane scan includes a corresponding read count value P1. B and P2 B Meets or exceeds the second read threshold 220 (even if all those read count values ​​(e.g., P2) B Data blocks in stripes that do not conform to or exceed the first read threshold 210).

[0043] At operation 440, as part of the multi-plane scan operation, the processing device optionally reads data from a third data block on the third plane P3 of the memory component 112A, together with data from the first data block and the second data block, wherein the third read count P3 of the third data block... B The data does not meet or exceeds the second read threshold 220. In one embodiment, the multi-plane scan includes data blocks in stripes whose corresponding read count values ​​255 meet or exceed the second read threshold 220, and read count values ​​P3. B At least one data block that does not meet the second read threshold 220.

[0044] At operation 450, as part of a multi-plane scan operation, the processing device optionally reads data from data blocks on each of the plurality of planes P1, P2, P3, and P4 to determine whether the error rate of any of the blocks in the stripe meets an error threshold criterion (i.e., meets or exceeds the error correction capability of memory component 112A). In one embodiment, the multi-plane scan includes data blocks on each of the planes P0, P1, P2, and P3 on memory component 112A, even when reading the count value P3. B For example, it may not even meet the second read threshold of 220.

[0045] Figure 5 An example machine illustrating computer system 500 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (The operation of the scanning determination component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0046] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is described, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0047] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0048] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communication via network 520.

[0049] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) on which one or more sets of instructions 526 or software embodying any one or more of the methods or functions described herein are stored. The instructions 526 may also reside wholly or at least partially within main memory 504 and / or processing device 502 during execution by computer system 500, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0050] In one embodiment, instruction 526 includes instructions for implementing the corresponding Figure 1The scanning determines the functional instructions of component 113. Although machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0051] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have already been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Here, and generally, an algorithm is conceived as a self-consistent sequence of operations that produce a desired result. An operation is an operation that requires physical manipulation of a physical quantity. Usually (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been found that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0052] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0053] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magnetic optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0054] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as illustrated in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0055] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0056] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory system comprising: Memory devices; Scan to identify components; as well as A processing device operatively coupled to the memory device to perform the following operations: By means of a scanning determination component, it is determined that a first metric of a first memory cell on a first plane of the memory device satisfies a first threshold criterion; The scanning determination component determines whether a second metric of a second memory cell on a second plane of the memory device satisfies a second threshold criterion and does not satisfy the first threshold criterion. as well as In response to the second metric satisfying the second threshold criterion but not the first threshold criterion, the scanning determination component performs a multi-plane data integrity operation to determine the first reliability statistics of the first memory cell and the second reliability statistics of the second memory cell in parallel.

2. The memory system of claim 1, wherein, in order to perform the multiplane data integrity operation, the processing device scans a third memory cell on a third plane of the memory device in parallel with the first memory cell and the second memory cell, wherein the third memory cell is associated with the first memory cell and the second memory cell, and wherein a third metric of the third memory cell does not satisfy the second threshold criterion.

3. The memory system of claim 2, wherein the first memory cell, the second memory cell, and the third memory cell are arranged in a strip spanning a plurality of planes of the memory device.

4. The memory system of claim 1, wherein, in order to perform the multi-plane data integrity operation, the processing device performs the following operations: Determine whether the first reliability statistics meet the error threshold criterion; and In response to the first reliability statistic satisfying the error threshold criterion: Relocate the data stored in the first memory cell to another memory cell on the first plane; and The first metric of the first memory cell is reset to its initial value.

5. The memory system of claim 1, wherein, in order to perform the multi-plane data integrity operation, the processing means scans the corresponding memory cells on each plane of the memory device.

6. The memory system according to claim 1, further comprising: In response to the second metric not meeting the second threshold criterion, a single-plane data integrity operation is performed to determine the first reliability statistics of the first memory cell.

7. The memory system of claim 1, wherein the second threshold criterion is in the range of 10% to 20% smaller than the first threshold criterion.

8. A method of operating a memory device, comprising: A first memory cell on a first plane of a plurality of planes of the memory device is identified via a processing device coupled to the memory device, wherein a first metric of the first memory cell satisfies a first threshold criterion; The processing device identifies a second memory cell on a second plane among the plurality of planes, wherein a second metric of the second memory cell satisfies a second threshold criterion and does not satisfy the first threshold criterion; as well as As part of the multiplane data integrity operation, the processing device reads data from the first memory cell and the second memory cell to determine whether the reliability statistics of the first memory cell or the second memory cell meet the error correction capability of the memory device.

9. The method of claim 8, further comprising: As part of the multiplane data integrity operation, data from a third memory cell on a third plane of the memory device is read together with data from the first memory cell and the second memory cell, wherein a third metric of the third memory cell does not satisfy the second threshold criterion.

10. The method of claim 9, wherein the first memory cell, the second memory cell, and the third memory cell are arranged in a strip spanning the plurality of planes of the memory device.

11. The method of claim 8, further comprising: In response to the reliability statistics satisfying the error correction capability of the memory device, data stored in a corresponding memory cell in the first memory cell or the second memory cell is relocated to another memory cell on the memory device, and the first metric or the second metric is reset to its initial value.

12. The method of claim 8, further comprising: As part of the multi-plane data integrity operation, data is read from the corresponding memory cell on each of the plurality of planes of the memory device.

13. The method of claim 8, further comprising: As part of the single-plane data integrity operation, data is read from the first memory cell in response to the second metric not meeting the second threshold criterion.

14. The method of claim 8, wherein the first metric indicates the number of times the first memory cell has been read since a previous data integrity operation was performed on the first memory cell.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to perform the following operations: By scanning and determining the component, it is determined that a first metric of a first memory cell on a first plane of the memory device satisfies a first threshold criterion; The scanning determination component determines whether a second metric of a second memory cell on a second plane of the memory device satisfies a second threshold criterion and does not satisfy the first threshold criterion. as well as In response to the second metric satisfying the second threshold criterion but not the first threshold criterion, the scanning determination component performs a multi-plane data integrity operation to determine the first reliability statistics of the first memory cell and the second reliability statistics of the second memory cell in parallel.

16. The non-transitory computer-readable storage medium of claim 15, wherein, in order to perform the multi-plane data integrity operation, the processing means scans a third memory cell on a third plane of the memory means in parallel with the first memory cell and the second memory cell, wherein the third memory cell is associated with the first memory cell and the second memory cell, and wherein a third metric of the third memory cell does not satisfy the second threshold criterion.

17. The non-transitory computer-readable storage medium of claim 16, wherein the first memory cell, the second memory cell, and the third memory cell are arranged in a strip spanning a plurality of planes of the memory device.

18. The non-transitory computer-readable storage medium of claim 15, wherein, in order to perform the multi-plane data integrity operation, the processing apparatus performs the following operations: Determine whether the first reliability statistics meet the error threshold criterion; and In response to the first reliability statistic satisfying the error threshold criterion: Relocate the data stored in the first memory cell to another memory cell on the first plane; and The first metric of the first memory cell is reset to its initial value.

19. The non-transitory computer-readable storage medium of claim 15, wherein, in order to perform the multi-plane data integrity operation, the processing means scans the corresponding memory cells on each plane of the memory device.

20. The non-transitory computer-readable storage medium of claim 15, wherein the instructions further cause the processing apparatus to perform the following operations: In response to the second metric not meeting the second threshold criterion, a single-plane data integrity operation is performed to determine the first reliability statistics of the first memory cell.

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