A frame memory scheduling system based on variable refresh rate

Abstract

This invention belongs to the field of head-up display character video image processing technology, specifically involving a frame buffer scheduling system based on a variable refresh rate. It includes an input video timing detection unit, an output video timing generation unit, a read-out frame scheduling unit, a video buffer unit, a write-out frame buffer scheduling unit, and a storage read-write control unit. The write-out frame buffer scheduling unit employs a three-frame buffer round-robin write algorithm, which writes video to the storage read-write control unit and inputs the generated current write-out video frame buffer number information to the read-out frame scheduling unit. The read-out frame scheduling unit calculates the frame buffer number to be read based on the received output video timing information and the current write-out video frame buffer number information. In summary, this invention has the advantage of dynamically matching and binding the output digital timing with the input analog timing through dynamic matching of the output refresh rate, significantly reducing video output latency.

Description

Technical Field

[0001] This invention belongs to the field of head-up display character video image processing technology, specifically relating to a frame buffer scheduling system based on variable refresh rate. Background Technology

[0002] Older head-up displays (HUDs) used CRT image sources. With technological advancements, CRTs were gradually replaced by digital image sources and faced discontinuation. Simultaneously, to achieve better display effects, converting CRT HUDs to digital HUDs became imperative. However, the conversion from CRT to digital inevitably increased the sampling and digital processing stages due to the change in scanning methods. In the original CRT scheme, the analog deflection and glow signals were amplified by the analog response circuit and directly drove the CRT for scanning and display. In the digital scheme, the deflection scanning method was transformed into the row and column scanning method of the digital image source, causing new delays in video information conversion. These changes in scanning methods, digital signal processing, and display all significantly increased display latency, affecting the usability of HUDs and making it impossible to address with existing technologies.

[0003] Therefore, there is an urgent need for a frame buffer scheduling system based on variable refresh rate, which can address the problem of digital timing mismatch between the existing front-end input signals and output signals, implement a variable refresh rate solution, and achieve the requirement of controlling the output delay within one frame (20ms). Summary of the Invention

[0004] In view of this, the present invention proposes a frame buffer scheduling system based on variable refresh rate. By dynamically matching the output refresh rate, the output digital timing sequence is dynamically matched and bound with the input analog timing sequence, which greatly reduces video output latency and has high value.

[0005] To achieve the above-mentioned technical objectives, the specific technical solution adopted by the present invention is as follows:

[0006] A frame buffer scheduling system based on variable refresh rate includes an input video timing detection unit, an output video timing generation unit, a read-out frame scheduling unit, a video buffer unit, a write-out frame buffer scheduling unit, and a storage read-write control unit. The video buffer unit is connected to the input video signal, performs a first-level buffering of the input video signal, and then inputs it into the write-out frame buffer scheduling unit. The storage read-write control unit is connected to both the write-out frame buffer scheduling unit and the read-out frame scheduling unit via logic control signals. The write-out frame buffer scheduling unit employs a three-frame buffer round-robin write algorithm, which virtually instantiates and numbers three frame buffer regions within the storage read-write control unit. The three-frame buffer round-robin writing algorithm, with the sequence 1-2-3-1, cyclically writes the video to the storage read / write control unit. Simultaneously, it inputs the generated current video frame buffer number information to the read-out frame scheduling unit. The output video timing generation unit receives the video signal processed by the input video timing detection unit, generates the corresponding output video timing information, and inputs it to the read-out frame scheduling unit. The read-out frame scheduling unit calculates the frame buffer number to be read based on the received output video timing information and the current video frame buffer number information, then retrieves the corresponding video information from the storage read / write control unit and outputs it to the outside of the system through the read-out frame scheduling unit.

[0007] Furthermore, the output of the write frame buffer scheduling unit is connected to the storage read / write control unit via a bus to schedule the writing of input video to the frame buffer.

[0008] Furthermore, the input video timing detection unit is connected to the input video signal and is used to obtain in real time whether the input video has completed the writing of a frame.

[0009] Furthermore, the input terminal of the readout frame scheduling unit is connected to the status output terminals of the write frame buffer scheduling unit and the output video timing generation unit via the instruction signal line, in order to obtain the information required for readout frame scheduling.

[0010] Furthermore, the input of the read frame scheduling unit is connected to the storage read / write control unit via a bus to control the reading of buffered data for a specified frame number.

[0011] By adopting the above technical solution, the present invention can also bring the following beneficial effects:

[0012] This invention constructs a frame buffer scheduler on an FPGA. This frame buffer scheduler employs fully parallel and pipelined computing technologies and a reusable modular design method. It processes video through its internal input video timing detection unit, output video timing generation unit, read-out frame scheduling unit, video buffer unit, write-to-frame buffer scheduling unit, and storage read-write control unit. The output video timing generation unit dynamically adjusts based on the real-time detection results of the input video timing. The read-out frame scheduling unit outputs video based on the status information of the write-to-frame buffer scheduling and output video timing generation units. This not only avoids frame buffer read-write conflicts but also further shortens the overlay latency, offering the advantages of preventing overlay screen tearing and achieving zero latency in output video. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the system structure in a specific embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram illustrating the technical implementation principle in a specific embodiment of the present invention. Detailed Implementation

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0018] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this invention, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0019] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0021] In one embodiment of the present invention, a frame buffer scheduling system based on a variable refresh rate is proposed, such as... Figure 1 and Figure 2 As shown, it includes a video buffer unit, a write frame buffer scheduling unit, a storage read / write control unit, an input video timing detection unit, an output video timing generation unit, and a read frame scheduling unit. Through dynamic matching of the output refresh rate, the output digital timing is dynamically matched and bound with the input analog timing. This low-latency frame switching logic architecture is implemented based on an FPGA hardware platform.

[0022] The input terminal of the video buffer unit is connected to the input video signal, and the output terminal of the video buffer unit is connected to the input terminal of the write frame buffer scheduling unit, which is used to realize the first-level buffer of external input video data.

[0023] The output of the write frame buffer scheduling unit is connected to the storage read / write control unit via a bus to schedule the writing of input video to the frame buffer.

[0024] The scheduling algorithm used by the frame buffer scheduling unit is the three-frame buffer round-robin writing algorithm. The three-frame buffer round-robin writing algorithm virtually instantiates three frame buffer regions in external storage and numbers them 1, 2, and 3. The three-frame buffer round-robin writing algorithm writes the video to the external storage in a cyclical order of 1-2-3-1.

[0025] The input terminal of the readout frame scheduling unit is connected to the status output terminal of the write frame buffer scheduling unit and the output video timing generation unit via the instruction signal line, in order to obtain the information required for readout frame scheduling.

[0026] The input terminal of the input video timing detection unit is connected to the input video signal and is used to obtain in real time whether the input video has completed the writing of a frame.

[0027] The read frame scheduling unit calculates the frame buffer number that needs to be read based on the timing of the output video and the current written video frame buffer number information.

[0028] The input of the read frame scheduling unit is also connected to the storage read / write control unit via a bus to control the reading of buffered data for a specified frame number.

[0029] In this embodiment, the video signal is first buffered and then input into the write frame buffer scheduling unit. Within the write frame buffer scheduling unit, it is processed by a three-frame buffer round-robin writing algorithm and then written to the storage read / write control unit. The write frame buffer scheduling unit then generates the current written video frame buffer number information and inputs it into the read frame scheduling unit, completing the transmission of one video signal from the buffer. Simultaneously, the input video timing detection unit is connected to the input video signal to obtain in real-time whether the input video has completed writing a frame. The processed video signal is then input to the output video timing generation unit, which generates the corresponding output video timing information and inputs it into the read frame scheduling unit. The read frame scheduling unit calculates the frame buffer number to be read based on the received output video timing information and the current written video frame buffer number information. Then, it retrieves the corresponding video information from the storage read / write control unit and outputs it to the outside of the system through the read frame scheduling unit. In summary, this invention has the advantage of dynamically matching and binding the output digital timing with the input analog timing through dynamic matching of the output refresh rate, significantly reducing video output latency.

[0030] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A frame buffer scheduling system based on variable refresh rate, characterized in that: It includes an input video timing detection unit, an output video timing generation unit, a readout frame scheduling unit, a video buffer unit, a write frame buffer scheduling unit, and a storage read / write control unit, wherein... The video buffer unit is connected to the input video signal, performs a first-level buffer on the input video signal, and then inputs it into the write frame buffer scheduling unit. The storage read / write control unit is connected to the write frame buffer scheduling unit and the read frame scheduling unit via logic control signals. The scheduling algorithm of the write frame buffer scheduling unit adopts a three-frame buffer round-robin writing algorithm. The three-frame buffer round-robin writing algorithm virtually instantiates three frame buffer regions in the storage read / write control unit and numbers them as 1, 2, and 3. The three-frame buffer round-robin writing algorithm writes the video into the storage read / write control unit in the order of 1-2-3-1. At the same time, the generated current written video frame buffer number information is input into the read frame scheduling unit. The output video timing generation unit receives the video signal processed by the input video timing detection unit, then generates the timing information of the corresponding output video, and inputs it into the readout frame scheduling unit. The readout frame scheduling unit calculates the frame buffer number that needs to be read based on the timing information of the received output video and the current written video frame buffer number information, then retrieves the corresponding video information from the storage read / write control unit, and then outputs it to the outside of the system through the outgoing frame scheduling unit; The input video timing detection unit is connected to the input video signal and is used to obtain in real time whether the input video has completed the writing of a frame.

2. The frame buffer scheduling system based on variable refresh rate according to claim 1, characterized in that: The output of the write frame buffer scheduling unit is connected to the storage read / write control unit via a bus, and is used to schedule the input video to be written to the frame buffer.

3. A frame buffer scheduling system based on variable refresh rate according to claim 2, characterized in that: The input terminal of the readout frame scheduling unit is connected to the status output terminals of the write frame buffer scheduling unit and the output video timing generation unit via an instruction signal line, and is used to obtain the information required for readout frame scheduling.

4. A frame buffer scheduling system based on a variable refresh rate according to claim 3, characterized in that: The input terminal of the read frame scheduling unit is connected to the storage read / write control unit via a bus, and is used to control the reading of buffered data for a specified frame number.

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