A digital microfluidic chip
By introducing glass via technology into digital microfluidic chips, multilayer TFT devices are stacked vertically and directly interconnected, solving the problem of insufficient chip pixel density and achieving high-performance, low-cost pixel density improvement and droplet precision enhancement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG ACXEL MICRO & NANO TECH CO LTD
- Filing Date
- 2024-01-10
- Publication Date
- 2026-05-19
AI Technical Summary
Digital microfluidic chips have the disadvantages of large chip size and low pixel density, resulting in fewer pixels integrated on a single digital microfluidic chip, which affects throughput and droplet accuracy.
By introducing glass vias into digital microfluidic chips, multilayer TFT devices can be stacked vertically and directly interconnected through the glass vias, achieving direct interconnection between different layers and improving pixel density.
This improves the pixel density of digital microfluidic chips, increases the number and precision of droplets, while reducing costs and signal transmission losses, and expanding application scenarios.
Smart Images
Figure CN117920365B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of LED imaging technology, and in particular to a three-dimensional integration method for improving the pixel density of digital microfluidic chips using glass vias. Background Technology
[0002] Pixels Per Inch (PPI), also known as pixel density unit, represents the number of pixels per inch. Therefore, a higher PPI value indicates higher precision and resolution. Currently, the field of digital microfluidic chips faces the problem of large chip size and low pixel density, resulting in fewer pixels integrated on a single digital microfluidic chip, thus affecting the overall throughput and droplet accuracy. To address this, a three-dimensional integration technique is developed that stacks multiple layers of TFT devices vertically within the digital microfluidic chip through glass vias, thereby improving pixel density. Summary of the Invention
[0003] In view of this, the embodiments of the present invention aim to provide a way to improve the pixel density of digital microfluidic chips by utilizing glass vias, so as to solve or alleviate the technical problems existing in the prior art, and at least provide a beneficial option.
[0004] The technical solution of this invention is implemented as follows: A digital microfluidic chip, the digital microfluidic chip including a top cover and an electrode layer, and a droplet channel layer disposed between the top cover and the electrode layer. The top cover includes an upper cover, a conductive layer and a first hydrophobic layer disposed sequentially. The electrode layer includes a second hydrophobic layer, a dielectric layer, a driving electrode, a first TFT device layer, a substrate layer and a second TFT device layer. The first hydrophobic layer and the second hydrophobic layer are disposed opposite to each other, and a droplet channel layer is formed between the first hydrophobic layer and the second hydrophobic layer. A glass via penetrates the first TFT device layer, the substrate layer and the second TFT device layer, and directly interconnects the vertically stacked first TFT device layer, second TFT device layer and driving electrode through the glass via.
[0005] The first TFT device layer is generally a functional layer. The TFTs in this functional layer can achieve various functions through different designs. These functional layers serve as detection, switching, or feedback mechanisms, such as pixel heating, voltage detection, photosensitivity detection, and temperature detection. This layer typically uses a-Si TFTs. The first TFT device layer can also serve as a backup driving circuit. Because TFT devices have a limited lifespan, stacking the backup driving circuit with the main driving circuit improves the chip's lifespan without compromising its accuracy.
[0006] The substrate layer typically serves to isolate the first TFT device layer from the second TFT device layer, preventing interference between the electrical signals between the two layers. Various materials can be chosen for the substrate layer, such as transparent glass substrates and plastic substrates.
[0007] The second TFT device layer is typically the device layer where the pixel driving circuit resides, and its main function is to supply power to the driving electrodes. Pixel driving TFTs generally use low-temperature polysilicon TFTs or metal-oxide TFTs.
[0008] The first TFT device layer, the second TFT device layer, and the driving electrode are connected through vertical glass vias. These vias connect the first TFT device layer, the second TFT device layer, and the driving electrode with the shortest possible distance, thereby maximizing the stacking density of the multilayer device in three dimensions, minimizing the interconnections between layers, and minimizing the overall size. This simple and effective method improves the pixel density (PPI) of the digital microfluidic chip, thereby increasing the number and precision of droplet tearing in the digital microfluidic chip.
[0009] The dielectric layer serves to insulate and protect the driving electrode.
[0010] In the application of digital microfluidic chips, the first and second hydrophobic layers can be made of Teflon, which has high crystallinity, tightly aligned molecules, and low porosity.
[0011] In some embodiments, the substrate layer is located between the first TFT device layer and the second TFT device layer.
[0012] In some embodiments, the diameter of the glass through-hole is 5-50 μm.
[0013] In some embodiments, the glass through-hole is filled with a conductive and thermally conductive material.
[0014] In some embodiments, the conductive and thermally conductive material is any one of aluminum, molybdenum, copper, nickel, nickel-manganese alloy, and nickel-chromium alloy.
[0015] In some embodiments, the substrate layer is made of either a transparent glass substrate or a plastic substrate.
[0016] The embodiments of the present invention have the following advantages due to the adoption of the above technical solutions:
[0017] This invention provides an application design for through-hole technology in the field of microfluidics. Glass through-holes connect the upper and lower TFT device layers of the substrate, enabling direct interconnection between different layers of the digital microfluidic chip. This maximizes the stacking density of the digital microfluidic chip in three dimensions, minimizes the interconnections between layers, and minimizes the overall size, thereby increasing the pixel density (PPI) of the digital microfluidic chip and ultimately improving the number and precision of droplet tearing.
[0018] This invention is a technology that can improve the pixel density of digital microfluidic chips. By using through-glass via (TGV) technology, through-holes are made in the substrate of the digital microfluidic chip to connect multiple TFTs. The vertical through-holes can realize direct interconnection between different layers of the digital microfluidic chip, thereby improving the stacking degree of the digital microfluidic chip in three dimensions while saving costs. The pixel density (PPI) is increased without affecting the chip, thereby achieving the goal of increasing the number and accuracy of tearing droplets in the digital microfluidic chip.
[0019] Because glass is an insulator with a dielectric constant only about one-third that of silicon and a loss factor two to three orders of magnitude lower, substrate loss and parasitic effects are significantly reduced, ensuring the integrity of signal transmission between different layers in the vertical direction. Furthermore, glass substrates are readily available, eliminating the need for insulating layer deposition, resulting in a simpler and relatively lower-cost process. This greatly reduces the cost of backplane fabrication. In addition, the high mechanical stability of glass allows for a wider range of applications for digital microfluidic chips using this technology.
[0020] Through-glass via (TW) technology offers a high-performance, low-cost solution for improving the performance and increasing pixel density of digital microfluidic chips. Furthermore, the fabricated backplanes exhibit advantages such as high electrical performance, high reliability, high yield, and low cost.
[0021] The above overview is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the invention will become readily apparent from the accompanying drawings and the following detailed description. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1This is a schematic diagram of a structure in which the TFT layers of a backplane are arranged using the method of the present invention in an embodiment of the present invention;
[0024] Figure 2 This is a schematic diagram of another structure in which the TFT layers of the backplane are arranged using the method of the present invention.
[0025] Figure 3 This is a schematic diagram of the structure of the digital microfluidic chip in an embodiment of the present invention.
[0026] Reference numerals: 1. Top cover; 2. Electrode layer; 3. Droplet channel layer; 4. Top cover; 5. Conductive layer; 6. First hydrophobic layer; 7. Droplet; 8. Second hydrophobic layer; 9. Dielectric layer; 10. Driving electrode; 11. First TFT device layer; 12. Substrate layer; 13. Second TFT device layer; 14. Through hole. Detailed Implementation
[0027] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.
[0028] It is important to note that terms such as "first," "second," "symmetric," and "array" are used only to distinguish between descriptive and positional descriptions and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features specified with terms such as "first" or "symmetric" may explicitly or implicitly include one or more of that feature; similarly, when the quantity of certain features is not limited by words such as "two" or "three," it should be noted that such features also explicitly or implicitly include one or more features.
[0029] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," and "fixation" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral molding; they can refer to a mechanical connection, a direct connection, a welding connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the accompanying drawings and specific circumstances.
[0030] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0031] This invention provides a three-dimensional integration method for improving the pixel density of digital microfluidic chips using glass vias, comprising:
[0032] The multilayer TFT devices in the digital microfluidic chip are stacked vertically through glass vias 14, and the multilayer TFT devices are directly interconnected through glass vias 14; the multilayer TFT devices refer to the first TFT device layer 11 and the second TFT device layer 13.
[0033] Because glass is an insulator with a dielectric constant only about one-third that of silicon and a loss factor two to three orders of magnitude lower, substrate loss and parasitic effects are significantly reduced, ensuring the integrity of signal transmission between different layers in the vertical direction. Furthermore, glass substrates are readily available, eliminating the need for insulating layer deposition, resulting in a simpler and relatively lower-cost process. This greatly reduces the cost of backplane fabrication. In addition, the high mechanical stability of glass allows for a wider range of applications for digital microfluidic chips using this technology.
[0034] Through-glass via (TW) technology offers a high-performance, low-cost solution for improving the performance and increasing pixel density of digital microfluidic chips. Furthermore, the fabricated backplanes exhibit advantages such as high electrical performance, high reliability, high yield, and low cost.
[0035] Specifically: such as Figure 3 As shown, the digital microfluidic chip includes a top cover 1 and an electrode layer 2. Between the top cover 1 and the electrode layer 2 is a droplet channel layer 3. The top cover 1 includes an upper cover 4, a conductive layer 5, and a first hydrophobic layer 6. The electrode layer 2 includes a second hydrophobic layer 8, a dielectric layer 9, a driving electrode 10, a first TFT device layer 11, a substrate layer 12, a second TFT device layer 13, and a glass via 14. A droplet 7 is disposed in the droplet channel layer 3, wherein the glass via passes through the first TFT device layer 11, the substrate layer 12, and the second TFT device layer 13. The digital microfluidic chip stacks multiple TFT devices in the vertical direction to improve the three-dimensional integration of pixel density.
[0036] Among them: the first TFT device layer 11 is a functional layer. The TFTs in the functional layer can realize a variety of functions through different designs. The functional layer plays the role of detection, switching or feedback, such as pixel heating, voltage detection, photosensitive detection, temperature detection. This layer of TFT generally uses a-Si TFT.
[0037] The second TFT device layer 13 is generally the layer where the pixel driving circuit is located. It is mainly used to power the driving electrode. The pixel driving TFT generally uses low temperature polysilicon TFT or metal oxide TFT.
[0038] The substrate layer is located between the first TFT device layer 11 and the second TFT device layer 13. It is used to isolate the two TFT device layers and prevent interference between the electrical signals between the two layers. The substrate layer can be selected from a variety of materials, such as transparent glass substrate and plastic substrate, and is not limited to the two materials mentioned above.
[0039] Specifically, the first TFF device layer 11 can also serve as a backup driving circuit. Since the lifespan of TFT devices is limited, the backup driving circuit is stacked with the main driving circuit, which improves the lifespan of the chip without compromising the accuracy of the digital microfluidic chip.
[0040] The first TFT device layer 11, the second TFT device layer 13, and the driving electrode 10 are connected by a vertical glass via 14. The glass via 14 connects the first TFT device layer 11, the second TFT device layer 13, and the driving electrode 10 with the shortest distance, thereby maximizing the stacking density of the display back panel in three dimensions, minimizing the interconnections between layers, and minimizing the overall size. This simple and effective method improves the pixel density (PPI) of the digital microfluidic chip, thereby increasing the number and precision of droplet tearing by the digital microfluidic chip.
[0041] In this embodiment, specifically, the diameter of the glass through-hole is 5-50 μm.
[0042] In this embodiment, specifically, the glass through-hole is filled with a conductive and thermally conductive material.
[0043] More specifically: the conductive and thermally conductive material is any one of aluminum, molybdenum, copper, nickel, nickel-manganese alloy and nickel-chromium alloy, and is not limited to the above materials. The above materials are metals with the characteristics of large work function, good shape stability, electrical conductivity and thermal conductivity. That is, other metals with the characteristics of large work function, good shape stability, electrical conductivity and thermal conductivity can also be used as materials for conductive and thermally conductive layers.
[0044] The dielectric layer 9 serves to insulate and protect the driving electrode. In digital microfluidic applications, the first hydrophobic layer 6 and the second hydrophobic layer 8 can be made of Teflon, which has high crystallinity, tightly aligned molecules, and low porosity.
[0045] like Figure 2 As shown, this is another implementation of the method of the present invention to improve pixel density, wherein the functions of each layer are the same as those of the layers mentioned above, only arranged in a different way;
[0046] The glass via 14 provides a high-performance, low-cost solution for improving the performance and increasing the pixel density of digital microfluidic chips.
[0047] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in the present invention, and these should all be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A digital microfluidic chip, characterized in that: The digital microfluidic chip includes a top cover (1) and an electrode layer (2), and a droplet channel layer (3) disposed between the top cover (1) and the electrode layer (2). The top cover (1) includes an upper cover (4), a conductive layer (5), and a first hydrophobic layer (6) disposed sequentially. The electrode layer (2) includes a second hydrophobic layer (8), a dielectric layer (9), a driving electrode (10), a first TFT device layer (11), a substrate layer (12), and a second TFT device layer (13). The first hydrophobic layer (6) and the second hydrophobic layer (8) are disposed opposite to each other. A droplet flow channel layer (3) is formed between (6) and the second hydrophobic layer (8). The first TFT device layer (11) is a functional circuit layer and also serves as a backup driving circuit. The second TFT device layer (13) is a driving circuit layer. The glass via (14) penetrates the first TFT device layer (11), the substrate layer (12), and the second TFT device layer (13) in the vertical direction with the shortest distance. The first TFT device layer (11), the second TFT device layer (13), and the driving electrode (10) stacked in the vertical direction are directly interconnected through the glass via (14).
2. The digital microfluidic chip according to claim 1, characterized in that: The diameter of the glass through-hole (14) is 5-50 μm.
3. The digital microfluidic chip according to claim 1, characterized in that: The glass through-hole (14) is filled with a conductive and thermally conductive material.
4. The digital microfluidic chip according to claim 3, characterized in that: The conductive and thermally conductive material is any one of aluminum, molybdenum, copper, nickel, nickel-manganese alloy, and nickel-chromium alloy.
5. The digital microfluidic chip according to claim 1, characterized in that: The substrate layer (12) is made of either a transparent glass substrate or a plastic substrate.