Downlink Control for Ultra-Reliable Communications

Abstract

The present invention relates to downlink control of ultra-reliable communication. For downlink control, a method receives a control channel with a first aggregation level at a user equipment at a transmission time interval by using a processor. The method attempts to decode the control channel. In response to the control channel being successfully decoded, the method determines a first downlink control information (DCI) with a first number of bits based on the received control channel; determines whether to decode the first DCI to determine a second DCI with a second number of bits based on the first DCI; and if it is determined that the first DCI is to be decoded, determines the second DCI with a second number of bits based on the decoded first DCI. If the second DCI is an uplink grant, the method sends data according to the second DCI. If the second DCI is a downlink assignment, the method receives data according to the second DCI.

Description

[0001] This application is a divisional application of an application which entered the Chinese national phase on May 12, 2020, with PCT application number PCT / IB2018 / 001412, international application date November 14, 2018, Chinese application number 201880073192.5, and invention name “Downlink Control for Ultra-Reliable Communications”. Technical Field

[0002] The subject matter disclosed herein generally relates to reliable communications. Background Art

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS

[0004] Mobility devices may communicate based on control information. Summary of the invention

[0005] A method for downlink control is disclosed. The method receives a control channel having a first aggregation level at a transmission time interval at a user equipment by using a processor. The method attempts to decode the control channel. In response to the control channel being successfully decoded, the method determines a first downlink control information (DCI) having a first number of bits based on the received control channel; determines whether to decode the first DCI to determine a second DCI having a second number of bits based on the first DCI; and if it is determined that the first DCI is to be decoded, determines a second DCI having a second number of bits based on the decoded first DCI. If the second DCI is an uplink grant, the method sends data according to the second DCI. If the second DCI is a downlink assignment, the method receives data according to the second DCI. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A more particular description of the embodiments briefly described above will be presented by reference to specific embodiments illustrated in the accompanying drawings. Understanding that these drawings depict only some embodiments and are therefore not to be considered limiting of scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0007] Figure 1 is a schematic block diagram illustrating an embodiment of downlink control information size alignment;

[0008] Figure 2 is a schematic block diagram illustrating one embodiment of a processing method;

[0009] Figure 3 is a schematic block diagram illustrating an embodiment of an encoding method;

[0010] Figure 4 is a schematic block diagram illustrating an alternative embodiment of an encoding method;

[0011] Figure 5 is a schematic block diagram illustrating an alternative embodiment of downlink control information size alignment;

[0012] Figure 6 is a schematic block diagram illustrating one embodiment of repetition in sTTI;

[0013] Figure 7 is a schematic diagram illustrating an embodiment of a TTI mode;

[0014] Fig. 8A is a schematic block diagram illustrating one embodiment of a communication system;

[0015] Figure 8B is a schematic block diagram illustrating one embodiment of a user equipment;

[0016] Fig. 9 is a schematic flow chart illustrating one embodiment of a data communication method; and

[0017] Fig.10 is a schematic block diagram illustrating one embodiment of transmitting data. DETAILED DESCRIPTION

[0018] As will be appreciated by those skilled in the art, aspects of the embodiments may be embodied as systems, methods or program products. Thus, the embodiments may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or a combination of software and hardware aspects, which may generally be referred to herein as "circuit", "module" or "system". In addition, the embodiments may take the form of a program product embodied in one or more computer-readable storage devices stored in machine-readable code, computer-readable code and / or program code, hereinafter referred to as code. The storage device may be tangible, non-temporary and / or non-transmitting. The storage device may not embody a signal. In a certain embodiment, the storage device employs only a signal for accessing the code.

[0019] Many of the functional units described in this specification have been labeled as modules in order to more specifically emphasize their implementation independence. For example, a module can be implemented as a hardware circuit including a custom VLSI circuit or gate array, an off-the-shelf semiconductor device such as a logic chip, a transistor or other discrete components. A module can also be implemented in a programmable hardware device such as a field programmable gate array, a programmable array logic, a programmable logic device, etc.

[0020] Modules can also be implemented in code and / or software to be executed by various types of processors. The identified code modules can, for example, include one or more physical or logical blocks of executable code, which can, for example, be organized as objects, processes, or functions. However, the executable files of the identified modules do not need to be physically located together, but can include irrelevant instructions stored in different locations, which, when logically connected together, include the module and achieve the purpose of the module.

[0021] In fact, a code module can be a single instruction or many instructions, and can even be distributed in several different code segments, among different programs, and across several memory devices. Similarly, in this article, operating data can be identified and illustrated in a module, and can be embodied in any suitable form and organized in a data structure of any suitable type. Operating data can be collected as a single data set, or can be distributed in different locations, including on different computer-readable storage devices. When a module or part of a module is implemented in software, the software portion is stored on one or more computer-readable storage devices.

[0022] Any combination of one or more computer readable media may be utilized. The computer readable medium may be a computer readable storage medium. The computer readable storage medium may be a storage device storing code. The storage device may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, holographic, micromechanical or semiconductor system, apparatus or device, or any suitable combination of the foregoing.

[0023] More specific examples of storage devices (a non-exhaustive list) would include the following: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0024] The code for performing the operations of the embodiments may be written in any combination of one or more programming languages ​​including object-oriented programming languages ​​such as Python, Ruby, Java, Smalltalk, C++, and the like, and traditional procedural programming languages ​​such as the "C" programming language, and / or machine languages ​​such as assembly languages. The code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0025] References to "one embodiment", "embodiment" or similar language in this specification mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment. Therefore, unless otherwise expressly stated, the phrases "in one embodiment", "in an embodiment" and similar language appearing throughout the specification may but do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments". Unless otherwise expressly stated, the terms "including", "comprising", "having" and their variations mean "including but not limited to". Unless otherwise expressly stated, the list of items listed does not imply that any or all items are mutually exclusive. Unless otherwise expressly stated, the terms "a / an" and "the" also refer to "one or more".

[0026] In addition, the features, structures or characteristics of the described embodiments may be combined in any suitable manner. In the following description, many specific details are provided, such as examples of programming, software modules, user selections, network transactions, database queries, database structures, hardware modules, hardware circuits, hardware chips, etc., to provide a thorough understanding of the embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of the specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring some aspects of the embodiments.

[0027] The various aspects of the embodiments are described below with reference to the schematic flow charts and / or schematic block diagrams of the methods, devices, systems and program products according to the embodiments. It will be understood that each block of the schematic flow charts and / or schematic block diagrams and the combination of the blocks in the schematic flow charts and / or schematic block diagrams can be implemented by code. These codes can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that instructions executed by the processor of the computer or other programmable data processing device create a means for implementing the functions / operations specified in the schematic flow charts and / or schematic block diagram blocks or some blocks.

[0028] The code may also be stored in a storage device that is capable of instructing a computer, other programmable data processing apparatus, or other device to operate in a specific manner so that the instructions stored in the storage device produce an article of manufacture including instructions that implement the functions / operations specified in a block or some blocks of the schematic flowchart and / or schematic block diagram.

[0029] The code may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, so that the code executed on the computer or other programmable apparatus provides a process for implementing the functions / operations specified in a block or blocks of the flowchart and / or block diagram.

[0030] The schematic flow charts and / or schematic block diagrams in the accompanying drawings illustrate possible implementations of the apparatus, system, method, and program product according to various embodiments, architecture, functions, and operations. In this regard, each block in the schematic flow charts and / or schematic block diagrams may represent a module, segment, or portion of code, which includes one or more executable instructions of the code for implementing a specified logical function.

[0031] It should also be noted that in some alternative implementations, the functions annotated in the blocks may not occur in the order annotated in the drawings. For example, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functions involved. Other steps and methods are contemplated that are equivalent in function, logic, or effect to one or more blocks or portions thereof of the illustrated drawings.

[0032] Although various arrow types and line types can be used in flow charts and / or block diagrams, it should be understood that they do not limit the scope of the corresponding embodiments. In fact, some arrows or other connectors can only be used to indicate the logical flow of the depicted embodiment. For example, an arrow can indicate a waiting or monitoring period of unspecified duration between the enumeration steps of the depicted embodiment. It will also be noted that each block of the block diagram and / or flow chart and the combination of the blocks in the block diagram and / or flow chart can be realized by a combination of a dedicated hardware-based system or dedicated hardware and code that performs a specific function or operation.

[0033] The description of an element in each figure may refer to an element of the previous figure. The same numerals refer to the same elements in all figures, including alternative embodiments of the same elements.

[0034] Ultra-Reliable Low-Latency Communications (URLLC)

[0035] The number of blind decodes in a shortened transmission time interval (sTTI) is limited: for example, 6 blind decodes per 2 / 3 orthogonal frequency division multiplexing (OFDM) symbols, 12 blind decodes per 7 OFDM symbols for each shortened downlink control information (DCI) for sTTI operation. The sTTI operation is called sTTI-O for long-term evolution (LTE) with sTTI. For URLLC, a DCI size smaller than sDCI can be used (the URLLC DCI in sTTI is referred to as u-sDCI in this article) to be able to support lower coding rates and thus improve the reliability of the control channel, which in turn increases the reliability of packet transmission. In this case, at least two different DCI sizes (i.e., sDCI size and u-sDCI size) may be monitored in the sTTI, and therefore, the number of blind decodes should be shared between the two DCI sizes, which in turn reduces the number of blind decodes for each type of service: for example, sTTI-O and URLLC.

[0036] One solution for separating blind decoding between sTTI-O and URLCC services is to configure the number of candidates for each AL corresponding to the URLLC service and the number of normal sTTI candidates for each aggregation level (AL) corresponding to the sTTI service.

[0037] Another solution is not to separate blind decoding, but to use all blind decoding for both sTTI-O and URLLC services. This is usually achieved when the sDCI size and u-sDCI size are aligned and, for example, sDCI and u-sDCI are distinguished via one or more bits, for example, if different reliability targets are expected to be used for URLLC services in sDCI / u-sDCI, more than one bit may be required. However, if the payloads (i.e., information bits) of sDCI and u-sDCI are very different, it is invalid to fill zeros into u-sDCI. One solution is to virtually align the sDCI and u-sDCI sizes.

[0038] Figure 1 An embodiment is shown where the sizes of u-sDCI 111 and sDCI 113 are aligned. Assume that u-sDCI 111 has a length of "K" bits and sDCI 113 has a length of "L" bits (eg, excluding the DCI type specifier bit described below).

[0039] Figure 2 12 is a schematic block diagram illustrating an embodiment of a processing method 120 for aligning the sizes of u-sDCI 111 and sDCI 113. If 121 u-sDCI 111 is size A, the processor can determine the size of sDCI 113. If sDCI 113 is not size A, instead of applying "LK" zeros to u-sDCI 111 to make u-sDCI 111 equal in size to sDCI 113, the processor can apply 123 an internal channel coding scheme (K→L) to u-sDCI 111, where the number of output bits is equal to the number of bits in sDCI 113 (i.e., "L"). The processor can further add 125 a one-bit specifier that is not internally channel coded. In one example, one of the unused states of the DCI type field present in sDCI 113 can be used, for example, the unused state "11" of the 2-bit DCI type field can be used to indicate u-sDCI 111. In another example, the one-bit discriminator may be an unused or padded bit in sDCI 113, or a bit reused for DCI type distinction. In another example, sTTI-0SDCI 113 may be modified and extended by a one-bit discriminator. A user equipment (UE) distinguishes between sDCI 113 and u-sDCI 111. If a UE detects u-sDCI 111, the UE may apply decoding of "L" bits to obtain "K" bits.

[0040] The processor may add 127 cyclic redundancy check (CRC) appendages, such as u-sDCI parity bits 115. Different coding techniques may be used to expand the "K" bits to "L" bits, such as Reed-Muller, repetition codes, block coding, polar coding, convolutional codes, simplex codes, etc.

[0041] In one example, polar codes are used and "LK" bits are mapped to frozen bit positions of a polar core encoder. In one example, additional coding includes one or more of rate matching, interleaving, and bit scrambling as part of channel coding 129. In one example, bit scrambling (of a scrambling sequence (e.g., a Gold sequence)) is initialized based on the DCI type.

[0042] Only a portion of the u-sDCI may be encoded: for example, if the sizes of the uplink (UL) u-sDCI and downlink (DL) u-sDCI are aligned, and the UL vs. DL u-sDCI is distinguished based on a 1-bit distinguishing field in the u-sDCI, this portion may be excluded from encoding, e.g. Figure 5 By encoding and decoding only a portion of the u-sDCI, the additional complexity due to the additional encoding and decoding of the u-sDCI 111 may be reduced.

[0043] In the u-sDCI and sDCI size alignment, the processor may add 127 a cyclic CRC of the u-sDCI parity bits 115 after the u-sDCI 111. The processor may further perform channel coding 129 and rate matching 131.

[0044] In another embodiment, if Figure 3 As shown in the coding method 133 of FIG. 1 , the CRC size may be different for sDCI 113 and u-sDCI 111. Figure 2 However, instead of Figure 2 As shown, after additional encoding of u-sDCI 111 and before CRC attachment, the sDCI and u-sDCI sizes are aligned, the size of the encoded u-sDCI 111 is increased by 135 to "Aw" bits via additional channel coding, where Aw>A~, and after additional (partial) CRC attachment, the encoded and partially CRC-attached u-sDCI becomes "A" bits. In this example, w is an additional CRC bit for u-sDCI 111 (e.g., 2 bits out of a total of 18 CRC bits) compared to sDCI 113 (which has a 16-bit CRC). Channel coding 129 ( Figure 3After variable D in ), the size of sDCI 113 and u-sDCI 111 are the same. In one example, because the CRC sizes for sDCI 113 and u-sDCI 111 are different, no additional bits for DCI type distinction are required.

[0045] Figure 4 An alternative encoding method 137 is shown. Figure 2 and Figure 3 In the depicted embodiment, the u-sDCICRC consists of two constructed CRC subfields - the first CRC subfield ( Figure 3 other CRC described in ) is of length w, and the second CRC subfield is the same length and has the CRC polynomial as the sDCI CRC - in this case, the other DCI type distinguishing bits can be used (after the length w CRC is attached to the first CRC subfield, and before the second CRC subfield CRC is attached) to reduce the implementation complexity of the UE (for example, blind detection and possible increased confusion (likelihood of false alarms in control decoding, where, for example, the UE mistakenly detects a control message as its own control message) due to the smaller length w CRC used to distinguish the u-sDCI).

[0046] Figure 5 The diagram aligns the size of sDCI and u-sDCI by encoding a portion of u-sDCI 111. In order to achieve low latency in URLLC, retransmission can be enabled / configured / scheduled / medium access control (MAC)-control element (CE) activated before receiving confirmation / negative confirmation (ACK / NACK) in the uplink or downlink. For example, reliability requirements such as target block error rate (BLER) for retransmission can be more relaxed compared to the initial transmission of a transport block (TB). In one example, retransmission of a TB can be scheduled via u-sDCI 111 or sDCI 113 or even conventional DCI. Retransmission of a TB can be scheduled via sDCI 113, and a field in sDCI 113 can indicate that the DL scheduling assignment / UL grant is intended for URLLC.

[0047] If SPS is enabled (or configured) for URLLC, the u-sDCI 111 for URLLC-semi-persistent scheduling (SPS) (e.g., SPS activation or SPS release) may be scrambled by the SPS-radio network temporary identifier (RNTI) and the u-sDCI 111 may contain a distinguisher field 116 that distinguishes the u-sDCI 111 from the sTTI-O SPS (if different sDCI and u-sDCI sizes are used, the distinguishing field for SPS activation / release is not required). The URLLC-SPS may contain periodic positions in time (sTTI), and each instance may be repeated "N" times in time (e.g., in consecutive sTTIs), where "N" may be configured (e.g., via URLLC-SPS configuration), alternatively, "N" may be signaled in a DCI / sDCI / u-sDCI such as an SPS activation command. Each repetition may be confirmed individually, or a confirmation may be sent once a TB is correctly decoded (e.g., after a portion of the repetitions). In one example, hybrid automatic repeat request (HARQ)-ACK transmission and timing are based only on the last sTTI in a bundle (where a bundle consists of initial and retransmissions of TBs corresponding to one SPS occasion).

[0048] If the dynamic grant is u-sDCI 111, in case a repetition (DL or UL) collides with a dynamic grant / assignment for the same HARQ process, that instance of the repetition is dropped. If more than a certain number / part (referred to as "N_drop" in this document) corresponding to a transport block (TB) is dropped, the UE may not send the remaining repetitions in the UL or may not attempt to decode the remaining retransmissions. "N_drop" may be fixed in the relevant specification / data target BLER (e.g., for URLLC services with different BLER targets, the N_drop for a lower target BLER may be lower than the N_drop for a higher target BLER).

[0049] In an embodiment, URLLC-SPS is (re)activated / released via "N" u-sDCI 111 / control signals sent in multiple sTTIs. All or part of the u-sDCI / control signals sent in multiple sTTIs may be verified for corresponding SPS assignments. The verification process includes checking selected fields for verification against known field values.

[0050] In one embodiment, the u-sDCI field used for verification may be different among multiple u-sDCI / control signals sent in multiple sTTIs. In another embodiment, the same u-sDCI field is used on multiple sTTIs for SPS assignment verification. In another embodiment, the same u-sDCI field is used on "M" sTTIs in multiple sTTIs / "M" out of "N" instances of u-sDCI 111 for SPS assignment verification, where "M" is less than the number of sTTIs in multiple sTTIs / "M" is less than "N". In another embodiment, if the UE has verified the SPS verification field on at least "M" sTTIs in multiple sTTIs or "M" instances of control signals for SPS assignment verification, the UE verifies the SPS assignment, where "M" is less than the number of sTTIs in multiple sTTIs.

[0051] Figure 6 One embodiment of repetitions in a sTTI 117 is illustrated. A URLLC-SPS sTTI 117a is described for a repetition factor of 2. For a shortened physical downlink shared channel (sPDSCH) based on a demodulation reference signal (DMRS), if repetitions are specified / configured / signaled, the DMRS pattern across the repetitions is known to the UE. In another embodiment, the total number of BDs for URLLC services is configured per sTTI 117, and the total number of BDs for normal sTTI operation is given by the total number of BDs in the sTTI 117 minus the number of BDs corresponding to the URLLC services. If the URLLC service is disabled (e.g., by configuration), the total number of BDs may be used for normal sTTI operation.

[0052] In sTTI LTE, the search space in sTTI 117 is also limited to 16sCCE. And each shortened control channel element (sCCE) is 4 or 6 resource blocks (RBs). The sPDCCH RB set can be large (up to the system BW). If larger aggregation levels (ALs) are supported, such as 16ALs for URLLC, if the same search space is used for URLLC and sTTI services, scheduling only one AL=16 for URLLC will occupy the entire search space, prohibiting other UEs / services from being scheduled / (SPS) activated.

[0053] In one embodiment, if the UE is configured for URLLC service, the search space can be set to a larger value "N" sCCEs ("N" can be set in the specification, for example, N = min(32 sCCEs, rounded down to (system BW / {size of sCCEs in RB}) or "N" can be configured).

[0054] In another embodiment, the sTTI 117 normal sDCI candidates are limited only to the first search space (which is limited to 16 sCCEs), and if URLLC is configured in addition to sTTI, there is a second search space (e.g., consisting of M sCCEs) added to the first search space. The u-sDCI candidate can be in either the first search space or the second search space, or can span both the first search space and the second search space. The first search space and the second search space can be overlapping (partially or completely) or non-overlapping. In the case where the first search space and the second search space overlap, the sCCE of the first search space can be aligned (or may not be aligned) with another sCCE in the second search space (the same set of RBs).

[0055] Timing advance for sTTI

[0056] An embodiment of the minimum processing time and maximum supported timing advance combination is given in Table 1 below.

[0057] Table 1

[0058]

[0059] Table 1 Based on the assumption of minimum processing time (i.e., N+x) and maximum timing advance (TA max ) to reduce processing time and shorten TTI. For sub-time slot TTI 117, two different sets of minimum processing time and maximum timing advance (TA) can be used (Set 1 and Set 2 in Table 1).

[0060] The UE may indicate support for Set 1 or Set 2 for subslot TTI depending on the shortened physical downlink control channel (sPDCCH) RB set configuration (separate set indications for 1OSCRS-based sPDCCH, 2OS CRS-based sPDCCH, and DMRS-based sPDCCH) and possibly the reference signal type of the subslot PDSCH (i.e., DMRS-based subslot PDSCH / CRS-based subslot PDSCH). The minimum processing time assumption for subslot TTI operation (i.e., N+4, N+6, or N+8) is configured by the radio resource control (RRC).

[0061] For a UE configured with N+4 timing with sub-slot TTI set 1, if its TA becomes greater than 2048*Ts, it is not expected that the UE will receive sPDSCH and / or monitor sDCI 113, and / or perform any sTTI / URLLC operations (e.g., SPS). For a UE configured with N+6 timing with sub-slot TTI set 1, if its timing advance (TA) is greater than 10816*Ts, it is not expected that the UE will receive sPDSCH, and / or monitor sDCI 113, and / or perform any sTTI / URLLC operations (e.g., SPS).

[0062] For a UE configured with N+6 timing with sub-slot TTI set 2, if its TA is greater than 5120*Ts, it is not desirable for the UE to receive sPDSCH, and / or monitor sDCI 113, and / or perform any sTTI / URLLC operations (e.g., SPS). For a UE configured with N+8 timing with sub-slot TTI set 2, if its TA becomes greater than 13888*Ts, it is not desirable for the UE to receive sPDSCH, and / or monitor sDCI 113, and / or perform any sTTI / URLLC operations (e.g., SPS). For a UE configured with N+8 timing with sub-slot TTI set 2, if its TA becomes greater than 13888*Ts, it is not desirable for the UE to receive sPDSCH, and / or monitor sDCI 113, and / or perform any sTTI / URLLC operations (e.g., SPS).

[0063] In one embodiment, the TA value includes an initial transmission timing set relative to the received downlink timing based on a timing advance command received in a random access response (RAR) message, a MAC timing advance update command relative to the latest uplink timing, and an automatic uplink transmission timing adjustment that tracks changes in the received downlink timing.

[0064] The timing adjustment indication in the RAR message indicates the initial N for the timing advance group (TAG). TA The timing advance command for a TAG indicates the change in uplink timing relative to the current uplink timing of the TAG as 16T s Multiples of (TA particle size).

[0065] In case of random access response, if the UE is configured with TAG, the 11-bit timing advance command T for TAG A By T A = 0, 1, 2, ..., 256 indicates the index value N TA value, otherwise T A =0, 1, 2, ..., 1282, where the time alignment amount for TAG is NTA =T A ×16 given.

[0066] In other cases, the 6-bit timing advance command T for TAG A By T A =0, 1, 2, ..., 63 indicates that the current N TA The value is adjusted to the new N TA Value, N TA,new , where N TA,new =N TA,old +(T A -31)×16. Here, N TA The value is adjusted by a positive or negative amount indicating that the uplink transmission timing of the TAG is advanced or delayed by a given amount, respectively.

[0067] In LTE, the transmission of an uplink radio frame number i from a UE will be (N i ) before the start of the corresponding downlink radio frame at the UE. TA +N TA offset )×T s seconds, where if the UE is configured with SCG, 0≤N TA ≤4096 and otherwise 0≤N TA ≤20512. Unless otherwise specified, for frame structure type 1 (e.g., FDD), N TA offset = 0 and for frame structure type 2 (e.g., TDD), N TA offset =624.

[0068] In another embodiment, RRC reconfiguration is not triggered for "x" sTTI / subframes after TA becomes greater than the maximum TA. "x" may be fixed in the specification or configured or determined based on UE capabilities. "x" may depend on the processing timeline (e.g., "N+4", "N+6", "N+8") and / or subslot TTI set 1 or 2.

[0069] In another embodiment, for example, at least in the case of an SPS associated with STTI operation, if the UE's TA has become greater than the maximum TA corresponding to the configured processing timeline, the UE still monitors sDCI 113. In an embodiment, once the UE verifies the SPS associated with the UL sTTI operation, it does not send the corresponding UL signal until its TA becomes less than the maximum TA associated with the configured processing timeline (for example, if its TA becomes less than the large TA before the timer expires).

[0070] In another embodiment, if the UE is configured with N+4 timing with sub-slot TTI set 1, then if its TA becomes greater than 2048*Ts, the UE can switch to N+6 timing as long as its TA is less than 10816*Ts. In one example, a hysteresis region of h*Ts (or h1*Ts) can be used, and the UE switches back to N+4 timing if the TA value drops below (2048-h)*Ts. In one example, the UE can notify the eNB when the UE's TA becomes greater than (or when the UE expects / estimates that its TA has become greater than) 2048*T or greater than (2048-h1)*Ts by triggering a timing advance or timing margin report including this value based on the current timing advance value (TA) or the gap to the TAmax value (TAmax–TA). The TA corresponds to UE Latest N TA Value, that is, N TA,new . The reported values ​​in the TA report may have a TA granularity of, for example, 16Ts. The TA granularity of the values ​​in the TA report may be the same as the granularity of the values ​​in the TA command. The TA report provides an indication to the eNB of the minimum processing time that the UE needs to be re-updated. In one example, the UE may initiate a random access procedure and send a TA report MAC control element in a message 3 physical uplink shared channel (PUSCH) transmission.

[0071] In another embodiment, if the UE is configured with N+6 timings with sub-slot TTI set 1, if its TA becomes greater than 6144*Ts but less than 10816*Ts, and if the UE is configured with a shortened processing time, it is not desirable for the UE to monitor DCI in the PDCCH UE-specific search space, however, the UE monitors sDCI 113 in the PDCCH UE-specific search space. In one example, a hysteresis region of h2*Ts (or h3*Ts) may be used, and if the TA value drops below (6144-h2)*Ts, the UE continues to monitor DCI in the PDCCH UE-specific search space with a reduced processing time. In one example, if the UE is configured with a shortened processing time and its TA becomes greater than 6144*Ts, the UE may switch to a regular N+4 processing time for PDCCHs received in the UE-specific search space. In one example, when the TA of the UE becomes greater than 6144*Ts or greater than (6144-h3)*Ts, the UE may notify the eNB when the TA of the UE becomes greater than 6144*Ts or greater than (6144-h3)*Ts by triggering a timing advance or timing margin report including the value based on the current timing advance value (TA) or the gap to the TAmax value (TAmax-TA). TA corresponds to UE Latest N TA Value, that is, N TA,new. The reported values ​​in the TA report may have a TA granularity of, for example, 16Ts. The TA granularity of the values ​​in the TA report may be the same as the granularity of the values ​​in the TA command. The TA report provides an indication to the eNB that the UE needs to be reconfigured with an updated minimum processing time. In one example, the UE may initiate a random access procedure and send a TA report MAC control element in a message 3 PUSCH transmission.

[0072] In one embodiment, the UE may adjust the timing of its uplink transmissions at subframe #n+6 for a TA command received in subframe #n. In sTTI, the UE may adjust the timing of its sTTI uplink transmissions at subframe #n+6 for a TA command received in subframe #n. If the UE is configured with URLLC, the UE may adjust the timing of its sTTI uplink transmissions at subframe #n+x for a TA command received in subframe #n, where x<=6, and x may be fixed in the specification, may be configurable, or may be a UE capability. In another embodiment, the UE may adjust the timing of all uplink transmissions at subframe #n+6.

[0073] In one embodiment, the UE may transmit the uplink data at a timing better than or equal to ±4*T compared to the timing of the previous uplink transmission. S The timing advance command adjusts the timing of its transmission to the signaled timing advance value with a relative accuracy of 16 seconds. In one embodiment, the aforementioned uplink transmission is the most recent 1 ms uplink transmission. In another embodiment, the aforementioned uplink transmission is the most recent sTTI uplink transmission. In yet another embodiment, the aforementioned uplink transmission is the most recent sTTI / 1 ms uplink transmission. In one embodiment, the timing advance command indicates the change in uplink timing relative to the current uplink timing as 16T. s multiples of.

[0074] Figure 7 The sTTI pattern 141 is illustrated based on the number of PDCCH symbols relative to the sTTI index 145 in the subframe 119. In one embodiment, if the UE incorrectly decodes a DCI (for 1ms operation) as a DL sDCI 113, but it is already a 2 / 3 symbol PDCCH, when the PDCCH region is the same as the sTTI length, it is not desirable for the UE to receive sPDSCH or single-TTI DL sDCI 113. If the sDCI 113 is a multi-TTI sDCI 113, the sPDSCH assignment applies to sTTIs other than sTTI0.

[0075] In another embodiment, if sDCI 113 and DCI are distinguished via field 143 in DCI / sDCI (e.g., 1 bit: 0 for DCI, 1 for sDCI), then in sTTI#0 (as shown below), the SPS verification process includes verifying the sDCI / DCI distinction field in the PDCCH set for DCI if only 1ms-SPS is configured, and / or verifying sDCI 113 if only sTTI-SPS is configured.

[0076] In another embodiment, for SPS assignment (e.g., activation or release), DCI (corresponding to 1ms-SPS) / sDCI (corresponding to sTTI-SPS), a field comprising a certain number of bits (e.g., 3 bits) and / or bit states are used to distinguish DCI from sDCI 113: for example, for DCI, the field is set to "000", and for sDCI 113, the field is set to "111".

[0077] If the UE is configured for SPS operation corresponding to 1ms TTI, and the UE is also configured for SPS operation corresponding to shortened TTI or URLLC, if the UE is configured with sTTI operation, and if sDCI 113 and DCI are distinguished in sTTI#0 via a field in DCI / sDCI (e.g., 1 bit: 0 for DCI, 1 for sDCI).

[0078] If the UE receives a DCI associated with an SPS-RNTI, the verification field should be set so that 1ms-SPS and sTTI-SPS can be verified against each other with high probability (e.g., by having a sufficient number of bits to follow a constant / known pattern of "0" and "1" for the SPS-sDCI, and the pattern / field used for verification is very different or has a Hamming distance greater than the verification pattern / field used for 1ms-SPS). This solution can be used when only 1ms-SPS is configured and / or only sTTI-SPS is configured.

[0079] If the UE is configured for SPS operation corresponding to 1ms TTI and the UE is not configured for SPS operation corresponding to shortened TTI or URLLC, if the UE is configured with sTTI operation. If the UE receives a DCI related to SPS-RNTI and if the UE verifies the SPS assignment as 1ms-SPS, the UE shall not verify the SPS assignment if the DCI / sDCI 115 distinction field does not indicate the DCI.

[0080] sTTI-SPS conflicts with 1ms

[0081] In one embodiment, in case of collision between non-SPS PUSCH / PUCCH and SPS sPUSCH in the same subframe on a given carrier, and if it is configured / specified and SPS has been activated at least x sTTIs ago, the UE shall send non-SPS 1ms TTI transmissions and abandon / stop SPS sPUCCH transmissions. "x" may be configured or specified. In another embodiment, if SPS sPUSCH has been activated before PUSCH grant, then SPS sPUSCH is discarded in case of collision with non-SPS PUSCH, otherwise non-SPS PUSCH is discarded.

[0082] Fig. 8A 1 is a schematic block diagram illustrating one embodiment of a communication system 100. The system 100 includes a base station 105 and a UE 110. The base station 105 may be a gNodeB (gNB) base station and / or an evolved NodeB (eNB) LTE base station. The UE 110 may be a mobile phone, a machine type communication (MTC) device, a tablet computer, a laptop computer, and an embedded communication device in a car, a kiosk, an appliance, etc. The base station 105 and the UE 110 may communicate via a network 107.

[0083] Figure 8B 4 is a schematic block diagram illustrating one embodiment of a UE 110. In the depicted embodiment, the UE 110 includes a processor 405, a memory 410, a communication hardware 415, a transmitter 420, and a receiver 425. The memory 410 hard drive may include a semiconductor storage device, a hard drive, or a combination thereof. The memory 410 may store code. The processor 405 may execute code. The communication hardware 415 may communicate with the transmitter 420 and / or the receiver 425. The transmitter 420 may send wireless signals. The receiver 425 may receive wireless signals.

[0084] Fig. 9 is a schematic flow chart illustrating an embodiment of a data communication method 500. The method 500 may determine whether to decode a second DCI having a plurality of bits based on a first decoded DCI. The method 500 may be executed by the processor 405 of the UE 110 and / or the processor 405 of the base station 105.

[0085] The method 500 begins, and in one embodiment, the processor 405 receives 501 a control channel having a first AL in a TTI at the UE 110. The processor 405 of the base station 105 may send the control channel. In one embodiment, the control channel includes a first downlink control information (DCI) having a first number of bits and a second DCI having a second number of bits. The first DCI bit may be determined based on encoding the second DCI bit. In addition, the processor 405 of the base station 105 may send and the processor 405 of the UE 110 may receive 503 an indication in the first DCI indicating whether to decode the first DCI. In a certain embodiment, the processor 405 receives 503 an indication in the first DCI indicating whether to decode the first DCI.

[0086] The processor 405 may attempt 505 to decode the control channel. In one embodiment, the processor 405 of the UE 110 attempts 505 to decode the control channel of a first DCI size and a second DCI size, wherein the first DCI size corresponds to a first DCI type and the second DCI size corresponds to a second DCI type. The control channel may be decoded based on one or more of a first bit scrambling initialization corresponding to the first DCI type and a second bit scrambling initialization corresponding to the second DCI type. In one embodiment, if the first bit scrambling initialization is used to decode the control channel, the UE determines whether to decode the first DCI to determine the second DCI. Otherwise, the UE determines not to decode the first DCI.

[0087] In one embodiment, the first DCI includes a first bit sequence and a second bit sequence. In addition, decoding the first DCI may include decoding the first bit sequence and not decoding the second bit sequence. The processor 405 may determine 507 whether the control channel is successfully decoded.

[0088] In one embodiment, the control channel is decoded according to a decoding operation for a polar coded sequence. In some embodiments, the first DCI has "L" bits and the second DCI has "K" bits. In a specific embodiment, the "LK" bits are mapped to frozen bit positions of a polar core encoder.

[0089] If the processor 405 determines 507 that the control channel is not successfully decoded, the method 500 ends. If the processor 405 determines 507 that the control channel is successfully decoded, the processor 405 may determine 509 a first DCI having a first number of bits based on the received control channel. Additionally, the processor 405 may determine 511 whether to decode the first DCI to determine a second DCI having a second number of bits based on the first DCI. If it is determined that the first DCI is to be decoded, the processor 405 may determine 513 a second DCI having a second number of bits based on the decoded first DCI. In one embodiment, determining 513 the second DCI based on the decoded first DCI further includes decoding the first DCI to obtain a first bit set and removing CRC bits from the first bit set, such as Figure 3 As depicted in .

[0090] In one embodiment, the CRC associated with the first DCI has a first length and has a first CRC polynomial. In a certain embodiment, the CRC associated with the second DCI has a second length and includes two constructed CRC subfields. In one embodiment, the first CRC subfield has a third length. In a specific embodiment, the second CRC subfield has a first length and has a first CRC polynomial. In a certain embodiment, removing CRC bits from the first bit set includes removing the CRC bits corresponding to the first CRC subfield.

[0091] If the second DCI is an uplink (UL) grant or is sent by the processor 405 of the base station 105, the processor 405 of the UE 110 further sends 515 and the processor 405 of the base station 104 receives data according to the second DCI, and if the second DCI is a downlink (DL) assignment, the processor 405 of the UE 110 receives 517 data according to the second DCI, and the method 500 ends.

[0092] Fig.10 2 is a schematic block diagram illustrating an embodiment of transmission data. The transmission data may be encoded for transmission and / or organized into a data structure. The transmission data includes a frame 225. The frame 225 includes 10 subframes 235. Two subframes 235 may include a TTI 230. Each subframe 235 includes two time slots 240. Each time slot includes seven OFDM symbols 245.

[0093] Transmission data may also include AL 250, TB 255, TA 260, control channel 265, TA command 270, DCI 275, and configuration 280. AL 250, TB 255, TA 260, control channel 265, TA command 270, DCI 275, and configuration 280 may be embodied in one or more OFDM symbols 245. OFDM symbol 245 may transmit data.

[0094] Examples may include:

[0095] A method comprising:

[0096] By using a processor, receiving, at a user equipment (UE) a control channel having a first aggregation level (AL) in a transmission time interval (TTI);

[0097] Attempt to decode the control channel;

[0098] In response to the control channel being successfully decoded,

[0099] determining, based on the received control channel, first downlink control information having a first number of bits;

[0100] determining whether to decode the first DCI to determine a second DCI having a second number of bits based on the first DCI;

[0101] If it is determined that the first DCI is to be decoded, determining a second DCI having a second number of bits based on the decoded first DCI;

[0102] If the second DCI is an uplink (UL) grant, sending data according to the second DCI; and

[0103] If the second DCI is a downlink (DL) assignment, data is received according to the second DCI.

[0104] In some embodiments, the method further comprises receiving, in the first DCI, an indication indicating whether to decode the first DCI.

[0105] In some embodiments, the second number of bits of the second DCI is less than the first number of bits of the first DCI.

[0106] In some embodiments, the number of bits of the second DCI is determined based on the first AL.

[0107] In some embodiments, the UE attempts to decode a control channel of a first DCI size and a second DCI size, wherein the first DCI size corresponds to a first DCI type and the second DCI size corresponds to a second DCI type.

[0108] In some embodiments, decoding the control channel further comprises: decoding the control channel based on:

[0109] A first bit scrambling initialization corresponding to a first DCI type; and

[0110] A second bit scrambling corresponding to the second DCI type is initialized.

[0111] In some embodiments, if the first bit scrambling initialization is used in decoding of the control channel, the UE determines whether to decode the first DCI to determine the second DCI, otherwise, the UE determines not to decode the first DCI.

[0112] In some embodiments:

[0113] The first DCI includes a first bit sequence and a second bit sequence; and

[0114] Decoding the first DCI includes decoding the first bit sequence and not decoding the second bit sequence.

[0115] In some embodiments, determining the second DCI based on the decoded first DCI further comprises:

[0116] decoding the first DCI to obtain a first set of bits; and

[0117] Cyclic redundancy check (CRC) bits are removed from the first set of bits.

[0118] In certain embodiments:

[0119] A CRC associated with the first DCI has a first length and has a first CRC polynomial;

[0120] The CRC associated with the second DCI has a second length and includes two constructed CRC subfields;

[0121] The first CRC subfield has a third length; and

[0122] The second CRC subfield has a first length and has a first CRC polynomial; and

[0123] Removing CRC bits from the first set of bits includes removing CRC bits corresponding to a first CRC subfield.

[0124] In some embodiments:

[0125] decoding the control channel according to a decoding operation of the polarity coded sequence;

[0126] The first DCI has "L" bits and the second DCI has "K" bits; and

[0127] The "LK" bits are mapped to the frozen bit positions of the polar kernel encoder.

[0128] A device comprising:

[0129] A processor that performs:

[0130] receiving, at a user equipment (UE) in a transmission time interval (TTI), a control channel having a first aggregation level (AL);

[0131] Attempt to decode the control channel;

[0132] In response to the control channel being successfully decoded,

[0133] determining, based on the received control channel, first downlink control information having a first number of bits;

[0134] determining whether to decode the first DCI to determine a second DCI having a second number of bits based on the first DCI;

[0135] If it is determined that the first DCI is to be decoded, determining a second DCI having a second number of bits based on the decoded first DCI;

[0136] If the second DCI is an uplink (UL) grant, sending data according to the second DCI; and

[0137] If the second DCI is a downlink (DL) assignment, data is received according to the second DCI.

[0138] In some embodiments, the processor further receives an indication in the first DCI indicating whether to decode the first DCI.

[0139] In some embodiments, the second number of bits of the second DCI is less than the first number of bits of the first DCI.

[0140] In some embodiments, the number of bits of the second DCI is determined based on the first AL.

[0141] In some embodiments, the UE attempts to decode a control channel of a first DCI size and a second DCI size, wherein the first DCI size corresponds to a first DCI type and the second DCI size corresponds to a second DCI type.

[0142] In some embodiments, decoding the control channel further comprises decoding the control channel based on:

[0143] A first bit scrambling initialization corresponding to a first DCI type; and

[0144] A second bit scrambling corresponding to the second DCI type is initialized.

[0145] In some embodiments, if the first bit scrambling initialization is used when decoding the control channel, the UE determines whether to decode the first DCI to determine the second DCI, otherwise, the UE determines not to decode the first DCI.

[0146] In some embodiments:

[0147] The first DCI includes a first bit sequence and a second bit sequence; and

[0148] Decoding the first DCI includes decoding the first bit sequence and not decoding the second bit sequence.

[0149] A method comprising:

[0150] By using a processor, at a base station, transmitting a control channel having a first aggregation level (AL) in a transmission time interval (TTI), wherein the control channel includes first downlink control information (DCI) having a first number of bits based on the received control channel and a second DCI having a second number of bits based on the first DCI;

[0151] If the second DCI is an uplink (UL) assignment, receiving data according to the second DCI; and

[0152] If the second DCI is a downlink (DL) assignment, data is sent according to the second DCI.

[0153] Embodiments may be practiced in other specific forms. The described embodiments should be considered in all respects as merely illustrative and not restrictive. Therefore, the scope of the present invention is indicated by the appended claims rather than the preceding description. All changes within the meaning and equivalent range of the claims are included within their scope.

Claims

1. A method at a device, the method comprising: receiving a semi-persistent scheduling (SPS) configuration for a first set of physical uplink shared channel (PUSCH) transmissions; receiving downlink control information (DCI) scheduling a second uplink (UL) transmission; determining whether any one of the first set of PUSCH transmissions overlaps with the second UL transmission; as well as In response to determining that a PUSCH transmission in the first set of PUSCH transmissions overlaps with the second UL transmission, determining whether to drop the PUSCH transmission in the first set of PUSCH transmissions based on the SPS configuration.

2. The method according to claim 1, wherein: The second UL transmission is a PUSCH transmission.

3. The method according to claim 1, wherein: The second UL transmission is a PUCCH transmission.

4. The method according to claim 1, wherein: The second UL transmission is sent in response to a determination to drop the PUSCH transmission in the first set of PUSCH transmissions.

5. The method according to claim 1, wherein: The second UL transmission is dropped in response to a determination not to drop the PUSCH transmission in the first set of PUSCH transmissions.

6. The method according to claim 1, wherein: The first set of PUSCH transmissions corresponds to Ultra-Reliable Low Latency Communication (URLLC).

7. The method according to claim 1, wherein: Determining whether to drop the PUSCH transmission in the first set of PUSCH transmissions based on the SPS configuration includes determining whether to drop the PUSCH transmission in the first set of PUSCH transmissions based on whether the SPS configuration has been activated for at least 'X' time intervals.

8. The method according to claim 7, wherein: Configure 'X'.

9. The method according to claim 2, wherein: The PUSCH transmissions in the first set of PUSCH transmissions and the PUSCH transmissions in the second UL transmission are associated with a same Hybrid Automatic Repeat Request (HARQ) process.

10. The method according to claim 1, wherein: The PUSCH transmissions in the first set of PUSCH transmissions include 'N' repetitions of a transport block (TB).

11. The method according to claim 10, wherein: 'N' is indicated in the corresponding DCI activating the SPS configuration.

12. The method according to claim 10, wherein: If more than N repetitions of the TB have been discarded, the remaining repetitions of the TB are not sent.

13. An apparatus for ultra-reliable communication, comprising: processor; a memory storing code executable by the processor to cause the apparatus to: receiving a semi-persistent scheduling (SPS) configuration for a first set of physical uplink shared channel (PUSCH) transmissions; receiving downlink control information (DCI) scheduling a second uplink (UL) transmission; determining whether any one of the first set of PUSCH transmissions overlaps with the second UL transmission; as well as In response to determining that a PUSCH transmission in the first set of PUSCH transmissions overlaps with the second UL transmission, Determining whether to drop the PUSCH transmission in the first set of PUSCH transmissions is based on the SPS configuration.

14. The device according to claim 13, wherein: The second UL transmission is a PUSCH transmission.

15. The device according to claim 13, wherein: The second UL transmission is a PUCCH transmission.

16. The device according to claim 13, wherein: The second UL transmission is sent in response to a determination to drop the PUSCH transmission in the first set of PUSCH transmissions.

17. The device according to claim 13, wherein: The second UL transmission is dropped in response to a determination not to drop the PUSCH transmission in the first set of PUSCH transmissions.

18. The device according to claim 13, wherein: The first set of PUSCH transmissions corresponds to Ultra-Reliable Low Latency Communication (URLLC).

19. The device according to claim 13, wherein: Determining whether to drop the PUSCH transmission in the first set of PUSCH transmissions based on the SPS configuration further includes determining whether to drop the PUSCH transmission in the first set of PUSCH transmissions based on whether the SPS configuration has been activated for at least 'X' time intervals.

20. A computer program product comprising a non-transitory computer-readable storage medium storing code, the code being executable by a processor to perform: receiving a semi-persistent scheduling (SPS) configuration for a first set of physical uplink shared channel (PUSCH) transmissions; receiving downlink control information (DCI) scheduling a second uplink (UL) transmission; determining whether any one of the first set of PUSCH transmissions overlaps with the second UL transmission; and In response to determining that a PUSCH transmission in the first set of PUSCH transmissions overlaps with the second UL transmission, Determining whether to drop the PUSCH transmission in the first set of PUSCH transmissions is based on the SPS configuration.

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