Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes K columns of first pads. Each first pad is connected to an anode of a light-emitting element, a second electrode of a fifth transistor, and a second electrode of a sixth transistor. The K columns of first pads include a plurality of first-first pads located in a (2k-1)th column among the K columns and a plurality of second-first pads located in a (2k-th column) among the K columns. Each first-first pad and each second-first pad have different average line widths.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light-emitting diode (OLED) displays are one of the hot topics in the field of flat panel display research today. Unlike thin-film transistor-liquid crystal displays (TFT-LCDs) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control light emission. The OLED display panel includes a plurality of pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied from the data line to the driving transistor via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the Invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising K columns of first pads; wherein each first pad is connected to an anode of a light-emitting element, a second electrode of a fifth transistor, and a second electrode of a sixth transistor; the K columns of first pads include a plurality of first-first pads located in a (2k-1)th column among the K columns and a plurality of second-first pads located in a (2k)th column among the K columns; and each first-first pad and each second-first pad has a different average line width.

[0004] Optionally, the array substrate further includes a plurality of first-first reset signal lines located in the (2k-1)th column among the K columns and a plurality of second-first reset signal lines located in the (2k)th column among the K columns; wherein the first parasitic capacitance between each first-first pad located in the (2k-1)th column among the K columns and the corresponding first reset signal line is different from the second parasitic capacitance between each second-first pad located in the (2k)th column among the K columns and the corresponding second-first reset signal line.

[0005] Optionally, the first parasitic capacitance is at least 5% greater than the second parasitic capacitance.

[0006] Optionally, the respective first-first pads located in the (2k-1)th column among the K columns and the orthographic projections of the corresponding first-first reset signal lines overlap with each other in a first overlapping region having a first area; the respective second-first pads located in the (2k)th column among the K columns and the orthographic projections of the corresponding second-first reset signal lines overlap with each other in a second overlapping region having a second area; and the first area and the second area are different from each other.

[0007] Optionally, the first area is at least 5% larger than the second area.

[0008] Optionally, the first portion of each first-first pad located in the first overlapping area has a first width along the first direction; the second portion of each second-first pad located in the second overlapping area has a second width along the first direction; and the first width is greater than the second width.

[0009] Optionally, the first width is at least 5% greater than the second width.

[0010] Optionally, a virtual line passes through the first portion and the second portion; along the virtual line, the respective first-first reset signal lines have a third width, and the respective second-first reset signal lines have a fourth width; the third width is substantially the same as the fourth width; and the first width is greater than the third width and greater than the fourth width.

[0011] Optionally, a ratio of a total number of the first-first reset signal lines to a total number of the first-first pads is the same as a ratio of a total number of the second-first reset signal lines to a total number of the second-first pads.

[0012] Optionally, the array substrate further includes a plurality of gate lines; wherein each of the first pads crosses a corresponding gate line among the plurality of gate lines.

[0013] Optionally, the array substrate further includes a plurality of reset control signal lines and a plurality of light-emitting control signal lines; wherein the orthographic projection of each first pad on the base substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line among the plurality of reset control signal lines on the base substrate; or the orthographic projection of the first pad on the base substrate at least partially overlaps with the orthographic projection of the corresponding light-emitting control signal line among the plurality of light-emitting control signal lines on the base substrate.

[0014] Optionally, the array substrate further includes a plurality of voltage supply lines; wherein each pixel driving circuit includes: a second pad; a node connection line; and a storage capacitor including a first capacitor electrode; wherein the second pad is connected to a corresponding voltage supply line among the plurality of voltage supply lines; the node connection line connects the first capacitor electrode in each pixel driving circuit to the first electrode of a third transistor; and an orthographic projection of the second pad on the base substrate covers at least 50% of an orthographic projection of the node connection line on the base substrate.

[0015] Optionally, an orthographic projection of the second pad on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor on the base substrate.

[0016] Optionally, the array substrate further includes a plurality of gate lines; wherein each of the plurality of gate lines includes a main portion extending along an extension direction of the respective gate lines and a gate protrusion protruding away from the main portion; and the orthographic projection of the second pad on the base substrate covers at least 50% of the orthographic projection of the gate protrusion on the base substrate.

[0017] Optionally, the array substrate further includes a plurality of data lines; wherein the second pad includes a fourth pad portion, a fifth pad portion and a sixth pad portion, the fifth pad portion connects the fourth pad portion to the sixth pad portion; and the fifth pad portion crosses corresponding data lines among the plurality of data lines located in adjacent pixel driving circuits, wherein the adjacent pixel driving circuits and the respective pixel driving circuits are in the same row along the first direction.

[0018] Optionally, the orthographic projection of the fourth pad portion on the substrate at least partially overlaps with the orthographic projection of the node connection line in each pixel driving circuit on the substrate; and the orthographic projection of the sixth pad portion on the substrate at least partially overlaps with the orthographic projection of a corresponding adjacent voltage supply line among the multiple voltage supply lines located in the adjacent pixel driving circuit on the substrate.

[0019] Optionally, the array substrate further includes an anode connection pad and an anode; wherein each first pad is connected to the first relay electrode through a ninth via extending through the first planarization layer, and is connected to the second relay electrode through a tenth via extending through the first planarization layer; the first relay electrode is connected to the second electrode of the fifth transistor through an eleventh via extending through at least the interlayer dielectric layer; the second relay electrode is connected to the second electrode of the sixth transistor through a twelfth via extending through at least the interlayer dielectric layer; the anode connection pad is connected to each first pad through a thirteenth via extending through the second planarization layer; and the anode is connected to the anode connection pad through a fourteenth via extending through the third planarization layer.

[0020] Optionally, the array substrate further includes a plurality of second reset signal lines located in a different layer from the plurality of first-first reset signal lines and the plurality of second-first reset signal lines; the plurality of second reset signal lines extend along a first direction; the plurality of first-first reset signal lines and the plurality of second-first reset signal lines extend along a second direction; each second reset signal line is configured to provide an initialization signal to the first electrode of the sixth transistor in each pixel driving circuit; each first-first reset signal line is configured to provide an initialization signal to the first electrode of the first transistor in the first-first corresponding pixel driving circuit in the (2k-1)th column; and each second-first reset signal line is configured to provide an initialization signal to the first electrode of the first transistor in the second-first corresponding pixel driving circuit in the (2k)th column.

[0021] Optionally, the pixel driving circuit located in the (2k-1)th column among the K columns is a pixel driving circuit for driving sub-pixels of a first color and sub-pixels of a second color to emit light; the pixel driving circuit located in the (2k)th column among the K columns is a pixel driving circuit for driving sub-pixels of a third color to emit light; and the first color, the second color and the third color are different from each other.

[0022] Optionally, the array substrate includes a display area, an additional display area and a peripheral area; wherein the additional display area extends away from the display area to a side area of ​​the peripheral area; the array substrate includes a plurality of light-emitting elements and a plurality of pixel driving circuits; the plurality of pixel driving circuits are located in the display area; a portion of the plurality of light-emitting elements are present in the additional display area; and transistors and capacitors of the plurality of pixel driving circuits are not present in the additional display area.

[0023] Optionally, a light-emitting layer corresponding to a plurality of pixel driving circuits along the boundary between the display area and the additional display area is located in the additional display area; the array substrate further includes a plurality of anode connection pads, which connect the pixel driving circuit along the boundary between the display area and the additional display area with the light-emitting layer located in the additional display area; and each of the plurality of anode connection pads electrically connects the second electrode of the sixth transistor to the anode of the corresponding light-emitting element located in the additional display area.

[0024] Optionally, in the additional display area, the orthographic projections of the multiple anode connection pads on the substrate partially overlap with the orthographic projections of the respective first sub-pixels on the substrate, forming a first overlapping area; the orthographic projections of the multiple anode connection pads on the substrate partially overlap with the orthographic projections of the respective second sub-pixels on the substrate, forming a second overlapping area; the orthographic projections of the multiple anode connection pads on the substrate partially overlap with the orthographic projections of the respective third sub-pixels on the substrate, forming a third overlapping area; the first overlapping area is greater than the second overlapping area; the third overlapping area is greater than the second overlapping area; and the respective first sub-pixels, the respective second sub-pixels and the respective third sub-pixels are sub-pixels of different colors.

[0025] In another aspect, the present disclosure provides a display device comprising the array substrate described herein and an integrated circuit connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The following drawings are examples for illustration purposes only and are not intended to limit the scope of the invention, in accordance with various disclosed embodiments.

[0027] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 2A is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0029] Figure 2B is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0030] Figure 2C is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0031] Figure 3A is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0032] Figure 3B It shows Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate depicted in FIG.

[0033] Figure 3C It shows Figure 3A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG.

[0034] Figure 3D It shows Figure 3A Schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG.

[0035] Figure 3E It shows Figure 3A Schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG.

[0036] Figure 3F It shows Figure 3A Schematic diagram of the structure of the insulating layer in the array substrate depicted in FIG.

[0037] Figure 3G It shows Figure 3A Schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0038] Figure 3H It shows Figure 3A Schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG.

[0039] Figure 3I It shows Figure 3A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG.

[0040] Figure 3J It shows Figure 3A Schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0041] Figure 3K It shows Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG.

[0042] Figure 3L It shows Figure 3A Schematic diagram of the structure of the anode connection pad layer in the array substrate depicted in FIG.

[0043] Figure 3M It shows Figure 3A Schematic diagram of the structure of the third planarization layer in the array substrate depicted in FIG.

[0044] Figure 3N It shows Figure 3A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0045] Figure 4A It is along Figure 3A Cross-sectional view along line AA'.

[0046] Figure 4B It is along Figure 3A Cross-sectional view along line BB'.

[0047] Figure 4C It is along Figure 3A Cross-sectional view of the CC' line in FIG.

[0048] Figure 4D It is along Figure 3A Cross-sectional view along line D-D'.

[0049] Figure 5A Shown Figure 3A The network of reset signal lines in the array substrate is depicted in FIG.

[0050] Figure 5B Shown Figure 3A The structure of the first pad and the first reset signal line in the array substrate is depicted in FIG.

[0051] Figure 5C It is along Figure 5B Cross-sectional view along line EE'.

[0052] Figure 5D It is along Figure 5B Cross-sectional view along the line F-F'.

[0053] Figure 5E It is a stack of respective first-first pads and respective second-first pads.

[0054] Figure 5F The structure of the first pad according to some embodiments of the present disclosure is shown.

[0055] Figure 6A The structures of the first signal line layer and the second signal line layer according to some embodiments of the present disclosure are shown.

[0056] Figure 6B The structure of the second pad according to some embodiments of the present disclosure is shown.

[0057] Figure 7 is a schematic diagram illustrating a display area and a peripheral area in an array substrate according to some embodiments of the present disclosure.

[0058] Figure 8 is a schematic diagram illustrating a display area and a peripheral area in an array substrate according to some embodiments of the present disclosure.

[0059] Figure 9Arrangements of a pixel driving circuit and a light emitting layer in an area around a boundary between a display area and an additional display area in some embodiments according to the present disclosure are shown.

[0060] Figure 10 Images of several layers in an area around a boundary between a display area and an additional display area in some embodiments according to the present disclosure are shown.

[0061] Figure 11A The structures of various pixel driving circuits and various light-emitting elements in some embodiments of the present disclosure are shown.

[0062] Figure 11B Shown Figure 11A The structure of the semiconductor material layer in the array substrate is depicted in FIG.

[0063] Figure 11C Shown Figure 11A The structure of the first conductive layer in the array substrate is depicted in FIG.

[0064] Figure 11D Shown Figure 11A The structure of the insulating layer in the array substrate is depicted in FIG.

[0065] Figure 11E Shown Figure 11A The structure of the second conductive layer in the array substrate is depicted in FIG.

[0066] Figure 11F Shown Figure 11A The structure of the first signal line layer in the array substrate is depicted in FIG.

[0067] Figure 11G Shown Figure 11A The structure of the second signal line layer in the array substrate is depicted in FIG.

[0068] Figure 11H Shown Figure 11A The structure of the third signal line layer in the array substrate is depicted in FIG.

[0069] Figure 11I Shown Figure 11A The structure of the anode layer in the array substrate is depicted in FIG.

[0070] Figure 11J Shown Figure 11A The structure of the pixel defining layer in the array substrate is depicted in FIG.

[0071] Figure 11K Shown Figure 11A The structure of the light-emitting layer in the array substrate is depicted in FIG.

[0072] Figure 12A It is along Figure 11A Cross-sectional view along line G-G'.

[0073] Figure 12B It is along Figure 11A Cross-sectional view along the H-H' line.

[0074] Figure 13A The structure in the second region of the array substrate according to some embodiments of the present disclosure is shown.

[0075] Figure 13B Shown Figure 13A The structure of the pixel driving circuit in FIG.

[0076] Figure 13C Shown Figure 13A The structure of the connecting lines in .

[0077] Figure 13D Shown Figure 13A The structure of the light-emitting element in FIG.

[0078] Figure 14 The structure of the anode connection pad layer, the anode layer and the light emitting layer according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0079] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise forms disclosed.

[0080] The present disclosure particularly provides an array substrate and a display device, which substantially eliminate one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes K columns of first pads. Optionally, each first pad is connected to the anode of the light-emitting element, the second electrode of the fifth transistor, and the second electrode of the sixth transistor. Optionally, the K columns of first pads include a plurality of first-first pads in the (2k-1)th column in the K columns and a plurality of second-first pads in the (2k)th column in the K columns. Optionally, each first-first pad and each second-first pad are formed to have different average line widths.

[0081] As used herein, with respect to the various patterns or patterned materials described herein, the term "average line width" refers to a dimension determined by taking two or more independent measurements of a line at different locations on the same or different lines using appropriate measurement techniques and equipment. As used herein, with respect to the various patterns or patterned materials described herein, the term "width" refers to the smaller dimension of an elongated shape, for example, the dimension along the first direction DR1 for each first-first pad and each second-first pad.

[0082] Various suitable pixel drive circuits can be used in this array substrate. Examples of suitable drive circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each of the multiple pixel drive circuits is a 7T1C drive circuit. Various suitable light-emitting elements can be used in this array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0083] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage supply lines Vdd. The light emission of each sub-pixel is driven by a corresponding pixel driving circuit PDC. In one example, a high-voltage signal is input to a corresponding pixel driving circuit PDC connected to the anode of the light-emitting element through each of the plurality of voltage supply lines Vdd; a low-voltage signal is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., VDD signal) and the low-voltage signal (e.g., VSS signal) is a driving voltage DV, which drives the light-emitting element to emit light.

[0084] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, respective third sub-pixels, and respective fourth sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in an S1-S2-S3-S4 format, where S1 represents each first sub-pixel, S2 represents each second sub-pixel, S3 represents each third sub-pixel, and S4 represents each fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents each first sub-pixel of a first color, C2 represents each second sub-pixel of a second color, C3 represents each third sub-pixel of a third color, and C4 represents each fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents each first subpixel of a first color, C2 represents each second subpixel of a second color, C3 represents each third subpixel of a third color, and C2' represents each fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is an RGBG format, where each first subpixel is a red subpixel, each second subpixel is a green subpixel, each third subpixel is a blue subpixel, and each fourth subpixel is a green subpixel.

[0085] In some embodiments, a minimum repeating unit of a plurality of sub-pixels of an array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td.

[0086] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, each pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line among a plurality of reset control signal lines rst, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vintc, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate line, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst, and the gate of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td; a fourth transistor T4 having a gate connected to a corresponding light emitting control signal line among the plurality of light emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among the plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; a fifth transistor T5 having a gate connected to the corresponding light emitting control signal line, a first electrode connected to the second electrode of the driving transistor Td and the second electrode of the third transistor T3, and a second electrode connected to the anode of the light emitting element LE; and a sixth transistor T6 having a gate connected to a corresponding reset control signal line among the plurality of reset control signal lines rst, a first electrode connected to a corresponding second reset signal line among the plurality of second reset signal lines Vintr, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the fourth transistor T4.

[0087] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2B In some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (in other words, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding gate line among the plurality of gate lines GL twice (in other words, the corresponding gate line crosses the active layer of the third transistor T3 twice).

[0088] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0089] Figure 2C is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2C In some embodiments, the gate of the first transistor T1 is connected to the corresponding reset control signal line rstN of the current stage (or current row) of the plurality of reset control signal lines. The gate of the sixth transistor T6 is connected to the corresponding reset control signal line rst(N+1) of the next adjacent stage (or next adjacent row) of the plurality of reset control signal lines.

[0090] Figure 3A is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. Figure 3B It shows Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate depicted in FIG. Figure 3B A portion of an array substrate is depicted having eight pixel driving circuits, including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, and PDC8. The pixel driving circuits are arranged in multiple columns, including the (2k-1)th column C(2k-1) and the (2k)th column C(2k). Figure 3A A portion of an array substrate having two pixel driving circuits is depicted, the two pixel driving circuits being located in the (2k-1)th column and the (2kth column) respectively. In one example, Figure 3A The two pixel driving circuits in Figure 3B PDC1 and PDC2 in.

[0091] As used herein, the terms "column (2k-1)" and "column (2k)" are used in the context of column K. The array substrate may or may not include additional columns (one or more) before the first column in column K and / or additional columns after the last column in column K. In the context of the array substrate, the term "column (2k-1)" does not necessarily refer to an odd column in the array substrate, and the term "column (2k)" does not necessarily refer to an even column in the array substrate. In one example, column (2k-1) is an odd column in the context of column K, but may be an even column in the context of the array substrate. In another example, column (2k-1) is an odd column in the context of column K and is also an odd column in the context of the array substrate. In one example, column (2k) is an even column in the context of column K, but may be an odd column in the context of the array substrate. In another example, column (2k) is an even column in the context of column K and is also an even column in the context of the array substrate.

[0092] Figure 3C It shows Figure 3A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG. Figure 3D It shows Figure 3A Schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG. Figure 3E It shows Figure 3A Schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG. Figure 3F It shows Figure 3A Schematic diagram of the structure of the insulating layer in the array substrate depicted in FIG. Figure 3G It shows Figure 3A Schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 3H It shows Figure 3A Schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG. Figure 3I It shows Figure 3A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG. Figure 3J It shows Figure 3A Schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Figure 3K It shows Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG. Figure 3L It shows Figure 3A Schematic diagram of the structure of the anode connection pad layer in the array substrate depicted in FIG. Figure 3M It shows Figure 3A Schematic diagram of the structure of the third planarization layer in the array substrate depicted in FIG. Figure 3N It shows Figure 3A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Figure 4A It is along Figure 3A Cross-sectional view along line AA'. Figure 4B It is along Figure 3A Cross-sectional view along line BB'. Figure 4C It is along Figure 3A Cross-sectional view along line CC'. Figure 4D It is along Figure 3A Cross-sectional view along line D-D'.

[0093] Reference Figures 3A to 3N as well as Figures 4A to 4D In some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML located on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer CT1 located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer away from the gate insulating layer GI, a second conductive layer CT2 located on a side of the insulating layer IN away from the first conductive layer CT1, an interlayer dielectric layer ILD located on a side of the second conductive layer CT2 away from the insulating layer IN, a first signal line layer SL1 located on a side of the interlayer dielectric layer ILD away from the second conductive layer CT2, and a position A first planarization layer PLN1 on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD, a second signal line layer SL2 on the side of the first planarization layer PLN1 away from the first signal line layer SL1, a second planarization layer PLN2 on the side of the second signal line layer SL2 away from the first planarization layer PLN1, an anode connection pad layer ACPL on the side of the second planarization layer PLN2 away from the second signal line layer SL2, a third planarization layer PLN3 on the side of the anode connection pad layer ACPL away from the second planarization layer PLN2, and an anode layer ADL on the side of the third planarization layer PLN3 away from the anode connection pad layer ACPL.

[0094] Reference Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3CEach pixel driving circuit is labeled with a reference number indicating the region corresponding to the multiple transistors in each pixel driving circuit. The multiple transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a driving transistor Td. Each pixel driving circuit is also labeled with a reference number indicating the components of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0095] In some embodiments, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are located on the same layer. Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit, at least a portion of the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and at least a portion of the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are located on the same layer. Optionally, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) in each pixel driving circuit are located on the same layer.

[0096] In some embodiments, the active layers ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd of the transistors T1, T2, T3, T4, T5, and Td in each pixel driving circuit are part of the first integral structure. In another example, the active layers ACT1, ACT2, ACT3, ACT4, ACT5, and ACTd of the transistors T1, T2, T3, T4, T5, and Td in each pixel driving circuit, the first electrodes S1, S2, S3, S4, S5, and Sd, and the second electrodes D1, D2, D3, D4, D5, and Dd are part of the first integral structure. Figure 3C As shown, in some embodiments, the active layer ACT6 of the transistor T6 in each pixel driving circuit is separated from the first overall structure, and the first overall structure includes the active layers ACT1, ACT2, ACT3, ACT4, ACT5 and ACTd of the transistors T1, T2, T3, T4, T5 and Td in each pixel driving circuit.

[0097] In some embodiments, the active layer ACT6 of the transistor T6, at least a portion of the first electrode S6, and at least a portion of the second electrode D6 in each pixel driving circuit are part of the second integral structure. Alternatively, the active layer ACT6 of the transistor T6, the first electrode S6, and the second electrode D6 in each pixel driving circuit are part of the second integral structure. The second integral structure in each pixel driving circuit is spaced apart from the first integral structure.

[0098] As used herein, active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, wherein the orthographic projection of at least a portion of the semiconductor material layer on the substrate overlaps with the orthographic projection of the gate on the substrate. As used herein, a first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate overlaps with the orthographic projection of the first gate on the substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate overlaps with the orthographic projection of the second gate on the substrate. In the context of a dual-gate transistor, a first electrode refers to a component of the transistor connected to the first portion away from the third portion on one side, and a second electrode refers to a component of the transistor connected to the second portion away from the third portion on one side.

[0099] Reference Figure 2A 、 Figure 2B 、 Figure 3A as well as Figure 3DIn some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of reset control signal lines rst, a plurality of light-emitting control signal lines em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of gate lines GL, the plurality of reset control signal lines rst, the plurality of light-emitting control signal lines em, and the first capacitor electrode Ce1 are located in the same layer.

[0100] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when multiple gate lines GL and the first capacitor electrode Ce1 are formed by one or more steps of the same patterning process performed on the same layer of material, the multiple gate lines GL and the first capacitor electrode Ce1 are located in the same layer. In another example, by performing the steps of forming the multiple gate lines GL and forming the first capacitor electrode Ce1 simultaneously, the multiple gate lines GL and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0101] In some embodiments, in each pixel driving circuit, each gate line among the multiple gate lines GL includes a main portion MP extending along an extension direction of each gate line, and a gate protrusion GP protruding away from the main portion MP, for example, along a direction from each gate line among the multiple gate lines GL in each pixel driving circuit toward a corresponding reset control signal line among the multiple reset control signal lines rst in the each pixel driving circuit.

[0102] In some embodiments, as described above, the third transistor T3 is a dual-gate transistor. In some embodiments, the gate protrusion GP is one of the dual gates G3 in the third transistor T3. Figure 4A , an orthographic projection of the gate protrusion GP on the substrate BS at least partially overlaps with an orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0103] Reference Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3EIn some embodiments, the second conductive layer includes a plurality of second reset signal lines Vintr, an anti-interference block IPB, and a second capacitor electrode Ce2 of the storage capacitor Cst. The anti-interference block IPB can effectively reduce crosstalk, especially the vertical crosstalk between the N1 node and the adjacent data line. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include but are not limited to aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of second reset signal lines Vintr, the second capacitor electrode Ce2, and the anti-interference block IPB are located on the same layer.

[0104] Figure 3F , a via extending through the insulating layer IN is depicted.

[0105] Reference Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3G In some embodiments, the first signal line layer includes multiple voltage supply lines Vdd, node connection lines Cln, initialization connection lines Cli, first relay electrodes RE1, second relay electrodes RE2, multiple first reset signal lines Vintc, and multiple data lines DL. The node connection lines Cln connect the first capacitor electrode Ce1 and the first electrode of the third transistor T3 in each pixel driving circuit. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned using a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the multiple voltage supply lines Vdd, the node connection lines Cln, initialization connection lines Cli, the first relay electrode RE1, the second relay electrode RE2, multiple first reset signal lines Vintc, and multiple data lines DL are located on the same layer.

[0106] Figure 3H , a via extending through the interlayer dielectric layer ILD is depicted.

[0107] Figure 3I A via extending through the first planarization layer PLN1 is depicted in FIG.

[0108] Reference Figure 2A 、 Figure 2B 、 Figure 3A as well as Figure 3JIn some embodiments, the second signal line layer includes a first pad PAD1 and a second pad PAD2 in each pixel driving circuit. The first pad PAD1 is configured to provide a parasitic capacitance at the fourth node N4. Figure 2A and Figure 2B As shown, the fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE. The first pad PAD1 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE. Specifically, in some embodiments, the second signal line layer includes K columns of first pads, that is, each first pad in each pixel driving circuit. The K columns of first pads include a plurality of first-first pads PAD1-1 in the (2k-1)th column C(2k-1) among the K columns and a plurality of second-first pads PAD1-2 in the (2k)th column C(2k) among the K columns. The second pad PAD2 is configured to reduce crosstalk between the first node N1 and the adjacent first pads. The second pad PAD2 is connected to a corresponding voltage supply line in a plurality of voltage supply lines Vdd located in an adjacent pixel driving circuit (e.g., the pixel driving circuit on the left) through a via extending through the first planarization layer PLN1. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the first pad PAD1 (for example, a plurality of first-first pads PAD1-1 in the (2k-1)th column C(2k-1) among the K columns and a plurality of second-first pads PAD1-2 in the (2k)th column C(2k) among the K columns) and the second pad PAD2 are located on the same layer.

[0109] Figure 3K , a via extending through the second planarization layer PLN2 is depicted.

[0110] Reference Figure 2A 、 Figure 2B 、 Figure 3A as well as Figure 3LIn some embodiments, the anode connection pad includes an anode connection pad ACP in each pixel driving circuit. The anode connection pad ACP connects the anode of the light-emitting element in each pixel driving circuit to the first pad PAD1 in each pixel driving circuit. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the anode connection pad. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the anode connection pad include but are not limited to metal oxide materials, such as indium tin oxide, and metal materials, such as aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0111] Figure 3M A via extending through the third planarization layer PLN3 is depicted. Figure 3M , the corresponding positions of multiple anodes are depicted with dotted lines.

[0112] Reference Figure 2A 、 Figure 2B 、 Figure 3A as well as Figure 3N The array substrate further includes an anode layer. Each anode is connected to an anode connection pad through a corresponding via extending through the third planarization layer PLN3.

[0113] Reference Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3D 、 Figure 3E and Figure 4AIn some embodiments, except for the hole region H where a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 on the base substrate BS completely overlaps and extends beyond the orthographic projection of the first capacitor electrode Ce1 on the base substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located on the same layer as the multiple voltage supply lines Vdd. Optionally, the array substrate further includes a first via v1 located in the hole region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1. In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. Optionally, the array substrate further includes a first via v1 and a second via v2. The first via v1 is located in the hole region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the first electrode S3 of the third transistor, as shown in FIG. Figure 4A Described in.

[0114] Reference Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3E and Figure 4D In some embodiments, the interference prevention block IPB and the second capacitor electrode Ce2 are located on the same layer. Each of the multiple voltage supply lines Vdd is connected to the interference prevention block IPB via a third via v3. Optionally, the third via v3 extends through the interlayer dielectric layer ILD. Optionally, the orthographic projection of the interference prevention block IPB on the substrate substrate BS partially overlaps with the orthographic projection of each of the multiple voltage supply lines Vdd on the substrate substrate BS.

[0115] Figure 5A Shown Figure 3A The network of reset signal lines in the array substrate is depicted in FIG. Figure 5A and Figure 3AThe network of reset signal lines in the array substrate includes: a plurality of second reset signal lines Vintr extending along a first direction DR1; and a plurality of first reset signal lines Vintc extending along a second direction DR2. Each first reset signal line intersects with the plurality of second reset signal lines. Each second reset signal line intersects with the plurality of first reset signal lines. At locations where each first reset signal line intersects with the plurality of second reset signal lines, each first reset signal line is not connected to the plurality of second reset signal lines. At locations where each second reset signal line intersects with the plurality of first reset signal lines, each second reset signal line is not connected to the plurality of first reset signal lines.

[0116] Reference Figure 2A 、 Figure 2B 、 Figure 3A and Figure 4B Each of the plurality of first reset signal lines Vintc is connected to the first electrode S1 of the first transistor T1 through a fourth via v4 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI to provide an initialization signal to the first electrode S1 of the first transistor T1.

[0117] Reference Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3G and Figure 4C The initialization connection line Cli is connected to the first electrode S6 of the sixth transistor T6 through a fifth via v5 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI; and is connected to each of the plurality of second reset signal lines Vintr through a sixth via v6 extending through the interlayer dielectric layer ILD and the insulating layer IN; thereby providing an initialization signal to the first electrode S6 of the sixth transistor T6.

[0118] Figure 5B Shown Figure 3A The structure of the first pad and the first reset signal line of the array substrate is depicted in FIG. Figure 5C It is along Figure 5B Cross-sectional view along line EE'. Figure 5D It is along Figure 5B Cross-sectional view along the line F-F'. Figure 5E is a stack of corresponding first-first pads and corresponding second-first pads. Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3J 、 Figure 4B as well as Figures 5A to 5EThe first pad PAD1 is configured to provide parasitic capacitance at the fourth node N4. In one example, the parasitic capacitance at the fourth node N4 is formed between the first pad PAD1 and each of the plurality of first reset signal lines Vintc. The orthographic projection of the first pad PAD1 on the base substrate BS at least partially overlaps with the orthographic projection of each of the first reset signal lines on the base substrate BS. The first pad PAD1 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0119] In some embodiments, the first pad PAD1 crosses each of the plurality of gate lines GL. Optionally, the orthographic projection of the first pad PAD1 on the base substrate BS at least partially overlaps with the orthographic projection of each of the plurality of reset control signal lines rst on the base substrate BS. Optionally, the orthographic projection of the first pad PAD1 on the base substrate BS at least partially overlaps with the orthographic projection of each of the plurality of light-emitting control signal lines em on the base substrate BS. In one example, the orthographic projection of the first pad PAD1 on the base substrate BS at least partially overlaps with the orthographic projection of each of the plurality of reset control signal lines rst on the base substrate BS, and at least partially overlaps with the orthographic projection of each of the plurality of light-emitting control signal lines em on the base substrate BS.

[0120] In some embodiments, the array substrate includes K columns of first pads, that is, each first pad in each pixel driving circuit. The K columns of first pads include a plurality of first-first pads PAD1-1 in the (2k-1)th column C(2k-1) among the K columns and a plurality of second-first pads PAD1-2 in the (2k)th column C(2k) among the K columns. The plurality of first reset signal lines Vintc include a plurality of first-first reset signal lines Vintc1 and a plurality of second-first reset signal lines Vintc2 arranged alternately. The plurality of first-first reset signal lines Vintc1 are located in the (2k-1)th column C(2k-1) among the K columns, and the plurality of second-first reset signal lines Vintc2 are located in the (2k)th column C(2k) among the K columns. Optionally, the plurality of first-first reset signal lines Vintc1 and the plurality of second-first reset signal lines Vintc2 are parallel to each other.

[0121] In some embodiments, a first parasitic capacitance between each first-first pad and each first-first reset signal line Vintc1 in the (2k-1)th column C(2k-1) of column K is different from a second parasitic capacitance between each second-first pad and each second-first reset signal line Vintc2 in the (2k)th column C(2k) of column K. Optionally, the first parasitic capacitance is greater than the second parasitic capacitance.

[0122] Optionally, the first parasitic capacitance is at least 1% greater than the second parasitic capacitance, for example, at least 2.5% greater, at least 5% greater, at least 7.5% greater, at least 10% greater, at least 12.5% ​​greater, at least 15% greater, at least 17.5% greater, at least 20% greater, at least 22.5% greater, at least 25% greater, at least 27.5% greater, at least 30% greater, at least 32.5% greater, at least 35% greater, at least 37.5% greater, or at least 40% greater. Optionally, the first parasitic capacitance is 20% greater than the second parasitic capacitance.

[0123] In some embodiments, the orthographic projections of each first-first pad and each first-first reset signal line Vintc1 in the (2k-1)th column C(2k-1) in the K column overlap in a first overlapping region having a first area, and the orthographic projections of each second-first pad and each second-first reset signal line Vintc2 in the (2k)th column C(2k) in the K column overlap in a second overlapping region having a second area, wherein the first area and the second area are different. Optionally, the first area is greater than the second area.

[0124] Alternatively, the first area is at least 1% larger than the second area, e.g., at least 2.5%, at least 5%, at least 7.5%, at least 10%, at least 12.5%, at least 15%, at least 17.5%, at least 20%, at least 22.5%, at least 25%, at least 27.5%, at least 30%, at least 32.5%, at least 35%, at least 37.5%, or at least 40%. Alternatively, the first area is 20% larger than the second area.

[0125] In some embodiments, reference Figures 5B to 5E , the first portion P1 of each first-first pad located in the first overlapping region has a first width w1 along the first direction DR1, and the second portion P2 of each second-first pad located in the second overlapping region has a second width w2 along the first direction DR1, the first width w1 and the second width w2 are different from each other, wherein a virtual line along the first direction DR1 (for example, Figure 5B A virtual line VL (intersecting the EE' line and the FF' line) in the first and second portions P1 and P2 intersects. The first direction DR1 is perpendicular to the extending direction of each first-first reset signal line Vintc1 and each second-first reset signal line Vintc2. Optionally, the first portion P1 is an elongated portion of each first-first pad located in the first overlapping region, with its longitudinal direction parallel to the second direction DR2. Optionally, the second portion P2 is an elongated portion of each second-first pad located in the second overlapping region, with its longitudinal direction parallel to the second direction DR2.

[0126] In some embodiments, the first width W1 is greater than the second width W2. Optionally, the first width W1 is at least 1% greater than the second width W2, such as at least 2.5%, at least 5%, at least 7.5%, at least 10%, at least 12.5%, at least 15%, at least 17.5%, at least 20%, at least 22.5%, at least 25%, at least 27.5%, at least 30%, at least 32.5%, at least 35%, at least 37.5%, or at least 40%. Optionally, the first width W1 is 20% greater than the second width W2.

[0127] Optionally, the first width W1 is at least 0.05 μm larger than the second width W2, for example, at least 0.1 μm larger, at least 0.15 μm larger, at least 0.2 μm larger, at least 0.25 μm larger, at least 0.3 μm larger, at least 0.35 μm larger, at least 0.4 μm larger, at least 0.45 μm larger, at least 0.5 μm larger, at least 0.55 μm larger, at least 0.6 μm larger, at least 0.65 μm larger, at least 0.7 μm larger, at least 0.75 μm larger, at least 0.8 μm larger, at least 0.85 μm larger, at least 0.9 μm larger, at least 0.95 μm larger, or at least 1 μm larger. Optionally, the first width W1 is 0.4 μm larger than the second width W2. In one example, the first width W1 is 2.4 μm and the second width W2 is 2.0 μm.

[0128] In some embodiments, reference Figures 5B to 5E Along the virtual line VL, each first-first reset signal line Vintc1 has a third width w3 along the first direction DR1, and each second-first reset signal line Vintc2 has a fourth width w4 along the first direction DR1, and the third width w3 is substantially the same as the fourth width w4. As used herein, the term "substantially the same" means that the difference between two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as not exceeding 8% of the base value, not exceeding 6% of the base value, not exceeding 4% of the base value, not exceeding 2% of the base value, not exceeding 1% of the base value, not exceeding 0.5% of the base value, not exceeding 0.1% of the base value, not exceeding 0.05% of the base value, or not exceeding 0.01% of the base value.

[0129] Optionally, the second width W2 is substantially the same as the third width W3. Optionally, the second width W2 is substantially the same as the fourth width W4.

[0130] In some embodiments, the first width W1 is greater than the third width W3. Optionally, the first width W1 is at least 1% greater than the third width W3, such as at least 2.5%, at least 5%, at least 7.5%, at least 10%, at least 12.5%, at least 15%, at least 17.5%, at least 20%, at least 22.5%, at least 25%, at least 27.5%, at least 30%, at least 32.5%, at least 35%, at least 37.5%, or at least 40%. Optionally, the first width W1 is 20% greater than the third width W3.

[0131] In some embodiments, the first width W1 is greater than the fourth width W4. Optionally, the first width W1 is at least 1% greater than the fourth width W4, such as at least 2.5%, at least 5%, at least 7.5%, at least 10%, at least 12.5%, at least 15%, at least 17.5%, at least 20%, at least 22.5%, at least 25%, at least 27.5%, at least 30%, at least 32.5%, at least 35%, at least 37.5%, or at least 40%. Optionally, the first width W1 is 20% greater than the fourth width W4.

[0132] In some embodiments, the first portion P1 of each first-first pad located in the first overlapping area has a first average width aw1 along the first direction DR1, and the second portion P2 of each second-first pad located in the second overlapping area has a second average width aw2 along the first direction DR1, and the first average width aw1 and the second average width aw2 are different from each other.

[0133] In some embodiments, the first average width aw1 is greater than the second average width aw2. Optionally, the first average width aw1 is at least 1% greater than the second average width aw2, such as at least 2.5% greater, at least 5% greater, at least 7.5% greater, at least 10% greater, at least 12.5% ​​greater, at least 15% greater, at least 17.5% greater, at least 20% greater, at least 22.5% greater, at least 25% greater, at least 27.5% greater, at least 30% greater, at least 32.5% greater, at least 35% greater, at least 37.5% greater, or at least 40% greater. Optionally, the first average width aw1 is 20% greater than the second average width aw2.

[0134] Optionally, the first average width aw1 is at least 0.05 μm greater than the second average width aw2, for example, at least 0.1 μm greater, at least 0.15 μm greater, at least 0.2 μm greater, at least 0.25 μm greater, at least 0.3 μm greater, at least 0.35 μm greater, at least 0.4 μm greater, at least 0.45 μm greater, at least 0.5 μm greater, at least 0.55 μm greater, at least 0.6 μm greater, at least 0.65 μm greater, at least 0.7 μm greater, at least 0.75 μm greater, at least 0.8 μm greater, at least 0.85 μm greater, at least 0.9 μm greater, at least 0.95 μm greater, or at least 1 μm greater. Optionally, the first average width aw1 is 0.4 μm greater than the second average width aw2. In one example, the first average width aw1 is 2.4 μm and the second average width aw2 is 2.0 μm.

[0135] In some embodiments, each first-first reset signal line Vintc1 has a third average width aw3 along the first direction DR1 , each second-first reset signal line Vintc2 has a fourth average width aw4 along the first direction DR1 , and the third average width aw3 is substantially the same as the fourth average width aw4 .

[0136] Optionally, the second average width aw2 is substantially the same as the third average width aw3. Optionally, the second average width aw2 is substantially the same as the fourth average width aw4.

[0137] In some embodiments, the first average width aw1 is greater than the third average width aw3. Optionally, the first average width aw1 is at least 1% greater than the third average width aw3, such as at least 2.5% greater, at least 5% greater, at least 7.5% greater, at least 10% greater, at least 12.5% ​​greater, at least 15% greater, at least 17.5% greater, at least 20% greater, at least 22.5% greater, at least 25% greater, at least 27.5% greater, at least 30% greater, at least 32.5% greater, at least 35% greater, at least 37.5% greater, or at least 40% greater. Optionally, the first average width aw1 is 20% greater than the third average width aw3.

[0138] In some embodiments, the first average width aw1 is greater than the fourth average width aw4. Optionally, the first average width aw1 is at least 1% greater than the fourth average width aw4, such as at least 2.5% greater, at least 5% greater, at least 7.5% greater, at least 10% greater, at least 12.5% ​​greater, at least 15% greater, at least 17.5% greater, at least 20% greater, at least 22.5% greater, at least 25% greater, at least 27.5% greater, at least 30% greater, at least 32.5% greater, at least 35% greater, at least 37.5% greater, or at least 40% greater. Optionally, the first average width aw1 is 20% greater than the fourth average width aw4.

[0139] In some embodiments, the ratio of the total number of the plurality of first-first reset signal lines Vintc1 to the total number of the plurality of first-first pads PAD1-1 is the same as the ratio of the total number of the plurality of second-first reset signal lines Vintc2 to the total number of the plurality of second-first pads PAD1-2.

[0140] Figure 5F Schematic diagram showing the structure of the first pad according to some embodiments of the present disclosure. Figure 5B and Figure 5F In some embodiments, the first pad includes a first pad portion PP1, a second pad portion PP2, and a third pad portion PP3. The first pad portion PP1 connects the second pad portion PP2 to the third pad portion PP3. The second pad portion PP2 and the third pad portion PP3 extend from the first pad portion PP1 toward the same side (e.g., toward the left). The orthographic projection of the first pad portion PP1 on the substrate at least partially overlaps with the orthographic projection of each first reset signal line on the substrate. The orthographic projection of the second pad portion PP2 on the substrate at least partially does not overlap with the orthographic projection of each first reset signal line on the substrate, for example, the orthographic projection of the second pad portion PP2 on the substrate does not overlap with the orthographic projection of each first reset signal line on the substrate. The orthographic projection of the third pad portion PP3 on the substrate at least partially does not overlap with the orthographic projection of each first reset signal line on the substrate, for example, the orthographic projection of the third pad portion PP3 on the substrate does not overlap with the orthographic projection of each first reset signal line on the substrate.

[0141] In some embodiments, the pixel driving circuit in the (2k-1)th column C(2k-1) in column K is a pixel driving circuit for driving sub-pixels of a first color and sub-pixels of a second color to emit light; and the pixel driving circuit in the (2k)th column C(2k) in column K is a pixel driving circuit for driving sub-pixels of a third color to emit light. In one example, the first color is red, the second color is blue, and the third color is green.

[0142] In related array substrates, green sub-pixels typically take longer to light up than red and blue sub-pixels, especially when displaying images with lower grayscale, which results in a red streaking defect in the related array substrates. In the present array substrate, the parasitic capacitance of the pixel driving circuit in the (2k-1)th column C(2k-1) in the K column at the fourth node N4 is greater than the parasitic capacitance of the pixel driving circuit in the (2k)th column C(2k) in the K column at the fourth node N4. Therefore, the higher parasitic capacitance at the fourth node N4 reduces the lighting speed of the red and blue sub-pixels compared to the green sub-pixels. The inventors of the present disclosure surprisingly and unexpectedly discovered that the fine structure of the present array substrate achieves similar lighting speeds in the green, red, and blue sub-pixels, eliminating the problem of the red streaking defect in the related array substrates.

[0143] As previously described, the second pad PAD2 is configured to reduce crosstalk between the first node N1 and the adjacent first pad. Figure 4D The second pad PAD2 is connected to a corresponding voltage supply line in an adjacent pixel driving circuit among the plurality of voltage supply lines Vdd through a seventh via v7 extending through the first planarization layer PLN1. Each of the plurality of voltage supply lines Vdd is connected to the second capacitor electrode Ce2 through an eighth via v8 extending through the interlayer dielectric layer ILD. Figure 6A 1 shows the structure of the first signal line layer and the second signal line layer according to some embodiments of the present disclosure. Figure 6A and Figure 4A As shown, in some embodiments, the orthographic projection of the second pad PAD2 in each pixel driving circuit on the substrate substrate BS covers at least 50% (e.g., at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the node connection line Cln in each pixel driving circuit on the substrate substrate BS. In some embodiments, the orthographic projection of the second pad PAD2 in each pixel driving circuit on the substrate substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate substrate BS. In some embodiments, the orthographic projection of the second pad PAD2 in each pixel driving circuit on the substrate substrate BS covers at least 50% (e.g., at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 99%, or 100%) of the orthographic projection of the gate protrusion GP of each gate line among the plurality of gate lines GL on the substrate substrate BS.

[0144] Figure 6B Schematic diagram showing the structure of the second pad according to some embodiments of the present disclosure. Figure 6B In some embodiments, the second pad includes a fourth pad portion PP4, a fifth pad portion PP5, and a sixth pad portion PP6. The fifth pad portion PP5 connects the fourth pad portion PP4 to the sixth pad portion PP6. Figure 3A 、 Figure 4D 、 Figure 6A and Figure 6B The orthographic projection of the fourth pad portion PP4 on the base substrate BS at least partially overlaps with the orthographic projection of the node connection line Cln in each pixel drive circuit on the base substrate BS, and at least partially overlaps with the orthographic projection of the gate protrusion GP of each gate line in the plurality of gate lines GL on the base substrate BS. The orthographic projection of the sixth pad portion PP6 on the base substrate BS at least partially overlaps with the orthographic projection of a corresponding voltage supply line in the plurality of voltage supply lines Vdd located in the adjacent pixel drive circuit on the base substrate BS. The fifth pad portion PP5 intersects with a corresponding data line in the plurality of data lines DL located in the adjacent pixel drive circuit. The adjacent pixel drive circuits and the corresponding pixel drive circuit are located in the same row along the first direction DR1.

[0145] Reference Figure 3A and Figure 4B , the first pad PAD1 is connected to the first relay electrode RE1 in the first signal line layer SL1 through a ninth via v9 extending through the first planarization layer PLN1, and is connected to the second relay electrode RE2 in the first signal line layer SL1 through a tenth via v10 extending through the first planarization layer PLN1. The first relay electrode RE1 is connected to the second electrode D5 of the fifth transistor T5 through an eleventh via v11 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The second relay electrode RE2 is connected to the second electrode D6 of the sixth transistor T6 through a twelfth via v12 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The anode connection pad ACP is connected to the first pad PAD1 through a thirteenth via v13 extending through the second planarization layer PLN2. The anode AD is connected to the anode connection pad ACP through a fourteenth via v14 extending through the third planarization layer PLN3.

[0146] Figure 7 Schematic diagram showing the display area and the peripheral area in the array substrate according to some embodiments of the present disclosure. Figure 7In some embodiments, the array substrate includes a display area DA and a peripheral area PA. In some embodiments, the peripheral area PA includes a first sub-area PA1 located on a first side S1 of the display area DA, a second sub-area PA2 located on a second side S2 of the display area DA, a third sub-area PA3 located on a third side S3 of the display area DA, and a fourth sub-area PA4 located on a fourth side S4 of the display area DA. Optionally, the first side S1 and the third side S3 are opposite to each other. Optionally, the second side S2 and the fourth side S4 are opposite to each other. Optionally, the first sub-area PA1 is the sub-area of ​​the array substrate where signal lines are connected to the integrated circuit.

[0147] As used herein, the term "display area" refers to the area of ​​the array substrate that actually displays the image. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in a liquid crystal display or the area corresponding to the light-emitting layer in an organic light-emitting diode display panel. The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in a liquid crystal display or the area corresponding to the pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas from two adjacent pixels.

[0148] As used herein, the term "peripheral region" refers to the region of an array substrate in a display panel where various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of a display device having an array substrate, opaque or light-impermeable components of the display device (e.g., a battery, a printed circuit board, a metal frame) may be disposed in the peripheral region rather than the display region.

[0149] In some embodiments, the first sub-region PA1 includes a side region SR and one or more corner regions (e.g., a first corner region CR1 and a second corner region CR2). The one or more corner regions are respectively located at the corners of the display panel. The one or more corner regions respectively connect the side region SR to one or more adjacent sub-regions of the peripheral region PA. For example, the first corner region CR1 connects the side region SR to the second sub-region PA2, and the second corner region CR2 connects the side region SR to the fourth sub-region PA4.

[0150] Figure 8 Schematic diagram showing a display area and a peripheral area in an array substrate according to some embodiments of the present disclosure. Figure 8 In some embodiments, the array substrate has an additional display area ADA in addition to the display area DA. Figure 8 and Figure 7 In contrast, in some embodiments, the additional display area ADA extends away from the display area DA to Figure 7 In the side area SR, the side area is reduced.

[0151] In some embodiments, the pixel driving circuit is provided in the display area DA. However, the light emitting layers corresponding to the plurality of pixel driving circuits along the boundary between the display area DA and the additional display area ADA are provided in the additional display area ADA. Because these driving circuits are provided in the display area DA and the corresponding light emitting layers are provided in the additional display area ADA, the plurality of anode connection pads (e.g., Figure 3L The ACP depicted in FIG) extends from the display area DA into the additional display area ADA. Figure 9 1 shows the arrangement of the pixel driving circuit and the light emitting layer in the area around the boundary between the display area and the additional display area in some embodiments according to the present disclosure. Figure 9 A plurality of anode connection pads ACP connecting each pixel driving circuit PDC and each light emitting layer EL extend from the display area DA to the additional display area ADA. The additional display area ADA does not have a pixel driving circuit but includes other components such as power lines.

[0152] Figure 10 1 shows the arrangement of the pixel driving circuit and the light emitting layer in the area around the boundary between the display area and the additional display area in some embodiments according to the present disclosure. Figure 10 Since the light emitting layer corresponding to the pixel driving circuit in the display area DA is provided in the additional display area ADA, this area can be the light emitting layer receiving the light from the pixel driving circuit of the previous row (in Figure 10 Indicated in the figure provides space for PEL).

[0153] Figure 11A The structures of various pixel driving circuits and various light-emitting elements in some embodiments of the present disclosure are shown. Figure 11B Shown Figure 11A The structure of the semiconductor material layer in the array substrate is depicted in FIG. Figure 11C Shown Figure 11A The structure of the first conductive layer in the array substrate is depicted in FIG. Figure 11D Shown Figure 11A The structure of the insulating layer in the array substrate is depicted in FIG. Figure 11E Shown Figure 11A The structure of the second conductive layer in the array substrate is depicted in FIG. Figure 11F Shown Figure 11A The structure of the first signal line layer in the array substrate is depicted in FIG. Figure 11G Shown Figure 11A The structure of the second signal line layer in the array substrate is depicted in FIG. Figure 11H Shown Figure 11A The structure of the third signal line layer in the array substrate is depicted in FIG. Figure 11I Shown Figure 11A The structure of the anode layer in the array substrate is depicted in FIG. Figure 11J Shown Figure 11A The structure of the pixel defining layer in the array substrate is depicted in FIG. Figure 11K Shown Figure 11A The structure of the light-emitting layer in the array substrate is depicted in FIG. Figure 12A It is along Figure 11A Cross-sectional view along line G-G'. Figure 12B It is along Figure 11A Cross-sectional view along the H-H' line.

[0154] Reference Figures 11A to 11K 、 Figure 12A and Figure 12B In some embodiments, the array substrate includes a base substrate BS, a semiconductor material layer SML located on the base substrate BS, a gate insulating layer GI located on a side of the semiconductor material layer SML away from the base substrate BS, a first conductive layer Gate1 located on a side of the gate insulating layer GI away from the semiconductor material layer SML, an insulating layer IN located on a side of the first conductive layer away from the gate insulating layer GI, a second conductive layer Gate2 located on a side of the insulating layer IN away from the first conductive layer Gate1, an interlayer dielectric layer ILD located on a side of the second conductive layer Gate2 away from the insulating layer IN, a first signal line layer SLL1 located on a side of the interlayer dielectric layer ILD away from the second conductive layer Gate2, and a first plane dielectric layer SLL1 located on a side of the first signal line layer SLL1 away from the interlayer dielectric layer ILD. A planarization layer PLN1, a second signal line layer SLL2 located on a side of the first planarization layer PLN1 away from the first signal line layer SLL1, a second planarization layer PLN2 located on a side of the second signal line layer SLL2 away from the first planarization layer PLN1, an anode connection pad layer ACPL located on a side of the second planarization layer PLN2 away from the second signal line layer SLL2, a third planarization layer PLN3 located on a side of the anode connection pad layer ACPL away from the second planarization layer PLN2, an anode layer ADL located on a side of the third planarization layer PLN3 away from the anode connection pad layer ACPL, a pixel defining layer PDL located on a side of the anode layer ADL away from the third planarization layer PLN3, and a light-emitting layer EML located on a side of the pixel defining layer PDL away from the anode layer ADL.

[0155] Reference Figures 11A to 11KIn some embodiments, the semiconductor material layer SML includes active layers of transistors, including the active layers of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor Td. Various suitable semiconductor materials can be used to manufacture the semiconductor material layer SML. Examples of suitable semiconductor materials for manufacturing the semiconductor material layer SML include polycrystalline silicon, amorphous silicon, and metal oxides.

[0156] In some embodiments, the first conductive layer Gate1 includes a plurality of gate lines GL, a plurality of reset control signal lines rst, a plurality of light emission control signal lines em, and a first capacitor electrode Ce1 of the storage capacitor Cst.

[0157] Figure 11D , a via extending through the insulating layer IN is depicted.

[0158] In some embodiments, the second conductive layer Gate2 includes an anti-interference block IPB, a second capacitor electrode Ce2 of the storage capacitor Cst, and a plurality of first reset signal lines Vintr. The anti-interference block IPB can effectively reduce crosstalk, especially vertical crosstalk between the N1 node and adjacent data lines.

[0159] In some embodiments, the first signal line layer SLL1 includes multiple voltage supply lines Vdd, node connection lines Cln, multiple second reset signal lines Vintc, and multiple data lines DL. The node connection lines Cln connect the first capacitor electrode Ce1 and the drain of the third transistor T3 in each pixel driving circuit. The array substrate also includes a first via v1 located in the hole region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1. In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. Optionally, the array substrate also includes a second via v2. The first via v1 is located in the hole region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1 and to the semiconductor material layer SML through the second via v2. Optionally, the node connection line Cln is connected to the drain D3 of the third transistor, as shown in FIG. Figure 12A Depicted.

[0160] In some embodiments, the second signal line layer SLL2 includes a connection pad CP, through which the N4 node is electrically connected to the anode of each light-emitting element. Optionally, the array substrate further includes a third via v3 extending through the first planarization layer PLN1, the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. The connection pad CP is connected to the N4 node through the third via v3.

[0161] In some embodiments, the anode connection pad layer ACPL includes a plurality of anode connection pads ACP. Each of the plurality of anode connection pads ACP electrically connects the connection pad CP to the anode of each light-emitting element. Optionally, the array substrate further includes a fourth via v4 extending through the second planarization layer PLN2. Each of the plurality of anode connection pads ACP is connected to the connection pad CP through the fourth via v4. Various suitable conductive materials can be used to manufacture the plurality of anode connection pads ACP. Examples of suitable conductive materials for manufacturing the plurality of anode connection pads ACP include conductive metal oxides, such as indium tin oxide.

[0162] The anode layer includes a plurality of anodes AD of the plurality of light-emitting elements. Each of the plurality of anodes AD is connected to a respective connection line. Optionally, the array substrate further includes a fifth via v5 extending through the third planarization layer PLN3. Each anode is connected to a respective connection line through the fifth via v5.

[0163] The pixel defining layer PDL defines a plurality of sub-pixel openings SA.

[0164] In some embodiments, the organic layer OL includes a plurality of light emitting layers EML of a plurality of light emitting elements, and each of the plurality of light emitting layers EML is electrically connected to each of the plurality of anodes AD.

[0165] The plurality of anode connection pads (ACP) may be disposed in various suitable layers. In some embodiments, the plurality of anode connection pads (ACP) are all located in the same layer. In some embodiments, the plurality of anode connection pads (ACP) may be disposed in multiple layers. In one example, two adjacent anode connection pads extending substantially along a column direction may be disposed in two different layers, respectively.

[0166] In one example, a plurality of anode connection pads ACP are located in the anode connection pad layer ACPL; the second planarization layer PLN2 is located on the side of the anode connection pad layer ACPL close to the substrate BS; the third planarization layer PLN3 is located on the side of the anode connection pad layer ACPL away from the substrate BS; the anode layer ADL is located on the side of the third planarization layer PLN3 away from the anode connection pad layer ACPL; and a plurality of pixel driving circuits PDC are located on the side of the second planarization layer PLN2 away from the anode connection pad layer ACPL.

[0167] Figure 13AThe structure in the second region of the array substrate according to some embodiments of the present disclosure is shown. Figure 13B Shown Figure 13A The structure of the pixel driving circuit in FIG. Figure 13C Shown Figure 13A The structure of the connecting lines in . Figure 13D Shown Figure 13A The structure of the light emitting element in 13A to 13D In the additional display area ADA, some of the plurality of light-emitting elements LE are present, and the plurality of transistors and capacitors of the pixel drive circuit PDC are absent. Alternatively, in the additional display area ADA, at least one row of light-emitting elements is present, and the plurality of transistors and capacitors of the pixel drive circuit PDC are absent. Alternatively, in the display area DA, multiple rows of light-emitting elements and multiple rows of transistors and capacitors of the pixel drive circuit are present.

[0168] In some embodiments, a plurality of anode connection pads ACP respectively connect a plurality of pixel driving circuits PDC with a plurality of corresponding light emitting elements, and a corresponding anode connection pad RACP connects a corresponding pixel driving circuit RPDC with a corresponding light emitting element RLE.

[0169] Figure 14 The structure of the anode connection pad layer, the anode layer and the light emitting layer in some embodiments of the present disclosure is shown. Figure 14 In some embodiments, the anode connection pad layer includes a plurality of anode connection pads ACP, the anode layer includes a plurality of anodes AD, and the light emitting layer includes a plurality of light emitting blocks EMB. Figure 14 The layout of multiple anode connection pads (ACP), multiple anodes (AD), and multiple light-emitting blocks (EMB) in the additional display area is depicted. In some embodiments, the multiple subpixels include respective first subpixels (sp1), respective second subpixels (sp2), respective third subpixels (sp3), and respective fourth subpixels (sp4). Optionally, each pixel of the array substrate includes a corresponding first subpixel (sp1), a corresponding second subpixel (sp2), a corresponding third subpixel (sp3), and a corresponding fourth subpixel (sp4). In one example, each first subpixel (sp1) is a red subpixel, each second subpixel (sp2) is a green subpixel, each third subpixel (sp3) is a blue subpixel, and each fourth subpixel (sp4) is a green subpixel.

[0170] In some embodiments, the orthographic projections of the multiple anode connection pads ACP on the substrate partially overlap with the orthographic projections of the respective first sub-pixels sp1 on the substrate, forming a first overlapping area; the orthographic projections of the multiple anode connection pads ACP on the substrate partially overlap with the orthographic projections of the respective second sub-pixels sp2 on the substrate, forming a second overlapping area; the orthographic projections of the multiple anode connection pads ACP on the substrate partially overlap with the orthographic projections of the respective third sub-pixels sp3 on the substrate, forming a third overlapping area; or, the orthographic projections of the multiple anode connection pads ACP on the substrate partially overlap with the orthographic projections of the respective fourth sub-pixels sp4 on the substrate, forming a fourth overlapping area. Optionally, the first overlapping area is larger than the second overlapping area, for example, at least 1% larger, at least 2.5% larger, at least 5% larger, at least 7.5% larger, at least 10% larger, at least 12.5% ​​larger, at least 15% larger, at least 17.5% larger, at least 20% larger, at least 22.5% larger, at least 25% larger, at least 27.5% larger, at least 30% larger, at least 32.5% larger, at least 35% larger, at least 37.5% larger, or at least 40% larger.

[0171] Optionally, the first overlapping area is larger than the fourth overlapping area, for example, at least 1% larger, at least 2.5% larger, at least 5% larger, at least 7.5% larger, at least 10% larger, at least 12.5% ​​larger, at least 15% larger, at least 17.5% larger, at least 20% larger, at least 22.5% larger, at least 25% larger, at least 27.5% larger, at least 30% larger, at least 32.5% larger, at least 35% larger, at least 37.5% larger, or at least 40% larger.

[0172] Optionally, the third overlapping area is larger than the second overlapping area, for example, at least 1% larger, at least 2.5% larger, at least 5% larger, at least 7.5% larger, at least 10% larger, at least 12.5% ​​larger, at least 15% larger, at least 17.5% larger, at least 20% larger, at least 22.5% larger, at least 25% larger, at least 27.5% larger, at least 30% larger, at least 32.5% larger, at least 35% larger, at least 37.5% larger, or at least 40% larger.

[0173] Optionally, the third overlapping area is larger than the fourth overlapping area, for example, at least 1% larger, at least 2.5% larger, at least 5% larger, at least 7.5% larger, at least 10% larger, at least 12.5% ​​larger, at least 15% larger, at least 17.5% larger, at least 20% larger, at least 22.5% larger, at least 25% larger, at least 27.5% larger, at least 30% larger, at least 32.5% larger, at least 35% larger, at least 37.5% larger, or at least 40% larger.

[0174] In one example, each first subpixel sp1 is a red subpixel, each second subpixel sp2 is a green subpixel, each third subpixel sp3 is a blue subpixel, and each fourth subpixel sp4 is a green subpixel. In related array substrates, green subpixels typically take longer to light up than red and blue subpixels, particularly when displaying images at lower grayscales, resulting in a red streaking defect in related array substrates. In at least the additional display area of ​​this array substrate, the parasitic capacitance of the pixel driver circuits in the red and blue subpixels is greater than the parasitic capacitance of the pixel driver circuit in the green subpixel. Therefore, the higher parasitic capacitance reduces the lighting speed of the red and blue subpixels compared to the green subpixels. The inventors of the present disclosure surprisingly and unexpectedly discovered that the fine structure of this array substrate achieves similar lighting speeds for the green, red, and blue subpixels, eliminating the red streaking defect in related array substrates.

[0175] In another aspect, the present invention provides a display device comprising an array substrate as described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS devices, and the like. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0176] On the other hand, the present invention provides a method for manufacturing an array substrate. In some embodiments, the method includes forming K columns of first pads. Optionally, each first pad is formed to be connected to an anode of a light-emitting element, a second electrode of a fifth transistor, and a second electrode of a sixth transistor. Optionally, forming K columns of first pads includes forming a plurality of first-first pads in a (2k-1)th column of the K columns and forming a plurality of second-first pads in a (2k)th column of the K columns. Optionally, each first-first pad and each second-first pad are formed to have different average line widths.

[0177] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be regarded as illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode practical application, thereby enabling those skilled in the art to understand the invention in various embodiments and with various modifications as are suited to a particular use or implementation contemplated. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are to be used in their broadest reasonable sense unless otherwise indicated. Therefore, the terms "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention are not intended to limit the invention, and no such limitation should be inferred. The present invention is to be limited only by the spirit and scope of the appended claims. Furthermore, the claims may use the terms "first," "second," etc., followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements to which they refer unless a specific number is provided. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, no element or component in this disclosure is intended to be dedicated to the public, regardless of whether the element or component is explicitly stated in the appended claims.

Claims

1. An array substrate, comprising: a display area, an additional display area, a peripheral area, K columns of first pads, a plurality of first-first reset signal lines located in a (2k-1)th column among the K columns, and a plurality of second-first reset signal lines located in a (2k)th column among the K columns; wherein each first pad is connected to the anode of the light emitting element, the second electrode of the fifth transistor, and the second electrode of the sixth transistor; The K columns of first pads include a plurality of first-first pads located in a (2k-1)th column among the K columns and a plurality of second-first pads located in a (2k)th column among the K columns; Each of the first-first pads and each of the second-first pads has a different average line width; a first parasitic capacitance between each first-first pad in the (2k-1)th column among the K columns and the corresponding first reset signal line is different from a second parasitic capacitance between each second-first pad in the (2k)th column among the K columns and the corresponding second-first reset signal line; The additional display area extends away from the display area to a side area of ​​the peripheral area; The array substrate includes a plurality of light-emitting elements and a plurality of pixel driving circuits; The plurality of pixel driving circuits are located in the display area; A portion of the plurality of light emitting elements exists in the additional display area; and The transistors and capacitors of the plurality of pixel driving circuits are not present in the additional display area.

2. The array substrate according to claim 1, wherein: The first parasitic capacitance is at least 5% greater than the second parasitic capacitance.

3. The array substrate according to claim 1, wherein: The respective first-first pads located in the (2k-1)th column among the K columns and orthographic projections of the corresponding first-first reset signal lines overlap with each other in a first overlapping region having a first area; orthographic projections of the respective second-first pads and the corresponding second-first reset signal lines located in the (2k)th column among the K columns overlap with each other in a second overlapping region having a second area; as well as The first area and the second area are different from each other.

4. The array substrate according to claim 3, wherein: The first area is at least 5% larger than the second area.

5. The array substrate according to claim 3, wherein: a first portion of each of the first-first pads located in the first overlapping region having a first width along a first direction; a second portion of each of the second-first pads located in the second overlapping region having a second width along the first direction; as well as The first width is greater than the second width.

6. The array substrate according to claim 5, wherein: The first width is at least 5% greater than the second width.

7. The array substrate according to claim 5, wherein: A virtual line passes through the first portion and the second portion; along the virtual line, the first-first reset signal lines have a third width, and the second-first reset signal lines have a fourth width; The third width is substantially the same as the fourth width; and The first width is greater than the third width and greater than the fourth width.

8. The array substrate according to any one of claims 1 to 7, wherein: A ratio of a total number of the plurality of first-first reset signal lines to a total number of the plurality of first-first pads is the same as a ratio of a total number of the plurality of second-first reset signal lines to a total number of the plurality of second-first pads.

9. The array substrate according to any one of claims 1 to 7, further comprising a plurality of gate lines; in, Each of the first pads crosses a corresponding gate line among the plurality of gate lines.

10. The array substrate according to claim 9, further comprising a plurality of reset control signal lines and a plurality of light emitting control signal lines; in, An orthographic projection of each first pad on the base substrate at least partially overlaps with an orthographic projection of a corresponding reset control signal line among the plurality of reset control signal lines on the base substrate; or An orthographic projection of the first pad on the base substrate at least partially overlaps with an orthographic projection of a corresponding light emitting control signal line among the plurality of light emitting control signal lines on the base substrate.

11. The array substrate according to any one of claims 1 to 7, further comprising a plurality of voltage supply lines; in, Each pixel driving circuit includes: Second pad; Node connecting lines; and a storage capacitor comprising a first capacitor electrode; wherein the second pad is connected to a corresponding voltage supply line among the plurality of voltage supply lines; The node connection line connects the first capacitor electrode in each pixel driving circuit to the first electrode of the third transistor; and The orthographic projection of the second pad on the base substrate covers at least 50% of the orthographic projection of the node connection line on the base substrate.

12. The array substrate according to claim 11, wherein: An orthographic projection of the second pad on the base substrate at least partially overlaps with an orthographic projection of the active layer of the third transistor on the base substrate.

13. The array substrate according to claim 11, further comprising a plurality of gate lines; in, Each of the plurality of gate lines comprises a main portion extending along an extension direction of the respective gate line and a gate protrusion protruding away from the main portion; as well as An orthographic projection of the second pad on the base substrate covers at least 50% of an orthographic projection of the gate protrusion on the base substrate.

14. The array substrate according to claim 11, further comprising a plurality of data lines; in, the second pad comprising a fourth pad portion, a fifth pad portion, and a sixth pad portion, the fifth pad portion connecting the fourth pad portion to the sixth pad portion; as well as The fifth pad portion crosses a corresponding data line among the plurality of data lines located in an adjacent pixel driving circuit, wherein the adjacent pixel driving circuit and the respective pixel driving circuit are in a same row along the first direction.

15. The array substrate according to claim 14, wherein: The orthographic projection of the fourth pad portion on the base substrate at least partially overlaps with the orthographic projection of the node connection line in each pixel driving circuit on the base substrate; as well as An orthographic projection of the sixth pad portion on the base substrate at least partially overlaps with an orthographic projection of a corresponding adjacent voltage supply line among the plurality of voltage supply lines located in the adjacent pixel driving circuit on the base substrate.

16. The array substrate according to any one of claims 1 to 7, further comprising an anode connection pad and an anode; in, Each of the first pads is connected to the first relay electrode through a ninth via hole extending through the first planarization layer, and is connected to the second relay electrode through a tenth via hole extending through the first planarization layer; The first relay electrode is connected to the second electrode of the fifth transistor through an eleventh via extending through at least the interlayer dielectric layer; The second relay electrode is connected to the second electrode of the sixth transistor through a twelfth via extending through at least the interlayer dielectric layer; The anode connection pad is connected to each of the first pads through a thirteenth via extending through the second planarization layer; as well as The anode is connected to the anode connection pad through a fourteenth via extending through the third planarization layer.

17. The array substrate according to any one of claims 1 to 7, further comprising a plurality of second reset signal lines located in a different layer from the plurality of first-first reset signal lines and the plurality of second-first reset signal lines; in, The plurality of second reset signal lines extend along the first direction; The plurality of first-first reset signal lines and the plurality of second-first reset signal lines extend along a second direction; Each second reset signal line is configured to provide an initialization signal to a first electrode of a sixth transistor in each pixel driving circuit; Each first-first reset signal line is configured to provide an initialization signal to a first electrode of a first transistor in a first-first corresponding pixel driving circuit located in the (2k-1)th column; as well as Each of the second-first reset signal lines is configured to provide an initialization signal to a first electrode of a first transistor in a second-first corresponding pixel driving circuit located in the (2k)th column.

18. The array substrate according to any one of claims 1 to 7, wherein: The pixel driving circuit located in the (2k-1)th column among the K columns is a pixel driving circuit for driving sub-pixels of the first color and sub-pixels of the second color to emit light; The pixel driving circuit located in the (2k)th column among the K columns is a pixel driving circuit for driving sub-pixels of a third color to emit light; as well as The first color, the second color, and the third color are different from each other.

19. The array substrate according to any one of claims 1 to 7, wherein: A light emitting layer corresponding to a plurality of pixel driving circuits along a boundary between the display area and the additional display area is located in the additional display area; The array substrate further includes a plurality of anode connection pads connecting the pixel driving circuit along the boundary between the display area and the additional display area to the light emitting layer located in the additional display area; and Each of the plurality of anode connection pads electrically connects the second electrode of the sixth transistor to an anode of a corresponding light emitting element located in the additional display area.

20. The array substrate according to claim 19, wherein: In the additional display area, The orthographic projections of the plurality of anode connection pads on the base substrate partially overlap with the orthographic projections of the first sub-pixels on the base substrate to form a first overlapping area; The orthographic projections of the plurality of anode connection pads on the base substrate partially overlap with the orthographic projections of the second sub-pixels on the base substrate to form a second overlapping area; The orthographic projections of the plurality of anode connection pads on the base substrate partially overlap with the orthographic projections of the third sub-pixels on the base substrate to form a third overlapping area; The first overlapping area is larger than the second overlapping area; The third overlapping area is larger than the second overlapping area; and The first sub-pixels, the second sub-pixels, and the third sub-pixels are sub-pixels of different colors. 21 . A display device comprising the array substrate according to claim 1 and an integrated circuit connected to the array substrate.

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