A switching noise suppression circuit and a switching noise suppression method

Abstract

The embodiment of the present application provides a switching noise suppression circuit and a switching noise suppression method, including: an inverting circuit combination, used to drive the power tube to be adjusted to turn off or on according to the input duty cycle signal, and used to output the logic control of the control circuit; a sampling circuit, used to collect the gate voltage change of the power tube to be adjusted; a current generating circuit, a user generates current according to the voltage change; a current injection circuit, used to inject the current into the gate of the power tube to be adjusted to slow down the opening speed of the power tube to be adjusted; a control circuit, used to control the drain of the power tube to be adjusted and the current generating circuit to cut off and conduct according to the output logic. The present application slows down the opening rate of the power tube to be adjusted by injecting current at the moment when the power tube to be adjusted is turned on, thereby achieving the purpose of suppressing switching noise.

Description

Technical Field

[0001] The embodiments of the present application belong to the technical field of noise suppression, and in particular, relate to a switching noise suppression circuit and a switching noise suppression method. Background Art

[0002] DC-DC power converters are widely used in various electronic devices due to their high efficiency, low power consumption, and flexible control of output voltage. Among them, the DC-DC buck converter (abbreviated as BUCK) is a type of switching power supply that is widely used in portable devices and consumer electronics and is gradually replacing linear regulators. BUCK converters need to provide stable and efficient power for other electronic devices or circuit systems, provided that the converter itself is kept in a stable and reliable working state as much as possible. Due to the presence of parasitic inductance, noise will be generated during the start-up process of the BUCK circuit. The instantaneous voltage of the noise voltage is high, which seriously affects the reliability of the circuit operation and generates a large amount of electromagnetic interference. Therefore, a switching noise suppression circuit is required. Summary of the invention

[0003] In order to solve or alleviate the problems in the prior art, in a first aspect, the present application provides a switching noise suppression circuit, including:

[0004] An inverting circuit combination, used to drive the power tube to be regulated to turn off or on according to the input duty cycle signal, and to output logic control of the control circuit;

[0005] A sampling circuit is used to collect the gate voltage variation of the power tube to be adjusted;

[0006] A current generating circuit, wherein the user generates current according to the voltage variation;

[0007] A current injection circuit, used for injecting the current into the gate of the power tube to be regulated to slow down the turn-on speed of the power tube to be regulated;

[0008] The control circuit is used to control the drain of the power tube to be regulated and the current generating circuit to be disconnected and connected according to the output logic.

[0009] Compared with the prior art, the embodiment of the present application provides a switching noise suppression circuit, which slows down the turn-on rate of the power tube to be regulated by injecting current at the moment when the power tube to be regulated is turned on, thereby achieving the purpose of suppressing switching noise.

[0010] In a second aspect, an embodiment of the present application provides a BUCK circuit, comprising the switching noise suppression circuit described in any one of the first aspect.

[0011] In a third aspect, an embodiment of the present application provides a switching noise suppression method, which is implemented by the circuit described in any one of the first aspects, including:

[0012] When the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are turned on and the sixth PMOS tube is turned off by the duty cycle control signal, the current generating circuit generates a current and injects the current into the gate of the power tube to be regulated, so as to slow down the speed of reducing the gate voltage of the power tube to be regulated, thereby controlling the turn-on rate of the power tube to be regulated;

[0013] When the fifth PMOS tube, the fourth PMOS tube and the third PMOS tube are turned off by the duty cycle control signal and the sixth PMOS tube is turned on, the current generating circuit is cut off and does not generate current, and does not control the power tube to be regulated.

[0014] Compared with the prior art, the beneficial effects of the technical solutions provided by the second and third aspects are the same as the beneficial effects of the circuit provided by the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. Some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0016] Figure 1 is a structural schematic diagram of a switching noise suppression circuit provided in an embodiment of the present application;

[0017] Figure 2 is a structural schematic diagram of a switching noise suppression circuit provided in an embodiment of the present application;

[0018] Figure 3 It is a structural schematic diagram of a BUCK circuit with a switching noise suppression circuit provided by an embodiment of the present application;

[0019] Figure 4 This is a diagram showing the changing state of the source current of the upper power tube during the turn-on process of the switching noise suppression circuit provided by the embodiment of the present application;

[0020] Figure 5 and Figure 6 This is a diagram of the switching noise change state on VDD and VSS under the action of the switching noise suppression circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0022] This application provides a new switching noise suppression circuit solution, which reduces the noise voltage generated by parasitic inductance during the switching process of the BUCK converter. Compared with the general solution of using gate series resistance, this method has better noise suppression effect and less power loss. This solution is based on slowing down the change rate of the power tube source current by injecting current into the power tube gate, thereby achieving the purpose of noise suppression. The circuit structure is simple, robust, and easy to implement. Figure 1 As shown, an embodiment of the present application provides a switching noise suppression circuit, including:

[0023] The inverter circuit combination 01 is used to drive the power tube to be adjusted to turn off or on according to the input duty cycle signal, and to output the logic control of the control circuit;

[0024] The sampling circuit 02 is used to collect the gate voltage variation of the power tube 03 to be adjusted;

[0025] A current generating circuit 05, wherein the user generates current according to the voltage variation;

[0026] The current injection circuit 06 is used to inject the current into the gate of the power tube 03 to be regulated to slow down the turn-on speed of the power tube 03 to be regulated;

[0027] The control circuit 04 is used to control the drain of the power tube to be regulated 03 and the current generating circuit 05 to be disconnected and connected according to the output logic.

[0028] It should be noted that the power tube to be adjusted is the upper power tube of the BUCK.

[0029] The present application provides a switching noise suppression circuit, which slows down the rate of turning on the upper power tube and reduces the rate of change of the current flowing through the parasitic inductor by injecting current at the moment when the upper power tube of the BUCK circuit is turned on, thereby achieving the purpose of suppressing the switching noise. The working process of the switching noise suppression circuit of the present application is divided into three stages. In stage one, the lower power tube of the BUCK circuit is turned on and the upper power tube is turned off. At this time, the switching noise suppression circuit is also in a closed state and does not work. In stage two, the lower power tube of the BUCK circuit is turned off, and the moment the upper power tube is turned on, the switching noise suppression circuit is turned on under the control of the duty cycle control signal, and injects current into the gate of the upper power tube to reduce the current flowing out through the gate of the upper power tube, and slows down the rate of turning on the upper power tube before the end stage of the Miller platform. In stage three, when the gate voltage of the upper power tube crosses the Miller platform, the switching noise suppression circuit is automatically turned off, and no current is injected into the gate of the upper power tube, so the upper power tube completes the remaining opening process, avoiding the problem of power consumption loss due to too long opening time. The switching noise suppression circuit described in the present application can achieve a good noise suppression effect while controlling the power tube startup process in stages. Before the Miller platform, the upper power tube is slowly turned on to reduce noise; after the Miller platform, the upper power tube quickly reaches the final startup state to reduce power consumption loss. The noise suppression circuit itself has a simple structure and is easy to implement.

[0030] like Figure 2 As shown, the inverting circuit combination includes a first inverting circuit 01-1 and a second inverting circuit 01-2 which are sequentially connected to each other;

[0031] The input end of the first inverter circuit 01-1 receives a duty cycle control signal, the output end of the second inverter circuit 01-2 is connected to the gate of the power tube to be adjusted, and the sampling circuit is connected to a first common end connected to the output end of the second inverter circuit 01-2 and the gate of the power tube to be adjusted.

[0032] It should be noted that, in the embodiments of the present application, an example of combining an inverting circuit into two inverting circuits is mainly introduced to explain the inventive concept of the present application in detail, but the present application is not limited to two inverting circuits. In the embodiments of the present application, the inverting circuit combination requires at least two inverting circuits. The upper power tube P1 of the BUCK circuit can be controlled by the inverting circuit combination, and the control circuit can also be controlled by the inverting circuit combination. The upper power tube P1 of the BUCK circuit in the present application adopts a PMOS tube, and the lower power tube N1 adopts an NMOS tube.

[0033] Specifically, the first inverter circuit 01 - 1 includes a first NMOS transistor N2 and a first PMOS transistor P2, and the second inverter circuit 01 - 2 includes a second NMOS transistor N3 and a second PMOS transistor P3;

[0034] The source of the first PMOS transistor P2 is connected to the power supply, the drain of the first PMOS transistor P2 is connected to the drain of the first NMOS transistor N2, the source of the first NMOS transistor N2 is connected to the ground terminal, and the gate of the first NMOS transistor N2 is connected to the first PMOS transistor P2;

[0035] The source of the second PMOS tube P3 is connected to the power supply, the drain of the second PMOS tube P3 is connected to the drain of the second NMOS tube N3, and the second common end is connected to the gate of the power tube to be adjusted. The source of the second NMOS tube N3 is connected to the ground end, and the third common end connected to the gate of the second NMOS tube N3 and the second PMOS tube P3 is connected to the output end of the first inverter circuit 01-1. The first inverter is a first-stage inverter circuit, and the second inverter circuit 01-2 is a second-stage inverter circuit.

[0036] In the embodiment of the present application, the inverter circuit in the present application is composed of a PMOS tube and an NMOS tube. The input end of the first inverter circuit 01-1 is the gate of the first PMOS tube P2 connected to the gate of the first NMOS tube N2. The fourth common end is the input end of the first inverter circuit 01-1. The input end of the first inverter circuit 01-1 is the drain of the first PMOS tube P2 connected to the drain of the first NMOS tube N2. The fifth common end is the output end of the first inverter circuit 01-1. The input end and output end of the first inverter circuit 01-1 are respectively connected to the control circuit.

[0037] In the embodiment of the present application, the sampling circuit is a capacitor C1;

[0038] The lower plate of the capacitor C1 is connected to the first common end connected to the output end of the second inverter circuit 01-2 and the gate of the power tube to be adjusted;

[0039] The upper plate of the capacitor C1 is connected to the current generating circuit through the control circuit.

[0040] In the embodiment of the present application, the voltage change amount of the gate of the upper power tube P1 of the BUCK is collected by the sampling circuit. At the same time, the capacitor C1 is also connected to the output end of the second inverter circuit 01-2, and the second inverter circuit 01-2 outputs a control signal to control the opening and closing of the upper power tube P1 of the BUCK.

[0041] In the embodiment of the present application, the current injection circuit is a third PMOS tube P6;

[0042] The source of the third PMOS tube P6 is connected to the power supply, the drain of the third PMOS tube P6 is respectively connected to the first common end, the gate of the third PMOS tube P6 is connected to the current generating circuit, and the current is injected into the power tube to be adjusted through the third PMOS tube P6 to slow down the start-up process of the power tube to be adjusted. The third PMOS tube P6 is a current injection tube, which is a core component of the noise suppression circuit. When it works, it will inject current into the node g through the drain to slow down the start-up process of the upper power tube P1 of the BUCK. The gate of the third PMOS tube P6 is connected to the source of the fourth PMOS switch tube, and the gate of the third PMOS tube P6 is also connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the power supply VDD. The drain of the fourth PMOS tube P9 is connected to the upper plate of the capacitor C1, and the gate of the fourth PMOS tube P9 is simultaneously connected to the drain of the sixth PMOS tube P7 and the source of the fifth PMOS tube P8.

[0043] In a specific embodiment, the current generating circuit is a second resistor R2. After the voltage change of the upper power tube P1 of the BUCK is collected by the sampling circuit, it is converted into current by the second resistor R2. When the current injection circuit is turned on, the current is injected into the gate of the upper power tube P1 of the BUCK to adjust the turn-on speed of the upper power tube P1 of the BUCK.

[0044] In the embodiment of the present application, the control circuit includes a fourth PMOS transistor P9, a fifth PMOS transistor P8, a sixth PMOS transistor P7 and a first resistor R1;

[0045] The source of the fourth PMOS tube P9 is connected to one end of the current generating circuit, the drain of the fourth PMOS tube P9 is connected to the upper plate of the capacitor C1, the gate of the fourth PMOS tube P9 is connected to the source of the fifth PMOS tube P8, the gate of the fifth PMOS tube P8 is connected to the input end of the first inverter, the source of the fifth PMOS tube P8 is connected to the gate of the fourth PMOS tube P9, and the drain of the fifth PMOS tube P8 is connected to the drain of the power tube to be adjusted;

[0046] The gate of the sixth PMOS transistor P7 is connected to the output end of the first inverter circuit 01-1, the source of the sixth PMOS transistor P7 is connected to the power supply, and the drain of the sixth PMOS transistor P7 is connected to the fourth common end between the gate of the fourth PMOS transistor P9 and the source of the fifth PMOS transistor P8;

[0047] When the third PMOS tube P6, the fourth PMOS tube P9 and the fifth PMOS tube P8 are turned on and the sixth PMOS tube P7 is turned off by the duty cycle control signal, the current generating circuit generates current and injects current into the gate of the power tube to be regulated, so as to slow down the speed of reducing the gate voltage of the power tube to be regulated, thereby controlling the turn-on rate of the power tube to be regulated;

[0048] When the fifth PMOS tube P8, the fourth PMOS tube P9 and the third PMOS tube P6 are turned off and the sixth PMOS tube P7 is turned on by the duty cycle control signal, the current generating circuit is cut off and does not generate current, and does not control the power tube to be regulated.

[0049] In the embodiment of the present application, when the duty cycle control signal is at a high level, the Vg voltage is high, and the upper power tube P1 of the BUCK is turned off. On the contrary, when the duty cycle control signal is at a low level, the Vg voltage is low, and the upper power tube P1 of the BUCK is turned on. The input and output of the first-stage inverter composed of the second PMOS tube P3 and the second NMOS tube N3 are respectively connected to the gates of the sixth PMOS tube P7 and the fifth PMOS tube P8, thereby controlling the operation of the switching noise suppression circuit to be turned on and off.

[0050] The drain of the fifth PMOS tube P8 is connected to the drain of the power tube to be adjusted through the first resistor R1.

[0051] In the embodiment of the present application, the capacitor C1 is used to sample the voltage transformation on the node g and convert it into current. The node g is a common node connected to the lower plate of the capacitor, the output end of the second inverter circuit and the gate of the upper power tube P1. When the fourth PMOS tube P9 is normally turned on, the current flows through the first resistor R1, and a voltage drop is generated relative to the power supply VDD. The voltage drop acts on the gate of the current injection circuit, thereby the current injection circuit generates a current flowing into the node g.

[0052] In the embodiment of the present application, the source of the sixth PMOS tube P7 is connected to the power supply VDD, the drain of the sixth PMOS tube P7 is connected to one end of the first resistor R1, and the other end is connected to the port SW, which will then be connected to the switching node of the BUCK circuit. The current flowing through the first resistor R1 is named I1, the current flowing through the third PMOS tube P6 is named I2, and the gate current of the upper power tube P1 of the BUCK circuit is Ig. The role of the fifth PMOS tube P8 and the fifth PMOS tube P8 is to control the operation of the switching noise suppression circuit. When the sixth PMOS tube P7 is turned on and the fifth PMOS tube P8 is turned off, the voltage of the node 4 is pulled to the power supply VDD, causing the fourth PMOS tube P9 to turn off, and the fifth PMOS tube P8 is turned off and also cuts off the connection between the SW point and the node 4. At this time, the third PMOS tube P6, the sampling capacitor C1 and the second resistor R2 elements cannot function, and the switching noise suppression circuit does not work and is in a closed state. When the sixth PMOS tube P7 is turned off and the fifth PMOS tube P8 is turned on, the gate of the fourth PMOS tube P9 is connected to the SW point. Under the control of the voltage at the SW point, the fourth PMOS tube P9 can be turned on, so that the third PMOS tube P6, the sampling capacitor C1 and the second resistor R2 can function normally, and the switching noise suppression circuit is in a working state. The fifth PMOS tube P8 and the sixth PMOS tube P7 ensure that the circuit will work at an appropriate time, so as not to interfere with the normal working process of the BUCK circuit.

[0053] In a second aspect, an embodiment of the present application further provides a BUCK circuit, comprising the switching noise suppression circuit described in the first aspect.

[0054] like Figure 3 As shown, the input of the inverting circuit combination is a bidirectional non-overlapping duty cycle control signal, which is duty1 and duty2 respectively. The duty cycle control signal drives the inverting circuit combination and then drives the upper power tube P1 and the lower power tube N1 to switch periodically according to a certain duty cycle. The output end of the BUCK circuit generates a target output voltage. The circuit in the dotted box is a switching noise suppression circuit proposed in this application, also called a slew rate control circuit. VDD is the power supply inside the chip, VSS is the ground inside the chip, Lp is the parasitic inductance, including the parasitic inductance of the package binding wire, the parasitic inductance on the PCB board, etc. L and C2 are the output filter inductor and filter capacitor of the BUCK circuit respectively, and RL is the load resistance. Vin is the input voltage of the BUCK circuit, SW is the common node of the upper power tube P1 and the lower power tube N1, called the switching node. Assuming that the threshold voltages of all NMOS and PMOS in the circuit are Vthn and Vthp respectively, the working principle of the circuit is as follows:

[0055] When the duty cycle signal duty1 is at a high level, the upper power transistor P1 is turned off, Vg is equal to the high level VDD. At this time, duty2 is also at a high level, the lower power transistor N1 is turned on, and SW is at the low level VSS. The inductor conducts continuous current through the lower power transistor N1. At this time, V1 is at a high level, the fifth PMOS transistor P8 is turned off, V2 is at a low level, the sixth PMOS transistor P7 conducts to pull the node 4 to the high level VDD, the fourth PMOS transistor P9 is turned off, the node 3 is pulled to the high level through the second resistor R2, and the third PMOS transistor P6 is turned off. Therefore, the switching noise suppression circuit does not work.

[0056] When the duty cycle signal duty1 changes from high to low, the node 1 is at a low level, the fifth PMOS transistor P8 conducts, the node 2 is at a high level, and the fifth PMOS transistor P8 is turned off. Since it takes a certain amount of time for the upper power transistor P1 to turn on, at the initial moment, Vg is still at a high level and SW is also at a low level, then V4 is at a low level, and the fourth MOS transistor conducts and V3 = Vg = high level. Subsequently, the Vg level decreases. When V3 = Vg < VDD - Vthp, the third PMOS transistor P6 conducts and injects current into the g point, making the Vg voltage decrease at a slower speed, thereby controlling the turn-on rate of the upper power transistor P1 and reducing the switching noise. As Vg further decreases, the gate-source voltage Vgs of the upper power transistor P1 reaches the Miller plateau, and SW will gradually increase. As Figure 4 shown, when V4 = SW > VDD - (2 * Vthp + 2 * ΔV), the fourth PMOS transistor P9 turns off and V3 is pulled up to the high level by the second resistor R2, and the third PMOS transistor P6 turns off and no longer injects current into the g point. The Vg voltage decreases rapidly until the low level VSS. At this time, the upper power transistor P1 is fully turned on and the turn-on is completed. ΔV is the overdrive voltage of the upper power transistor P1. From Figure 4 it can be seen that the slope of the power transistor source pole current Is becomes significantly smaller and the rising process becomes significantly slower. From Figure 5 and Figure 6 it can be clearly seen that under the action of the switching noise suppression circuit, the switching noise on VDD and VSS is significantly reduced.

[0057] The function of the capacitor C1 is to sample the change rate of Vg. According to the capacitor C1 formula:

[0058]

[0059] When the Vg voltage changes rapidly, there will be a current I1 flowing through the capacitor C1 injected into the gate. In addition, this current generates a voltage drop on the second resistor R2 to turn on the third PMOS transistor P6, and there will be a current I2 injected into the gate of the upper power transistor P1. According to Kirchhoff's law equation, the equation can be listed as:

[0060] I1 + I2 + I g = I N3

[0061]

[0062]

[0063]

[0064] In the formula, k ′ p and k ′ n are the process parameters of PMOS and NMOS tubes respectively; W and L refer to the gate width and gate length of the MOS tube respectively, Vthn is the threshold voltage of the NMOS tube, Vthp is the threshold voltage of the PMOS tube, VDD is the power supply voltage, V3 is the voltage of node 3, I N3 is the current flowing through the third NMOS transistor N3, I2 is the current flowing through the third PMOS transistor P6, I1 is the current flowing through the first resistor R1, and I g is the current at node g.

[0065] Reasonably set the capacitor C1, resistor, MOS tube size and the ratio of each part current in the above equation, and ensure that I g >0, so that the upper power tube P1 can be turned on normally, while controlling the turn-on rate of the upper power tube P1. When the upper power tube P1 is turned on and the Vg voltage no longer changes, the current flowing through the capacitor C1 is 0, so V3=VDD, the third PMOS tube P6 is turned off, the switching noise suppression circuit is turned off, and there is no static power consumption. Therefore, the capacitor C1 and the sixth PMOS tube P7 and the fifth PMOS tube P8 constitute two methods for automatically turning on and off the switching noise suppression circuit, which more reliably ensures the turning on and off of the circuit in a specific time period and will not interfere with the normal working process of the drive circuit in other time periods.

[0066] In a third aspect, an embodiment of the present application further provides a switching noise suppression method, which is implemented by the circuit described in the first aspect, including:

[0067] When the third PMOS tube P6, the fourth PMOS tube P9 and the fifth PMOS tube P8 are turned on and the sixth PMOS tube P7 is turned off by the duty cycle control signal, the current generating circuit generates a current and injects the current into the gate of the power tube to be regulated, so as to slow down the speed of reducing the gate voltage of the power tube to be regulated, thereby controlling the turn-on rate of the power tube to be regulated;

[0068] When the fifth PMOS tube P8, the fourth PMOS tube P9 and the third PMOS tube P6 are turned off and the sixth PMOS tube P7 is turned on by the duty cycle control signal, the current generating circuit is cut off and does not generate current, and does not control the power tube to be regulated.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A switching noise suppression circuit, characterized in that: include: The inverter circuit combination is used to drive the power tube to be adjusted to turn off or on according to the input duty cycle signal, and to output Provide logical control of the control circuit; A sampling circuit is used to collect the gate voltage variation of the power tube to be adjusted; A current generating circuit, wherein the user generates current according to the voltage variation; A current injection circuit, used for injecting the current into the gate of the power tube to be regulated to slow down the turn-on speed of the power tube to be regulated; A control circuit, used for controlling the drain of the power tube to be regulated and the current generating circuit to be disconnected and connected according to the output logic; The inverting circuit combination comprises a first inverting circuit and a second inverting circuit connected in sequence to each other; The input end of the first inverter circuit receives a duty cycle control signal, the output end of the second inverter circuit is connected to the gate of the power tube to be adjusted, and the sampling circuit is connected to a first common end connected to the output end of the second inverter circuit and the gate of the power tube to be adjusted; The first inverting circuit includes a first NMOS tube and a first PMOS tube, and the second inverting circuit includes a second NMOS tube and a second PMOS tube; The source of the first PMOS tube is connected to a power source, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is connected to a ground terminal, and the gates of the first NMOS tube and the first PMOS tube are connected; The source of the second PMOS tube is connected to the power supply, the drain of the second PMOS tube is connected to the drain of the second NMOS tube, the second common end is connected to the gate of the power tube to be adjusted, the source of the second NMOS tube is connected to the ground end, and the third common end of the second NMOS tube and the gate of the second PMOS tube is connected to the output end of the first inverter circuit; The sampling circuit is a capacitor; The lower plate of the capacitor is connected to the first common end connected to the output end of the second inverter circuit and the gate of the power tube to be adjusted; The upper plate of the capacitor is connected to the current generating circuit through the control circuit; The current injection circuit is a third PMOS tube; The source of the third PMOS tube is connected to the power supply, the drain of the third PMOS tube is respectively connected to the first common end, the gate of the third PMOS tube is connected to the current generating circuit, and the current is injected into the power tube to be regulated through the third PMOS tube to slow down the start-up process of the power tube to be regulated.

2. A switching noise suppression circuit as claimed in claim 1, characterized in that: The control circuit includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube and a first resistor; The source of the fourth PMOS tube is connected to one end of the current generating circuit, the drain of the fourth PMOS tube is connected to the upper plate of the capacitor, the gate of the fourth PMOS tube is connected to the source of the fifth PMOS tube, the gate of the fifth PMOS tube is connected to the input end of the first inverter, the source of the fifth PMOS tube is connected to the gate of the fourth PMOS tube, and the drain of the fifth PMOS tube is connected to the drain of the power tube to be adjusted; The gate of the sixth PMOS tube is connected to the output end of the first inverter circuit, the source of the sixth PMOS tube is connected to the power supply, and the drain of the sixth PMOS tube is connected to the fourth common end between the gate of the fourth PMOS tube and the source of the fifth PMOS tube; When the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are turned on by the duty cycle control signal and the sixth PMOS tube is turned off, the current generating circuit generates current and injects current into the gate of the power tube to be regulated, so as to slow down the speed of reducing the gate voltage of the power tube to be regulated, thereby controlling the turn-on rate of the power tube to be regulated; When the fifth PMOS tube, the fourth PMOS tube and the third PMOS tube are turned off and the sixth PMOS tube is turned on by the duty cycle control signal, the current generating circuit is cut off and does not generate current, and does not control the power tube to be regulated.

3. A switching noise suppression circuit as claimed in claim 2, characterized in that: The drain of the fifth PMOS tube is connected to the drain of the power tube to be adjusted through a first resistor.

4. A switching noise suppression circuit as claimed in claim 1, characterized in that: The current generating circuit is a second resistor.

5. A BUCK circuit, characterized in that: The invention comprises the switching noise suppression circuit according to any one of claims 1 to 4.

6. A switching noise suppression method, characterized in that: The circuit is implemented by any one of claims 1 to 4, comprising: When the third PMOS tube, the fourth PMOS tube and the fifth PMOS tube are turned on and the sixth PMOS tube is turned off by the duty cycle control signal, the current generating circuit generates current and injects the current into the gate of the power tube to be regulated, so as to slow down the gate voltage reduction speed of the power tube to be regulated, thereby controlling the turn-on rate of the power tube to be regulated; when the fifth PMOS tube, the fourth PMOS tube and the third PMOS tube are turned off and the sixth PMOS tube is turned on by the duty cycle control signal, the current generating circuit is cut off and does not generate current, and does not control the power tube to be regulated.

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