Display device

Abstract

On the display area side of the peripheral circuit of the bezel area (F), a protective element (Ga) is provided along each display wiring (18g). The protective element (Ga) includes: a first conductive layer (12b) formed of a first semiconductor film made of polysilicon; a third semiconductor layer (16b) formed on the first conductive layer (12b) by a second semiconductor film made of oxide semiconductor separated from a fifth inorganic insulating film (13a); a second conductive layer (20h) and a third conductive layer (20i) formed separately from each other by a third metal film, and electrically connecting the first conductive layer (12b) to the first source region (16ba) and the first drain region (16bb).

Description

Technical Field

[0001] This invention relates to display devices. Background Technology

[0002] In recent years, self-emissive organic EL (OLED) displays, which use organic electroluminescent (EL) elements, have attracted attention as an alternative to liquid crystal displays. In these OLED displays, a thin-film transistor (TFT) is provided for each sub-pixel, which is the smallest unit of an image. Here, the semiconductor layer constituting the TFT is, for example, a semiconductor layer made of polycrystalline silicon with high mobility, or a semiconductor layer made of oxide semiconductors such as In-Ga-Zn-O with low leakage current, as is well known.

[0003] For example, in Patent Document 1, an organic EL display device is illustrated as a display device using a TFT substrate having a TFT having an oxide semiconductor layer.

[0004] Existing technical documents

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent No. 6311900 Summary of the Invention

[0007] The technical problem to be solved by the present invention

[0008] However, in high-resolution display devices with TFTs having semiconductor layers made of oxide semiconductors, the characteristics of TFTs using oxide semiconductors may be reduced due to damage to the insulating film caused by electrostatic discharge accumulated during the manufacturing process and the intrusion of moisture from the outside.

[0009] The present invention was made in view of the above-mentioned problems, and its object is to suppress the degradation of the characteristics of thin film transistors using oxide semiconductors caused by electrostatic discharge and moisture intrusion.

[0010] Technical solutions for solving technical problems

[0011] To achieve the above objectives, the display device of the present invention comprises: a substrate; and a thin-film transistor layer disposed on the substrate, wherein a first semiconductor film made of polysilicon; a first gate insulating film made of a first inorganic insulating film; a first metal film; a first interlayer insulating film made of a second inorganic insulating film; a second semiconductor film made of an oxide semiconductor; a second gate insulating film made of a third inorganic insulating film; a second metal film; a second interlayer insulating film made of a fourth inorganic insulating film; a third metal film; and a planarization film made of an organic resin material are sequentially stacked on the substrate. The thin-film transistor layer comprises: a plurality of display wirings extending parallel to each other from the second metal film; a plurality of in-pixel thin-film transistors corresponding to a plurality of sub-pixels constituting a display area; and a plurality of out-of-pixel thin-film transistors serving as peripheral circuitry in a border region surrounding the display area. Each in-pixel thin-film transistor has a shape formed by the second semiconductor film. The display device is characterized in that, on the display area side of the peripheral circuit in the bezel region, a protective element is provided along each display wiring, the protective element comprising: a first conductive layer formed of the first semiconductor film and conductive; a third semiconductor layer formed of the second semiconductor film and separated from the first conductive layer by a fifth inorganic insulating film, wherein a first source region and a first drain region are defined in a mutually separated manner, and a first channel region is defined between the first source region and the first drain region; a second conductive layer and a third conductive layer formed mutually separated by the third metal film, and the first conductive layer is electrically connected to the first source region and the first drain region, the first channel region being configured to overlap with each display wiring.

[0012] Beneficial effects

[0013] According to the present invention, it is possible to suppress the degradation of the characteristics of thin-film transistors using oxide semiconductors caused by electrostatic discharge and moisture intrusion. Attached Figure Description

[0014] Figure 1 This is a top view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention.

[0015] Figure 2 This is a top view of the display area of ​​the organic EL display device according to the first embodiment of the present invention.

[0016] Figure 3 This is a cross-sectional view of the organic EL display device according to the first embodiment of the present invention.

[0017] Figure 4 This is an equivalent circuit diagram of the TFT layer of the organic EL display device constituting the first embodiment of the present invention.

[0018] Figure 5 This is a cross-sectional view of the organic EL layer constituting the organic EL display device of the first embodiment of the present invention.

[0019] Figure 6 This is a top view showing the area between the display area and the bezel area of ​​the organic EL display device according to the first embodiment of the present invention.

[0020] Figure 7 It is along Figure 6 A cross-sectional view of the bezel area of ​​an organic EL display device with lines VII-VII in the diagram.

[0021] Figure 8 This is a top view showing the area between the display area and the bezel area of ​​the driving circuit of a modified example of the organic EL display device according to the first embodiment of the present invention.

[0022] Figure 9 This is a top view showing the area between the display area and the bezel area of ​​the organic EL display device according to the second embodiment of the present invention.

[0023] Figure 10 It is along Figure 9 A cross-sectional view of the bezel area of ​​an organic EL display device with XX lines. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0025] First Implementation Method

[0026] Figures 1 to 8 A first embodiment of the display device of the present invention is shown. Furthermore, in the following embodiments, an organic EL display device having an organic EL element layer is exemplified as a display device having a light-emitting element layer. Here, Figure 1 This is a top view showing the schematic configuration of the organic EL display device 50a according to this embodiment. Furthermore, Figure 2 This is a top view of the display area D of the organic EL display device 50a. Furthermore, Figure 3 This is a cross-sectional view of the organic EL display device 50a. Furthermore, Figure 4 This is an equivalent circuit diagram of the TFT layer 30 constituting the organic EL display device 50a. Furthermore, Figure 5This is a cross-sectional view of the organic EL layer 33 constituting the organic EL display device 50a. Furthermore, Figure 6 This is a top view showing the area between the display area D and the bezel area F of the organic EL display device 50a, as well as the driving circuit M. Furthermore, Figure 7 It is along Figure 6 A cross-sectional view of the bezel region F of the organic EL display device 50a with lines VII-VII in the diagram. Furthermore, Figure 8 This is a top view of the area between the display area D and the driving circuit M of the bezel area F of a modified example of the organic EL display device 50a (organic EL display device 50aa).

[0027] like Figure 1 As shown, the organic EL display device 50a includes, for example, a display area D for displaying images, which is set in a rectangular shape, and a border area F that is set in a frame shape around the display area D. In addition, in this embodiment, a rectangular display area D is exemplified, but the rectangular shape also includes, for example, a shape with rounded edges, a shape with rounded corners, or a shape with a cutout on part of the edge, etc., which are generally rectangular shapes.

[0028] like Figure 2 As shown, in display area D, multiple sub-pixels P are arranged in a matrix. Furthermore, in display area D, as... Figure 2 As shown, for example, sub-pixels P having a red emitting area Lr for red display, sub-pixels P having a green emitting area Lg for green display, and sub-pixels P having a blue emitting area Lb for blue display are arranged adjacent to each other. Furthermore, in the display area D, for example, a pixel is formed by three adjacent sub-pixels P having the red emitting area Lr, the green emitting area Lg, and the blue emitting area Lb.

[0029] In the border area F Figure 1 The right end of the terminal portion T is provided in a manner that extends in one direction (longitudinal in the figure). Furthermore, as... Figure 1 As shown, between the display area D and the terminal portion T, that is, in the bezel area F, on the display area D side of the terminal portion T, a bent portion B, which can be bent at 180° (U-shape) as the bending axis in the figure, is provided in a manner that extends in one direction (the longitudinal direction in the figure). Furthermore, in the bezel area F... Figure 1 The upper and lower ends of the circuit are equipped with drive circuits M as peripheral circuits.

[0030] like Figure 3As shown, the organic EL display device 50a includes: a resin substrate 10 provided as a substrate, a TFT layer 30 provided on the resin substrate 10, an organic EL element layer 40 provided on the TFT layer 30 as a light-emitting element layer, and a sealing film 45 provided to cover the organic EL element layer 40.

[0031] The resin substrate 10 is made of, for example, polyimide resin.

[0032] like Figure 3 As shown, the TFT layer 30 includes: a base coating film 11 disposed on the resin substrate 10, and a plurality of first pixel in-cell TFTs 9a disposed on the base coating film 11 (see reference). Figure 4 ), multiple second-pixel internal TFT9b, multiple capacitors 9c (refer to) Figure 4 A protective insulating film 21 and a planarization film 22 are sequentially disposed on multiple external TFTs 9d of each pixel, internal TFTs 9a of each first pixel, internal TFTs 9b of each second pixel, capacitors 9c, and external TFTs 9d of each pixel. Here, in the TFT layer 30, as shown... Figure 2 and Figure 4 As shown, multiple gate lines 18g are arranged as display wiring, extending parallel to each other along the horizontal direction in the figure. Additionally, in the TFT layer 30, as... Figure 2 and Figure 4 As shown, multiple source lines 20f are provided as display wiring in a direction that intersects (orthogonally to) the multiple gate lines 18g, that is, in a manner that extends parallel to each other along the longitudinal direction shown in the figure. Furthermore, in the TFT layer 30, as... Figure 2 and Figure 4 As shown, multiple power lines 20g are arranged parallel to each other along the longitudinal direction of the diagram as display wiring. Furthermore, as... Figure 2 As shown, each power line 20g is positioned adjacent to each source line 20f. Furthermore, in the TFT layer 30, as... Figure 4 As shown, each sub-pixel P is provided with a TFT 9a in the first pixel, a TFT 9b in the second pixel, and a capacitor 9c. Additionally, as... Figure 3 As shown, in the TFT layer 30, a base coating film 11, a first semiconductor film that becomes the first semiconductor layer 12a (described later), a first gate insulating film 13, a first metal film that becomes the second gate 14a (described later), a first interlayer insulating film 15, a second semiconductor film that becomes the second semiconductor layer 16a (described later), a second gate insulating film 17, a second metal film that becomes the gate line 18g, a second interlayer insulating film 19, a third metal film that becomes the source line 20f, a protective insulating film 21, and a planarization film 22 are sequentially stacked on the resin substrate 10.

[0033] The substrate coating film 11 is, for example, an inorganic insulating film composed of a single layer or a stack of films such as silicon nitride, silicon oxide, or silicon oxynitride. Furthermore, the first gate insulating film 13 is, for example, a first inorganic insulating film composed of a single layer or a stack of films such as silicon nitride, silicon oxide, or silicon oxynitride. Furthermore, the first interlayer insulating film 15 is, for example, a second inorganic insulating film composed of a single layer or a stack of films such as silicon nitride, silicon oxide, or silicon oxynitride. Furthermore, the second gate insulating film 17 is, for example, a third inorganic insulating film composed of a single layer or a stack of films such as silicon nitride, silicon oxide, or silicon oxynitride. Furthermore, the second interlayer insulating film 19 is, for example, a fourth inorganic insulating film composed of a single layer or a stack of films such as silicon nitride, silicon oxide, or silicon oxynitride. Furthermore, the protective insulating film 21 is, for example, a sixth inorganic insulating film composed of a single layer or a stack of films such as silicon nitride, silicon oxide, or silicon oxynitride. Here, at least the second semiconductor layer 16a side of the first interlayer insulating film 15 and the second semiconductor layer 16a side of the second gate insulating film 17 are composed of silicon oxide film.

[0034] like Figure 4 As shown, the TFT 9a within the first pixel is electrically connected to the corresponding gate line 18g and source line 20f in each sub-pixel P. Furthermore, as... Figure 3 As shown, the TFT 9a in the first pixel includes: a second semiconductor layer 16a disposed on the first interlayer insulating film 15; a first gate 18a disposed on the second semiconductor layer 16a across the second gate insulating film 17; and a first source 20a and a first drain 20b disposed on the second interlayer insulating film 19 in a mutually separated manner.

[0035] The second semiconductor layer 16a is formed, for example, a second semiconductor film composed of an oxide semiconductor such as an In-Ga-Zn-O system. Figure 3The diagram shows a second source region 16aa and a second drain region 16ab defined in a mutually separated manner, and a second channel region 16ac defined between the second source region 16aa and the second drain region 16ab. Here, the In-Ga-Zn-O semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited. Furthermore, the In-Ga-Zn-O semiconductor can be amorphous or crystalline. Additionally, as a crystalline In-Ga-Zn-O semiconductor, a crystalline In-Ga-Zn-O semiconductor with its c-axis oriented substantially perpendicular to the layer is preferred. Furthermore, other oxide semiconductors may be included instead of the In-Ga-Zn-O semiconductor. Other oxide semiconductors may include, for example, In-Sn-Zn-O semiconductors (e.g., In₂O₃-SnO₂-ZnO; InSnZnO). Here, the In-Sn-Zn-O semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors may also include In-Al-Zn-O, In-Al-Sn-Zn-O, Zn-O, In-Zn-O, Zn-Ti-O, Cd-Ge-O, Cd-Pb-O, CdO (cadmium oxide), Mg-Zn-O, In-Ga-Sn-O, In-Ga-O, Zr-In-Zn-O, Hf-In-Zn-O, Al-Ga-Zn-O, Ga-Zn-O, In-Ga-Zn-Sn-O, InGaO3(ZnO)5, and magnesium zinc oxide (MgO). x Zn 1-x O), zinc cadmium oxide (Cd) x Zn 1-x (O), etc. In addition, as a Zn-O semiconductor, it is possible to use amorphous (amorphous) semiconductors of ZnO with one or more impurity elements from Group 1, Group 13, Group 14, Group 15, and Group 17, polycrystalline semiconductors, microcrystalline semiconductors with a mixture of amorphous and polycrystalline states, or semiconductors without any impurity elements added.

[0036] like Figure 3 As shown, the first gate 18a is configured to overlap with the second channel region 16ac of the second semiconductor layer 16a, thereby controlling the conduction between the second source region 16aa and the second drain region 16ab of the second semiconductor layer 16a. Furthermore, similar to the gate line 18g, the first gate 18a is formed of a second metal film.

[0037] like Figure 3 As shown, the first source 20a and the first drain 20b are electrically connected to the second source region 16aa and the second drain region 16ab of the second semiconductor layer 16a via contact holes formed in the second gate insulating film 17 and the second interlayer insulating film 19, respectively. Furthermore, similar to the source line 20f and the power line 20g, the first source 20a and the first drain 20b are formed of a third metal film.

[0038] like Figure 4 As shown, the TFT 9b in the second pixel is electrically connected to the corresponding TFT 9a in the first pixel and the power line 20g in each sub-pixel P. Furthermore, the TFT 9b in the second pixel, like the TFT 9a in the first pixel, includes a second semiconductor layer (16a), a first gate (18a), a first source (20a), and a first drain (20b).

[0039] like Figure 4 As shown, capacitor 9c is electrically connected to the corresponding TFT 9a and power line 20g in each sub-pixel P. Here, capacitor 9c includes, for example, a lower conductive layer formed of a second metal film, an upper conductive layer formed of a third metal film, and a second interlayer insulating film 19 disposed between these lower and upper conductive layers. Furthermore, the upper conductive layer is electrically connected to the power line 20g through contact holes formed in the second interlayer insulating film 19.

[0040] The planarization film 22 has a flat surface in the display area D, and is made of organic resin materials such as polyimide resin.

[0041] like Figure 3 As shown, the organic EL element layer 40 includes a plurality of first electrodes 31a, a shared edge mask 32a, a plurality of organic EL layers 33, and a shared second electrode 34, which are sequentially stacked corresponding to a plurality of sub-pixels P. Here, in each sub-pixel P, as... Figure 3 As shown, the first electrode 31a, the organic EL layer 33, and the second electrode 34 constitute the organic EL element 35 (see reference). Figure 4 ).

[0042] The first electrode 31a is electrically connected to the first drain 20b of the TFT 9b in the second pixel of each sub-pixel P via contact holes formed on the protective insulating film 21 and the planarization film 22. Furthermore, the first electrode 31a has the function of injecting holes into the organic EL layer 33. Moreover, to improve the efficiency of hole injection into the organic EL layer 33, it is more preferable to form the first electrode 31a with a material having a high work function. Examples of materials constituting the first electrode 31a include, for example, metallic materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). Additionally, the material constituting the first electrode 31a may also be, for example, an alloy of astatine (At) / astatine oxide (AtO2). Furthermore, the material constituting the first electrode 31a can be, for example, a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). Additionally, the first electrode 31a can be formed by stacking multiple layers composed of the aforementioned materials. Furthermore, compound materials with high work functions can be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0043] The edge cover 32a is made of, for example, organic resin materials such as polyimide resin and acrylic resin, or SOG (spin on glass) material based on polysiloxane. Here, for example... Figure 3 As shown, a portion of the surface of the edge mask 32a protrudes upwards in the figure, becoming a pixel light spacer configured as an island.

[0044] The organic EL layer 33 is set as a light-emitting functional layer, such as Figure 5 As shown, the device comprises a hole injection layer 1, a hole transport layer 2, a light emission layer 3, an electron transport layer 4, and an electron injection layer 5, which are sequentially stacked on the first electrode 31a.

[0045] Hole injection layer 1, also known as anolyte buffer layer, functions to bring the energy levels of the first electrode 31a and the organic EL layer 33 closer together, thereby improving the hole injection efficiency from the first electrode 31a to the organic EL layer 33. Examples of materials constituting hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrene-anthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0046] The hole transport layer 2 has the function of improving the hole transport efficiency from the first electrode 31a to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrene-based amine derivatives, polyvinylcarbazole, poly-p-phenylene vinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrene-based anthracene derivatives, fluorenone derivatives, hydrazone derivatives, zirconia derivatives, hydrogenated amorphous silicon, amorphous hydrogenated silicon carbide, zinc sulfide, or zinc selenide.

[0047] The light-emitting layer 3 is the region in which holes and electrons are injected from the first electrode 31a and the second electrode 34 respectively when a voltage is applied, and the holes and electrons recombine. Here, the light-emitting layer 3 is formed of a material with high luminous efficiency. Furthermore, as materials constituting the light-emitting layer 3, examples include, for instance, metal hydroxyquinoline ketone compounds [8-hydroxyquinoline metal complexes], naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinyl acetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bis(Styryl)Benzene derivatives, tristyrylbenzene derivatives, perylene derivatives, pyrene derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, acridine derivatives, phenoxazone, quinacridone derivatives, rubrene, poly(p-phenylenevinylene), or polysilanes.

[0048] The electron transport layer 4 has the function of enabling electrons to move efficiently to the light-emitting layer 3. Here, as materials constituting the electron transport layer 4, examples of organic compounds include: oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinone dimethane derivatives, biphenylquinone derivatives, fluorenone derivatives, thiophene derivatives, metaloxinoid compounds, etc.

[0049] The electron injection layer 5 functions to bring the energy levels of the second electrode 34 and the organic EL layer 33 closer together, thereby improving the efficiency of electron injection from the second electrode 34 into the organic EL layer 33. This function reduces the driving voltage of the organic EL element 35. The electron injection layer 5 is also referred to as a cathode buffer layer. Examples of materials constituting the electron injection layer 5 include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), as well as alumina (Al2O3) and strontium oxide (SrO).

[0050] like Figure 3 As shown, the second electrode 34 is shared across all sub-pixels P, covering each organic EL layer 33 and the edge mask 32a. Furthermore, the second electrode 34 has the function of injecting electrons into the organic EL layer 33. Moreover, to improve the efficiency of electron injection into the organic EL layer 33, the second electrode 34 is more preferably made of a material with a low work function. Examples of materials constituting the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). Furthermore, the second electrode 34 may also be formed from alloys such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO2), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). Additionally, the second electrode 34 may also be formed from conductive oxides such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), and indium zinc oxide (IZO). Furthermore, the second electrode 34 may also be formed by stacking multiple layers of the above-mentioned materials. In addition, materials with low work functions include, for example, magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), lithium fluoride (LiF) / calcium (Ca) / aluminum (Al), etc.

[0051] like Figure 3As shown, the sealing film 45 is provided to cover the second electrode 34, and has a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 sequentially stacked on the second electrode 34, and has the function of protecting the organic EL layer 33 of the organic EL element 35 from the influence of moisture, oxygen, etc. Here, the first inorganic sealing film 41 and the second inorganic sealing film 43 are, for example, made of inorganic insulating films such as silicon nitride film, silicon oxide film, and silicon oxynitride film. In addition, the organic sealing film 42 is, for example, made of organic resin materials such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, and polyamide resin.

[0052] In addition, such as Figure 3 As shown, the organic EL display device 50a has a plurality of peripheral light spacers 32b arranged in an island-like manner on the planarization film 22 in the bezel region F, protruding upwards in the figure through a conductive layer 31b. Here, each peripheral light spacer 32b is formed in the same layer as the edge cover 32a. Furthermore, the conductive layer 31b is formed in the same layer as the first electrode 31a.

[0053] In addition, such as Figure 3 As shown, the organic EL display device 50a has multiple external TFTs 9d in the bezel area F, which are arranged in a manner that constitutes a driving circuit M.

[0054] like Figure 3 As shown, the external TFT 9d includes: a first semiconductor layer 12a disposed on a substrate coating film 11, a second gate 14a disposed on the first semiconductor layer 12a separated by a first gate insulating film 13, and a second source 20c and a second drain 20d disposed on a second interlayer insulating film 19 in a mutually separated manner.

[0055] The first semiconductor layer 12a is formed, for example, from polycrystalline silicon such as LTPS (low temperature polysilicon), such as... Figure 3 As shown, it includes a third source region 12aa and a third drain region 12ab that are defined in a mutually separated manner, and a third channel region 12ac that is defined between the third source region 12aa and the third drain region 12ab.

[0056] like Figure 3 As shown, the second gate 14a is configured to overlap with the third channel region 12ac of the first semiconductor layer 12a, thereby controlling the conduction between the third source region 12aa and the third drain region 12ab of the first semiconductor layer 12a. Furthermore, the second gate 14a is formed of a first metal film.

[0057] like Figure 3As shown, the second source 20c and the second drain 20d are electrically connected to the third source region 12aa and the third drain region 12ab of the first semiconductor layer 12a via contact holes formed in the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 17, and the second interlayer insulating film 19, respectively. Furthermore, the second source 20c and the second drain 20d, along with the source line 20f, the power line 20g, the first source 20a, and the first drain 20b, are also formed from a third metal film.

[0058] In addition, such as Figure 6 As shown, the organic EL display device 50a has multiple protection elements Ga disposed along each gate line 18g on the display area D side of the driving circuit M in the bezel area F.

[0059] like Figure 6 and Figure 7 As shown, the protective element Ga includes: a first conductive layer 12b disposed on a substrate coating film 11, a third semiconductor layer 16b disposed on the first conductive layer 12b through a fifth inorganic insulating film 13a, and a second conductive layer 20h and a third conductive layer 20i disposed on a second interlayer insulating film 19 in a mutually separated manner.

[0060] The first conductive layer 12b is formed from a first semiconductor film and is made conductive by doping with impurity ions. Here, as... Figure 7 As shown, the portion of the first conductive layer 12b that is electrically connected to the second conductive layer 20h and the portion that is electrically connected to the third conductive layer 20i are integrated in such a way that the first conductive layer 12b overlaps with the first channel region 16ac described later.

[0061] The fifth inorganic insulating film 13a is composed of, for example, a single-layer film or a multilayer film such as silicon nitride, silicon oxide, or silicon oxynitride. Specifically, it is formed in the same layer as the first gate insulating film 13. Furthermore, in this embodiment, a configuration in which a fifth inorganic insulating film 13a formed in the same layer as the first gate insulating film 13 is disposed between the first conductive layer 12b and the third semiconductor layer 16b is described. However, the fifth inorganic insulating film 13a between the first conductive layer 12b and the third semiconductor layer 16b may also be formed in the same layer as the first interlayer insulating film 15.

[0062] The third semiconductor layer 16b, like the second semiconductor layer 16a, is formed of the second semiconductor film, such as... Figure 7 As shown, it includes: a first source region 16ba and a first drain region 16bb defined in a mutually separated manner; and a first channel region 16bc defined between the first source region 16ba and the first drain region 16bb. Here, as Figure 7 As shown, the first channel region 16bc is configured to overlap with each gate line 18g.

[0063] like Figure 7 As shown, the second conductive layer 20h and the third conductive layer 20i are configured to electrically connect the first conductive layer 12b to the first source region 16ba and the first drain region 16bb respectively via contact holes formed in the second gate insulating film 17 and the second interlayer insulating film 19. Furthermore, the second conductive layer 20h and the third conductive layer 20i, like the source line 20f, the power line 20g, the first source 20a, and the first drain 20b, are formed of a third metal film.

[0064] The protective element Ga described above is configured such that, for example, if static electricity accumulated along the longer gate lines 18g that cross the display area D enters through the second conductive layer 20h and the third conductive layer 20i, which are provided as lightning rods, it accumulates in the fifth inorganic insulating film 13a disposed between the first conductive layer 12b and the first source region 16ba and the first drain region 16bb. Here, the protective element Ga is configured such that even if it is damaged by static electricity, it will not be electrically connected to the components that contribute to the actual operation of the organic EL display device 50a, and therefore will not affect the actual operation of the organic EL display device 50a. Furthermore, the protective element Ga can physically block moisture that enters along each gate line 18g as a structure, thus suppressing the intrusion of moisture from the outside into the display area D.

[0065] Furthermore, in this embodiment, an organic EL display device 50a with a protective element Ga is illustrated, but it could also be as follows: Figure 8 An organic EL display device 50aa with a protective element Gaa, as shown.

[0066] Specifically, in the organic EL display device 50aa, such as Figure 8 As shown, the protective element Gaa includes a first conductive layer 12ba disposed on the substrate coating film 11, and is separated by a fifth inorganic insulating film 13a (see reference). Figure 7 The third semiconductor layer 16b is disposed on the first conductive layer 12ba, and the second interlayer insulating film 19 is disposed separately from each other (see reference). Figure 7 The second conductive layer 20h and the third conductive layer 20i on the surface. Here, as... Figure 8 As shown, the first conductive layer 12ba is shared in a strip shape among multiple protective elements. According to this organic EL display device 50aa, the capacitance of the fifth inorganic insulating film 13a disposed between the first conductive layer 12ba and the first source region 16ba and the first drain region 16bb increases, thus enabling the storage of more static electricity. Furthermore, the first conductive layer 12ba can also be grounded.

[0067] In addition, the organic EL display device 50a includes a first barrier rib provided in a frame shape so as to surround the display area D and a second barrier rib provided in a frame shape around the first barrier rib in the border area F. Here, the first barrier rib and the second barrier rib each include a lower resin layer formed of, for example, the same material as the planarization film 22 on the same layer, and an upper resin layer provided on the lower resin layer and formed of the same material as the edge cover 32a on the same layer. In addition, the first barrier rib is provided so as to overlap with the outer peripheral end portion of the organic sealing film 42 of the sealing film 45 and is configured to suppress the diffusion of the ink of the organic sealing film 42.

[0068] The above-described organic EL display device 50a is configured such that in each sub-pixel P, a gate signal is input to the first in-pixel TFT 9a through the gate line 18g to make the first in-pixel TFT 9a conductive, a data signal is written to the first gate 18a of the second in-pixel TFT 9b and the capacitor 9c through the source line 20f, and a current corresponding to the gate voltage of the second in-pixel TFT 9b is supplied from the power supply line 20g to the organic EL layer 33, so that the light-emitting layer 3 of the organic EL layer 33 emits light to perform image display. In addition, in the organic EL display device 50a, even when the first in-pixel TFT 9a becomes non-conductive, since the gate voltage of the second in-pixel TFT 9b is held by the capacitor 9c, the light emission of the light-emitting layer 3 is maintained until the gate signal of the next frame is input.

[0069] Next, a method for manufacturing the organic EL display device 50a of the present embodiment will be described. Here, the method for manufacturing the organic EL display device 50a of the present embodiment includes a TFT layer formation process, an organic EL element layer formation process, and a sealing film formation process.

[0070] <TFT layer formation process>

[0071] First, on the resin substrate 10 formed on the glass substrate, a silicon nitride film (with a thickness of about 50 nm) and a silicon oxide film (with a thickness of about 250 nm) are sequentially formed by, for example, plasma CVD (Chemical Vapor Deposition) method to form the base coating film 11.

[0072] Next, an amorphous silicon film (with a thickness of about 50 nm) is formed on the surface of the substrate on which the base coating film 11 is formed by, for example, plasma CVD method. After the amorphous silicon film is crystallized by laser annealing or the like to form a first semiconductor film made of polysilicon, the first semiconductor film is patterned to form the first semiconductor layer 12a and other first semiconductor layers 12b.

[0073] Subsequently, for example, a silicon oxide film (about 100 nm thick) is formed on the surface of a substrate on which the first semiconductor layer 12a is formed by plasma CVD, and the silicon oxide film is patterned to form the first gate insulating film 13 and the fifth inorganic insulating film 13a.

[0074] Furthermore, on the substrate surface on which the first gate insulating film 13 is formed, a first metal film such as a molybdenum film (with a thickness of about 200 nm) is formed, for example by sputtering, the first metal film is patterned to form the second gate 14a.

[0075] Next, using the second gate 14a as a mask, impurity ions are doped into the first semiconductor layer 12a and the other first semiconductor layers (12b), thereby integrating a portion of the first semiconductor layer 12a with the other first semiconductor layers (12b), forming a third source region 12aa, a third drain region 12ab and a third channel region 12ac in the first semiconductor layer 12a, and forming a first conductive layer 12b.

[0076] Then, a silicon nitride film (about 150 nm thick) and a silicon oxide film (about 100 nm thick) are sequentially formed on the surface of a substrate that has been conductiveized, such as a portion of the first semiconductor layer 12a, by means of, plasma CVD, thereby forming a first interlayer insulating film 15.

[0077] Furthermore, on the substrate surface on which the first interlayer insulating film 15 is formed, a second semiconductor film is formed, for example, by sputtering an oxide semiconductor such as an InGaZnO4 film (thickness of about 30 nm), and the second semiconductor film is patterned to form a second semiconductor layer 16a and a third semiconductor layer 16b.

[0078] Next, for example, a silicon oxide film (about 100 nm thick) is formed on the surface of a substrate on which the second semiconductor layer 16a is formed by plasma CVD, thereby forming the second gate insulating film 17.

[0079] Then, on the substrate surface where the second gate insulating film 17 is formed, a second metal film such as a molybdenum film (about 200 nm thick) is formed by sputtering, and the second metal film is patterned to form a first gate 18a and a gate line 18g.

[0080] Furthermore, for example, a silicon oxide film (approximately 300 nm thick) and a silicon nitride film (approximately 150 nm thick) are sequentially formed on the surface of a substrate on which the first gate 18a is formed, by plasma CVD, thereby forming a second interlayer insulating film 19. In addition, by heat treatment after the formation of the second interlayer insulating film 19, a portion of the second semiconductor layer 16a and a portion of the third semiconductor layer 16b are made conductive, forming a second source region 16aa, a second drain region 16ab, and a second channel region 16ac in the second semiconductor layer 16a, and forming a first source region 16ba, a first drain region 16bb, and a first channel region 16bc in the third semiconductor layer 16b.

[0081] Next, contact holes are formed on the substrate surface where the second interlayer insulating film 19 is formed by appropriately patterning the first gate insulating film 13, the first interlayer insulating film 15, the second gate insulating film 17, and the second interlayer insulating film 19. Here, even if the patterning is performed by dry etching when forming the contact holes (typically near the end of a long wiring that is prone to electrostatic discharge), electrostatic discharge can be suppressed because multiple protective elements Ga are provided along each gate line 18g on the display area D side of the drive circuit M in the frame region F.

[0082] Subsequently, for example, a third metal film is formed by sequentially forming a titanium film (thickness of about 50 nm), an aluminum film (thickness of about 400 nm), and a titanium film (thickness of about 200 nm) on the surface of the substrate where the contact holes are formed using a sputtering method. Then, the third metal film is patterned to form a first source electrode 20a, a first drain electrode 20b, a second source electrode 20c, a second drain electrode 20d, a source line 20f, a power line 20g, a second conductive layer 20h, and a third conductive layer 20i.

[0083] Furthermore, for example, a silicon oxide film (approximately 250 nm thick) is formed on the surface of a substrate on which the first source electrode 20a is formed by plasma CVD, thereby forming a protective insulating film 21.

[0084] Next, for example, an acrylic photosensitive resin film (about 2 μm thick) is coated on the surface of the substrate on which the protective insulating film 21 is formed by spin coating or slot coating. Then, the coated film is pre-baked, exposed, developed and post-baked to form a planarization film 22 with contact holes.

[0085] Finally, the exposed protective insulating film 21 is removed from the contact hole of the planarization film 22, so that the contact hole reaches the second drain 20d of the TFT9b in the second pixel.

[0086] As described above, a TFT layer 30 can be formed.

[0087] <Organic EL Device Layer Formation Process>

[0088] On the planarization film 22 of the TFT layer 30 formed in the above-mentioned TFT layer formation process, a first electrode 31a, an edge mask 32a, an organic EL layer 33 (hole injection layer 1, hole transport layer 2, light emission layer 3, electron transport layer 4, electron injection layer 5) and a second electrode 34 are formed using known methods, thereby forming an organic EL element layer 40.

[0089] <Sealing film formation process>

[0090] First, on the surface of the substrate on which the organic EL element layer 40 is formed in the above-mentioned organic EL element layer formation process, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask, thereby forming a first inorganic sealing film 41.

[0091] Next, for example, an organic resin material such as acrylic resin is formed on the surface of the substrate on which the first inorganic sealing film 41 is formed by inkjet printing to form an organic sealing film 42.

[0092] Furthermore, for the substrate on which the organic sealing film 42 is formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask, thereby forming a second inorganic sealing film 43, and thus forming a sealing film 45.

[0093] Finally, after attaching a protective sheet (not shown) to the surface of the substrate on which the sealing film 45 is formed, a laser is irradiated from the glass substrate side of the resin substrate 10, thereby peeling the glass substrate off from the lower surface of the resin substrate 10, and then attaching a protective sheet (not shown) to the lower surface of the resin substrate 10 after the glass substrate has been peeled off.

[0094] As described above, the organic EL display device 50a of this embodiment can be manufactured.

[0095] As explained above, in the organic EL display device 50a according to this embodiment, a plurality of protective elements Ga are provided along each gate line 18g on the display area D side of the driving circuit M in the bezel area F. Here, the protective element Ga includes: a first conductive layer 12b disposed on the substrate coating film 11; a third semiconductor layer 16b disposed on the first conductive layer 12b with a fifth inorganic insulating film 13a separating it; a second conductive layer 20h and a third conductive layer 20i disposed on the second interlayer insulating film 19 in a mutually separated manner; and a fifth inorganic insulating film 13a disposed between the first conductive layer 12b and the first source region 16ba and the first drain region 16bb when static electricity accumulated along each gate line 18g penetrates from the second conductive layer 20h and the third conductive layer 20i. Furthermore, the protective element Ga can physically block moisture penetrating along each gate line 18g as a structure, thus suppressing the intrusion of moisture from the outside into the display area D. Therefore, it is possible to suppress the degradation of the characteristics of the first pixel TFT9a and the second pixel TFT9b of the oxide semiconductor caused by electrostatic discharge and moisture intrusion.

[0096] Second Implementation Method

[0097] Figure 9 and Figure 10 A second embodiment of the display device of the present invention is shown. Here, Figure 9 This is a top view showing the area between the display area D and the bezel area F of the organic EL display device 50b according to this embodiment, and the driving circuit M. Furthermore, Figure 10 It is along Figure 9 A cross-sectional view of the bezel region F of the organic EL display device 50b with XX lines. Furthermore, in the following embodiments, [the following is a description of the device]. Figures 1 to 8 Identical parts are labeled with the same reference numerals, and their detailed descriptions are omitted.

[0098] In the first embodiment described above, an organic EL display device 50a is illustrated in which a protective element Ga is provided on the display area D side of the driving circuit M in the bezel area F. However, in this embodiment, an organic EL display device 50b is illustrated in which a protective element Gb is provided on the display area D side of the driving circuit M in the bezel area F.

[0099] The organic EL display device 50b is similar to the organic EL display device 50a of the first embodiment described above, and includes a display area D that is set in a rectangle and a border area F that is set in a frame shape around the display area D.

[0100] Furthermore, the organic EL display device 50b, like the organic EL display device 50a of the first embodiment described above, includes: a resin substrate 10; a TFT layer 30 disposed on the resin substrate 10; an organic EL element layer 40 disposed on the TFT layer 30; and a sealing film 45 disposed to cover the organic EL element layer 40.

[0101] Furthermore, the organic EL display device 50b is similar to the organic EL display device 50a of the first embodiment described above, and has a plurality of peripheral light spacers 32b, a plurality of external TFTs 9d, a first barrier wall, and a second barrier wall in the frame area F.

[0102] In addition, such as Figure 9 As shown, the organic EL display device 50b includes a plurality of protection elements Gb disposed along each gate line 18g on the display area D side of the drive circuit M in the bezel area F.

[0103] like Figure 9 and Figure 10 As shown, the protective element Gb includes: a pair of first conductive layers 12c disposed on the substrate coating film 11; a third semiconductor layer 16b disposed on the pair of first conductive layers 12c separated by a fifth inorganic insulating film 13b; and a second conductive layer 20j and a third conductive layer 20k disposed on a second interlayer insulating film 19 in a mutually separated manner.

[0104] The first conductive layer 12c is formed from a first semiconductor film and is made conductive by doping with impurity ions. Here, as... Figure 9 and Figure 10 As shown, the first conductive layer 12c is separated on one side electrically connected to the second conductive layer 20j and on the other side electrically connected to the third conductive layer 20k, and a pair is provided as described above.

[0105] The fifth inorganic insulating film 13b is composed of, for example, a single layer or a multilayer film such as silicon nitride, silicon oxide, or silicon oxynitride. Specifically, it is formed in the same layer as the first gate insulating film 13.

[0106] like Figure 9 and Figure 10 As shown, the second conductive layer 20j and the third conductive layer 20k are configured such that a pair of first conductive layers 12c, a first source region 16ba, and a first drain region 16bb are electrically connected via contact holes formed in the second gate insulating film 17 and the second interlayer insulating film 19. Furthermore, the second conductive layer 20j and the third conductive layer 20k, like the source line 20f, the power line 20g, the first source 20a, and the first drain 20b, are formed from a third metal film.

[0107] Here, as Figure 9As shown, the protection elements Gb of one gate line in an adjacent pair of gate lines 18g and the protection elements Gb of the other gate line in an adjacent pair of gate lines 18g are configured to be adjacent to each other along a direction that intersects (orthogonally) with the gate lines 18g (vertical direction in the figure). Furthermore, in the pair of protection elements Gb adjacent along the direction orthogonal to the gate lines 18g, a second conductive layer 20j and a third conductive layer 20k are shared, and a first conductive layer 12c electrically connected to the second conductive layer 20j and the third conductive layer 20k are also shared. Additionally, among the plurality of first conductive layers 12c disposed along the direction that intersects (orthogonally) with the gate lines 18g, the first conductive layer 12c at the substrate end is grounded.

[0108] The protective element Gb described above is configured such that when static electricity accumulated along the longer gate lines 18g that cut across the display area D enters through the second conductive layer 20j and the third conductive layer 20k, which are provided as lightning rods, and a voltage above the threshold for TFT operation is applied to each gate line 18g, the first source region 16ba and the first drain region 16bb are connected. Thus, the second conductive layer 20j and the third conductive layer 20k are connected via the third semiconductor layer 16b, and the static electricity entering the second conductive layer 20j and the third conductive layer 20k is removed via the outermost first conductive layer 12c. Here, the protective element Gb is not electrically connected to any components that contribute to the actual operation of the organic EL display device 50b, and therefore does not affect the actual operation of the organic EL display device 50b. Furthermore, the protective element Gb can physically block moisture entering along each gate line 18g, thus suppressing the intrusion of moisture from the outside into the display area D.

[0109] The organic EL display device 50b with the above structure is similar to the organic EL display device 50a of the first embodiment, and is flexible. In each sub-pixel P, the light-emitting layer 3 of the organic EL layer 33 is appropriately illuminated via the TFT 9a in the first pixel and the TFT 9b in the second pixel to display an image.

[0110] The organic EL display device 50b of this embodiment can be manufactured by changing the pattern shape of the first conductive layer 12b, the second conductive layer 20h, and the third conductive layer 20i in the TFT layer formation process of the manufacturing method of the organic EL display device 50a of the first embodiment described above.

[0111] As explained above, in the organic EL display device 50b according to this embodiment, a plurality of protective elements Gb are provided along each gate line 18g on the display area D side of the driving circuit M in the bezel area F. Here, the protective element Gb includes: a pair of first conductive layers 12c disposed on the substrate coating film 11, a third semiconductor layer 16b disposed on the pair of first conductive layers 12c separated by a fifth inorganic insulating film 13b, and a second conductive layer 20j and a third conductive layer 20k disposed on a second interlayer insulating film 19 in a mutually separated manner. Furthermore, the protection element Gb is configured such that static electricity accumulated along each gate line 18g enters through the second conductive layer 20j and the third conductive layer 20k, which are provided as lightning rods. When a voltage exceeding a threshold is applied to each gate line 18g, conduction occurs between the first source region 16ba and the first drain region 16bb. This conducts through the third semiconductor layer 16b, and the static electricity entering the second conductive layer 20j and the third conductive layer 20k is discharged through the outermost first conductive layer 12c. In addition, the protection element Gb can physically block moisture entering along each gate line 18g, thus suppressing moisture intrusion from the outside into the display area D. Therefore, the degradation of the characteristics of the first pixel TFT 9a and the second pixel TFT 9b of the oxide semiconductor caused by electrostatic discharge and moisture intrusion can be suppressed.

[0112] Other implementation methods

[0113] In the above embodiments, an organic EL layer with a five-layer stacked structure of hole injection layer, hole transport layer, light emission layer, electron transport layer and electron injection layer is shown. However, the organic EL layer may also be a three-layer stacked structure of hole injection layer as hole transport layer, light emission layer and electron transport layer as electron injection layer.

[0114] Furthermore, in the above embodiments, an organic EL display device is illustrated with the first electrode as the anode and the second electrode as the cathode. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, with the first electrode as the cathode and the second electrode as the anode.

[0115] Furthermore, in the above embodiments, an organic EL display device is illustrated in which the electrode of the TFT connected to the first electrode is used as the drain electrode. However, the present invention can also be applied to organic EL display devices in which the electrode of the TFT connected to the first electrode is used as the source electrode.

[0116] Furthermore, in the above embodiments, an organic EL display device was described as an example of a display device, but the present invention can be applied to display devices having multiple light-emitting elements driven by current, for example, to display devices having light-emitting elements having a layer of quantum dots, i.e., QLED (Quantum-dot light emitting diode).

[0117] Industrial availability

[0118] As described above, the present invention is useful for high-precision, small-sized display devices, such as those used in HMD (Head Mounted Display) applications.

[0119] Explanation of reference numerals in the attached figures

[0120] D: Display area

[0121] F: Border area

[0122] Ga, Gaa, Gb: Protective elements

[0123] M: Drive circuit (peripheral circuit)

[0124] P: Subpixel

[0125] 9a: In-pixel TFT (Thin Film Transistor)

[0126] 9b: In-pixel TFT (Thin Film Transistor)

[0127] 9d: External TFT (External Thin Film Transistor)

[0128] 10: Resin substrate (base substrate)

[0129] 12a: First semiconductor layer

[0130] 12aa: Third source region

[0131] 12ab: Third drain region

[0132] 13: First gate insulating film

[0133] 13a, 13b: Fifth inorganic insulating film

[0134] 14a: Second gate

[0135] 15: First interlayer insulating film

[0136] 16a: Second semiconductor layer

[0137] 16aa: Second source region

[0138] 16ab: Second drain region

[0139] 16b: Third semiconductor layer

[0140] 16ba: First source region

[0141] 16bb: First drain region

[0142] 16bc: First trench area

[0143] 17: Second gate insulating film

[0144] 18a: First gate

[0145] 18g: Gate line (display wiring)

[0146] 19: Second interlayer insulating film

[0147] 20a: First source pole

[0148] 20b: First drain electrode

[0149] 20c: Second source

[0150] 20d: Second drain electrode

[0151] 20h: Second conductive layer (third conductive layer)

[0152] 20i: Third conductive layer (second conductive layer)

[0153] 21: Protective insulating film

[0154] 22: Planarization film

[0155] 30: TFT layer (Thin Film Transistor layer)

[0156] 31a: First electrode

[0157] 33: Organic EL layer (organic electroluminescent layer, light-emitting functional layer)

[0158] 34: Second electrode

[0159] 40: Organic EL element layer (light-emitting element layer)

[0160] 45: Sealing membrane

[0161] 50a, 50aa, 50b: Organic EL display devices

Claims

1. A display device comprising: Substrate; as well as A thin-film transistor layer is disposed on the substrate, and the thin-film transistor layer comprises, in sequence: a first semiconductor film made of polycrystalline silicon; a first gate insulating film made of a first inorganic insulating film; a first metal film; a first interlayer insulating film made of a second inorganic insulating film; a second semiconductor film made of oxide semiconductor; a second gate insulating film made of a third inorganic insulating film; a second metal film; a second interlayer insulating film made of a fourth inorganic insulating film; a third metal film; and a planarization film made of an organic resin material. The thin-film transistor layer includes: Multiple display wirings are provided by the second metal film in a manner that extends in parallel to each other; Multiple thin-film transistors within pixels are disposed corresponding to multiple sub-pixels constituting the display area; and Multiple pixel-external thin-film transistors are configured as peripheral circuitry in the bezel area surrounding the display area. The thin-film transistor within each pixel has a second semiconductor layer formed by the second semiconductor film, and the thin-film transistor outside each pixel has a first semiconductor layer formed by the first semiconductor film. The display device is characterized in that... On the display area side of the peripheral circuit in the frame region, a protective element is provided along each display wiring, the protective element comprising: A first conductive layer is formed from the first semiconductor film and is conductive; The third semiconductor layer is formed by the second semiconductor film and is separated from the first conductive layer by a fifth inorganic insulating film. The third semiconductor layer has a first source region and a first drain region defined in a mutually separated manner, and a first channel region is defined between the first source region and the first drain region. A second conductive layer and a third conductive layer are formed separately from each other through the third metal film, and the first conductive layer is electrically connected to the first source region and the first drain region. The first channel region is configured to overlap with each of the display wirings.

2. The display device according to claim 1, characterized in that, The first conductive layer is integrally formed with a portion electrically connected to the second conductive layer and a portion electrically connected to the third conductive layer, overlapping the first channel region.

3. The display device according to claim 2, characterized in that, Multiple protective elements are provided along each of the display wirings. The first conductive layer is commonly disposed in multiple of the protective elements.

4. The display device according to claim 1, characterized in that, The first conductive layer is configured to have one side electrically connected to the second conductive layer and one side electrically connected to the third conductive layer.

5. The display device according to claim 4, characterized in that, Multiple protective elements are provided along each of the display wirings. The protective elements provided on one side of an adjacent pair of display wirings and the protective elements provided on the other side of the adjacent pair of display wirings are arranged adjacent to each other in a direction that intersects with the display wirings. In the adjacent pair of protective elements, the second conductive layer and the third conductive layer are shared, and the first conductive layer electrically connected to the second conductive layer and the first conductive layer electrically connected to the third conductive layer are also shared. The first conductive layer is grounded.

6. The display device according to any one of claims 1 to 5, characterized in that, Each pixel contains a thin-film transistor including: The second semiconductor layer has a second source region and a second drain region defined in a mutually separated manner. A first gate, which is disposed on the second semiconductor layer, separated from the second gate insulating film and formed by the second metal film; and A first source and a first drain are disposed on the second interlayer insulating film through the third metal film in a mutually separate manner, and are electrically connected to the second source region and the second drain region, respectively.

7. The display device according to any one of claims 1 to 5, characterized in that, Each pixel-external thin-film transistor includes: The first semiconductor layer has a third source region and a third drain region defined in a mutually separated manner. A second gate, which is disposed on the first semiconductor layer, separated from the first gate insulating film, and by the first metal film; and The second source and the second drain are disposed on the second interlayer insulating film by the third metal film in a mutually separate manner, and are electrically connected to the third source region and the third drain region, respectively.

8. The display device according to any one of claims 1 to 5, characterized in that, The wiring for each display is a gate line.

9. The display device according to any one of claims 1 to 5, characterized in that, A protective insulating film is provided between the third metal film and the planarization film, and the protective insulating film is composed of a sixth inorganic insulating film.

10. The display device according to any one of claims 1 to 5, characterized in that, The display device includes: A light-emitting element layer, disposed on the thin-film transistor layer, wherein a plurality of first electrodes, a plurality of light-emitting functional layers, and a common second electrode are sequentially stacked corresponding to the plurality of sub-pixels; and A sealing film is provided in a manner that covers the light-emitting element layer.

11. The display device according to claim 10, characterized in that, Each of the light-emitting functional layers is an organic electroluminescent layer.

Images