Array substrate, display panel and display device

Abstract

The application belongs to the field of display, and particularly relates to an array substrate, a display panel and a display device. The array substrate comprises n rows of scanning lines, m columns of data lines, a plurality of arrayed pixel driving circuits, n rows of gate driving circuits and n rows of first pull-up modules. The gate driving circuit of the 2k-1th row is connected with the first end of the scanning line, the gate driving circuit of the 2kth row is connected with the second end of the scanning line, the gate driving circuit is used for outputting the clock signal of the current row to the scanning line and the stage transmission signal to the gate driving circuit of the next stage, the first pull-up module of the 2k-1th row is connected with the second end of the scanning line, the first pull-up module circuit of the 2kth row is connected with the first end of the scanning line, and the first pull-up module is used for responding to the control signal of the gate driving circuit of the next stage and outputting the clock signal of the current row to the scanning line. The scanning signals output to both ends of the scanning line are generated by the same clock signal, the waveform difference of the scanning signals Gn at both ends of the scanning line is reduced or eliminated, and the display effect of the display panel is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] A display panel includes a liquid crystal display (LCD) panel and an organic light emitting diode (OLED) display panel. The display panel includes pixel units arranged in an array. After a gate drive circuit provides a scanning signal on a corresponding scanning line, all transistors connected to the scanning line are switched to an open state, so that each pixel unit on the scanning line receives a display signal from a respective connected data line and controls the brightness of different pixel units according to the display signal, thereby realizing the display of a row of pixels. The gate drive circuit includes a gate driver on array (GOA) circuit.

[0003] The existing display panel has a single-sided arrangement of the gate drive circuit and single-side driving. Compared with double-sided double driving, i.e., the gate drive circuit is arranged on both sides of each row of pixel units, the single-side driving of the gate drive circuit reduces the number of devices by half, which is conducive to realizing a narrow frame.

[0004] However, the single-sided arrangement of the gate drive circuit and the single-side driving have the following problems. The scanning signal near the gate drive circuit is a better square wave, and the rising edge time Tr and the falling edge time Tf are relatively small. After passing through the display area, as the distance increases, the impedance becomes larger and larger, and the rising edge time Tr and the falling edge time Tf of the output scanning signal waveform also become larger and larger. Due to the difference between the scanning signal waveforms near and far from the gate drive circuit, the charging rates of the pixel units near and far from the gate drive circuit also differ, and the edge of the display panel will form stripes with alternating light and dark, which is particularly obvious for a fish screen and a high refresh rate display panel. SUMMARY

[0005] The present application aims to provide an array substrate, a display panel and a display device to reduce or eliminate the difference between the scanning signal waveforms near and far from the gate drive circuit and improve the display effect of the display panel.

[0006] To achieve the above-mentioned purpose, the present application provides an array substrate, including n rows of scanning lines, m columns of data lines and a plurality of pixel drive circuits arranged in an array, the pixel drive circuits correspond one by one to the intersection points of the scanning lines and the data lines, the pixel drive circuits are connected to the scanning lines in the same row and the data lines in the same column, n and m are integers greater than or equal to 1, and the array substrate includes:

[0007] The gate driving circuit is connected with the first end of the scan line in the 2k-1th row and connected with the second end of the scan line in the 2kth row, and is used for outputting the clock signal of the current row to the scan line and outputting the stage transmission signal to the gate driving circuit in the next stage, k is an integer greater than or equal to 1;

[0008] The first pull-up module is connected with the second end of the scan line in the 2k-1th row and connected with the first end of the scan line in the 2kth row, and is used for outputting the clock signal of the current row to the scan line in response to the control signal of the gate driving circuit in the next stage.

[0009] Optionally, the gate driving circuit comprises a pull-up control module, a pull-up stage transmission module and a second pull-up module, the pull-up control module, the pull-up stage transmission module and the second pull-up module are all connected with the first node, the pull-up control module is used for pulling the voltage of the first node to the voltage of the first voltage end in response to the start signal, the start signal comprises the stage transmission signal of the gate driving circuit in the previous a stage, a is greater than or equal to 2, the pull-up stage transmission module is used for outputting the clock signal of the current row to the stage transmission signal end in response to the voltage of the first node, the stage transmission signal end outputs the stage transmission signal, the second pull-up module is used for outputting the clock signal of the current row to the first scan signal end in response to the voltage of the first node, the first scan signal end outputs the scan signal, the scan line is connected with the first scan signal end, and the control signal of the gate driving circuit in the next stage comprises the voltage of the first node.

[0010] Optionally, the array substrate further comprises two groups of clock signal lines, the two groups of clock signal lines are arranged on two sides of the array substrate respectively, the gate driving circuit or the first pull-up module is connected with the clock signal line away from the side of the scan line, each group of clock signal lines comprises 4p clock signal lines, p is an integer greater than or equal to 1, the first pull-up module in the 4p-bth row and the gate driving circuit in the 4p-bth row are connected with the 4p-bth clock signal line, b is an integer greater than or equal to 1 and less than 4p, and the control signal of the gate driving circuit in the next stage of the first pull-up module comprises at least the voltage of the first node in the next stage.

[0011] Optionally, p is equal to 2, the control signal of the gate driving circuit in the next stage of the first pull-up module comprises the voltage of the first node in the next stage and the voltage of the first node in the third next stage.

[0012] Optionally, the pull-up control module comprises a first transistor, a control end of the first transistor is connected with the start signal end, the start signal end outputs the start signal, a first end of the first transistor is connected with the first voltage end, and a second end of the first transistor is connected with the first node.

[0013] The pull-up stage transmission module comprises an eleventh transistor, a control end of the eleventh transistor is connected with the first node, a first end of the eleventh transistor is connected with the clock signal line of the current row, and a second end of the eleventh transistor is connected with the stage transmission signal end.

[0014] The second pull-up module comprises a tenth transistor and a bootstrap capacitor, a control end of the tenth transistor is connected with the first node, a first end of the tenth transistor is connected with the clock signal line of the current row, a second end of the tenth transistor is connected with the first scan signal end, and the bootstrap capacitor is connected with the first node and the first scan signal end.

[0015] Optionally, the first pull-up module comprises a fifteenth transistor, a control end of the fifteenth transistor is connected with the first node of the gate drive circuit of the next stage, a first end of the fifteenth transistor is connected with the clock signal line of the current row, a second end of the fifteenth transistor is connected with a second scan signal end, the second scan signal end outputs the scan signal, and the scan line is connected with the second scan signal end.

[0016] Optionally, the gate drive circuit further comprises a pull-down reset module, a pull-down maintenance module and a frame reset module, the pull-down reset module is used for responding to a reset signal and pulling the voltage of the first node to the voltage of a second voltage end, the reset signal comprises the stage transmission signal of the gate drive circuit of the next c stage, c is greater than or equal to 2, the pull-down maintenance module is used for responding to the voltage of the first node and pulling the first node, the stage transmission signal end and the first scan signal end to the voltage of the second voltage end, and the frame reset module is used for responding to a frame reset signal and pulling the first node, the stage transmission signal end and the first scan signal end to the voltage of the second voltage end.

[0017] Optionally, the pull-down reset module comprises a ninth transistor, a control end of the ninth transistor is connected with a reset signal end, the reset signal end outputs the reset signal, a first end of the ninth transistor is connected with the first node, and a second end of the ninth transistor is connected with the second voltage end.

[0018] The pull-down maintaining module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a fourteenth transistor, a control end of the fifth transistor is connected with the first voltage end, a first end of the fifth transistor is connected with the first voltage end, a second end of the fifth transistor is connected with a second node, a control end of the sixth transistor is connected with the first node, a first end of the sixth transistor is connected with the second node, a second end of the sixth transistor is connected with the second voltage end, a control end of the seventh transistor is connected with a start signal end, a first end of the seventh transistor is connected with the second node, a second end of the seventh transistor is connected with the second voltage end, a control end of the eighth transistor is connected with the second node, a first end of the eighth transistor is connected with the first node, a second end of the eighth transistor is connected with the second voltage end, a control end of the thirteenth transistor is connected with the second node, a first end of the thirteenth transistor is connected with a stage transmission signal end, a second end of the thirteenth transistor is connected with the second voltage end, a control end of the fourteenth transistor is connected with the second node, a first end of the fourteenth transistor is connected with the first scanning signal end, and a second end of the fourteenth transistor is connected with the second voltage end.

[0019] The frame reset module comprises a second transistor, a fourth transistor, a twelfth transistor and a third transistor, a control end of the second transistor is connected with a frame reset end, the frame reset end outputs a frame reset signal, a first end of the second transistor is connected with the first node, a second end of the second transistor is connected with the second voltage end, a control end of the fourth transistor is connected with the frame reset end, a first end of the fourth transistor is connected with the stage transmission signal end, a second end of the fourth transistor is connected with the second voltage end, a control end of the twelfth transistor is connected with the frame reset end, a first end of the twelfth transistor is connected with the first scanning signal end, a second end of the twelfth transistor is connected with the second voltage end, and a control end of the third transistor is connected with the frame reset end, a first end of the third transistor is connected with the second node, and a second end of the third transistor is connected with the second voltage end.

[0020] The application further provides a display panel, comprising:

[0021] The array substrate;

[0022] A pixel structure layer is formed on the array substrate, the pixel structure layer comprises a plurality of pixel units arranged in an array, and pixel driving circuits of the array substrate are connected with the pixel units one by one.

[0023] The application further provides a display device, comprising:

[0024] the display panel;

[0025] a main board connected with the display panel.

[0026] The array substrate, the display panel and the display device disclosed by the present application have the following beneficial effects:

[0027] In the present application, the array substrate comprises n rows of scan lines, m columns of data lines, a plurality of arrayed pixel driving circuits, n rows of gate driving circuits and n rows of first pull-up modules, the pixel driving circuit is connected with the scan line in the same row and the data line in the same column, the gate driving circuit in the 2k-1th row is connected with the first end of the scan line, the gate driving circuit in the 2kth row is connected with the second end of the scan line, the gate driving circuit is used for outputting the clock signal CK of the current row to generate the scan signal Gn at one end of the current row and outputting the stage transmission signal Tn, the first pull-up module is used for outputting the clock signal CK of the current row to generate the scan signal Gn at the other end of the current row, the scan signals Gn output to both ends of the scan line are generated by the same clock signal CK, the rising edge time Tr and the falling edge time Tf have a small difference, compared with the single-side driving scheme of the gate driving circuit, the waveform difference of the scan signals Gn at both ends of the scan line is reduced or eliminated, and the display effect of the display panel is improved.

[0028] Other characteristics and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0029] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0030] The drawings herein are incorporated into the specification and form a part of the specification, show embodiments consistent with the present application, and together with the specification serve to explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0031] Figure 1 is a structural schematic diagram of the array substrate in embodiment one of the present application.

[0032] Figure 2 is a structural schematic diagram of the gate driving circuit in embodiment one of the present application.

[0033] Figure 3 is a variation schematic diagram of the scan signal waveform in embodiment one of the present application.

[0034] Figure 4 is a structural schematic diagram of the gate driving circuit in embodiment one of the present application.

[0035] Figure 5 Fig. 1 is a schematic diagram of a gate drive circuit and a first pull-up module connected in an embodiment of the present application.

[0036] Figure 6 Fig. 2 is a timing diagram of partial signals of the gate drive circuit in the embodiment of the present application.

[0037] Figure 7 Fig. 3 is a schematic diagram of a display panel in an embodiment of the present application.

[0038] Figure 8 Fig. 4 is a schematic diagram of a display device in an embodiment of the present application.

[0039] Legend of signs:

[0040] 100, array substrate; 101, scan line; 102, data line; 103, clock signal line; 120, pixel drive circuit; 130, gate drive circuit; 131, pull-up control module; 132, pull-up stage transmission module; 133, second pull-up module; 134, pull-down reset module; 135, pull-down maintenance module; 136, frame post-reset module; 140, first pull-up module; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; M8, eighth transistor; M9, ninth transistor; M10, tenth transistor; M11, eleventh transistor; M12, twelfth transistor; M13, thirteenth transistor; M14, fourteenth transistor; M15, fifteenth transistor; C1, bootstrap capacitor;

[0041] 200, counter substrate; 300, liquid crystal layer;

[0042] 10, display panel; 20, main board. DETAILED DESCRIPTION

[0043] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any

[0044] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0045] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0046] Example 1

[0047] See Figure 1 and Figure 2 As shown, in this embodiment, the array substrate 100 includes n rows of scan lines 101, m columns of data lines 102, and multiple arrayed pixel driving circuits 120. The pixel driving circuits 120 correspond one-to-one with the intersections of the scan lines 101 and the data lines 102, and are connected to the scan lines 101 in their respective rows and the data lines 102 in their respective columns. n and m are integers greater than or equal to 1.

[0048] The array substrate 100 also includes n rows of gate driving circuits, each including a gate driving circuit 130 and a first pull-up module 140. The gate driving circuit 130 in row 2k-1 is connected to the first end of scan line 101, and the gate driving circuit 130 in row 2k is connected to the second end of scan line 101, where k is an integer greater than or equal to 1. The gate driving circuit 130 outputs the clock signal CK of the current row to scan line 101, generating a scan signal Gn at one end of the current row. The gate driving circuit 130 also outputs a stage transmission signal Tn to the subsequent gate driving circuit 130. The first pull-up module 140 in row 2k-1 is connected to the second end of scan line 101, and the first pull-up module 140 in row 2k is connected to the first end of scan line 101. The first pull-up module 140 responds to the control signal of the subsequent gate driving circuit 130 and outputs the clock signal CK of the current row to scan line 101, generating a scan signal Gn at the other end of the current row. The control signal for controlling the first pull-up module 140 is specifically provided by the subsequent gate drive circuits 130, depending on the number of clock signals CK.

[0049] In some technical solutions, the gate driving circuit 130 is arranged on one side, and the gate driving circuit 130 is unilaterally driven. The scanning signal Gn near the gate driving circuit 130 is a better square wave, and the rising edge time Tr and the falling edge time Tf are both relatively small. After passing through the display area, as the distance increases, the impedance becomes larger and larger, and the rising edge time Tr and the falling edge time Tf of the output scanning signal Gn waveform also become larger and larger, as shown in FIG. 11. Figure 3 Due to the difference between the scanning signal Gn waveforms near and far from the gate driving circuit 130, that is, the difference between the scanning signal Gn waveforms at both ends of the scanning line 101, the charging rates of the pixel units near and far from the gate driving circuit 130 are also different. Such alternating driving causes the formation of stripes with alternating brightness at the edges of the display panel, which is particularly obvious for fish screen display panels and high refresh rate display panels.

[0050] In the embodiment, the array substrate 100 includes n rows of scanning lines 101, m columns of data lines 102, a plurality of array arranged pixel driving circuits 120, n rows of gate driving circuits 130, and n rows of first pull-up modules 140. The pixel driving circuit 120 is connected with the scanning line 101 in the same row and the data line 102 in the same column. The gate driving circuit 130 in the 2k-1 row is connected with the first end of the scanning line 101, and the gate driving circuit 130 in the 2k row is connected with the second end of the scanning line 101. The gate driving circuit 130 is used to output the clock signal CK of the current row to generate the scanning signal Gn at one end of the current row and output the stage transmission signal Tn. The first pull-up module 140 is used to output the clock signal CK of the current row to generate the scanning signal Gn at the other end of the current row. The scanning signal Gn output to both ends of the scanning line 101 is generated by the same clock signal CK, and the difference between the rising edge time Tr and the falling edge time Tf is small. Compared with the scheme of unilateral driving of the gate driving circuit 130, the difference between the scanning signal Gn waveforms at both ends of the scanning line 101 is reduced or eliminated, and the display effect of the display panel is improved.

[0051] In addition, the gate driving circuit 130 includes a pull-up control module 131, a pull-up stage transmission module 132, and a second pull-up module 133. In the present application, one end of the scanning line 101 of the array substrate 100 is the gate driving circuit 130, and the other end of the scanning line 101 is the first pull-up module 140. One first pull-up module 140 is used instead of the gate driving circuit 130. Compared with the scheme of bilateral arrangement and bilateral driving of the gate driving circuit 130, about half of the devices can be reduced, the gate driving circuit structure is simplified, and the manufacturing cost of the array substrate 100 is reduced.

[0052] Referring to Figure 4 and Figure 5As shown, the gate drive circuit 130 comprises a pull-up control module 131, a pull-up stage transmission module 132 and a second pull-up module 133, and the pull-up control module 131, the pull-up stage transmission module 132 and the second pull-up module 133 are connected with the first node PU. The pull-up control module 131 is used for responding to a start signal input and pulling the voltage of the first node PU to the voltage of the first voltage terminal VGH. The start signal comprises a stage transmission signal of a gate drive circuit 130 in front a stages, and a is greater than or equal to 2.

[0053] The pull-up stage transmission module 132 is used for responding to the voltage of the first node PU and outputting the clock signal CK of the current row to a stage transmission signal terminal, and the stage transmission signal terminal outputs a stage transmission signal Tn. The second pull-up module 132 is used for responding to the voltage of the first node PU and outputting the clock signal CK of the current row to a first scanning signal terminal, and the first scanning signal terminal outputs a scanning signal Gn, and the scanning line 101 is connected with the first scanning signal terminal. The control signal of the gate drive circuit 130 in the rear stage comprises the voltage of the first node PU, that is, the first pull-up module 140 is used for responding to the voltage of the first node PU of the gate drive circuit 130 in the rear stage and outputting the clock signal CK of the current row to the scanning line 101. For example, the first pull-up module 140 of the n-1th row responds to the voltage of the first node PUn of the gate drive circuit 130 of the nth row and outputs the clock signal CK of the n-1th row to the scanning line 101 of the n-1th row; the first pull-up module 140 of the nth row responds to the voltage of the first node PUn+1 of the gate drive circuit 130 of the n+1th row and outputs the clock signal CK of the nth row to the scanning line 101 of the nth row.

[0054] a is a parameter related to the number of clock signal lines 103, and the clock signal line 103 outputs the clock signal CK. For example, the array substrate 100 has two groups of clock signal lines 103, each group of clock signal lines 103 has 8 clock signal lines 103, and the start signal input is Tn-4, and n is greater than or equal to 5. For the gate drive circuit 130 in the front four stages, the start signal input is the frame start signal STV.

[0055] The control signal of the gate drive circuit 130 in the rear stage comprises the voltage of the first node PU, that is, the first pull-up module 140 in the front stage is controlled by the voltage of the first node PU of the gate drive circuit 130 in the rear stage, and the gate drive circuit 130 does not increase an additional control module, thereby simplifying the structure of the gate drive circuit 130 and being beneficial to reducing the manufacturing cost of the array substrate 100.

[0056] Referring to Figure 2 , Figure 4 and Figure 5As shown, the array substrate 100 includes two groups of clock signal lines 103, which are arranged on both sides of the array substrate 100. The gate driving circuit 130 or the first pull-up module 140 is connected with the clock signal line 103 away from the scanning line 101. Each group of clock signal lines 103 includes 4p clock signal lines 103, where p is an integer greater than or equal to 1. The first pull-up module 140 of the 4p-b row is connected with the 4p-b clock signal line 103, and b is an integer greater than or equal to 1 and less than 4p. The control signal of the gate driving circuit 130 at the rear stage of the first pull-up module 140 at least includes the first node PU voltage of the rear stage.

[0057] The two groups of clock signal lines 103 are arranged on both sides of the array substrate 100, which facilitates the gate driving circuit 130 and the first pull-up module 140 to be connected with the clock signal line 103 nearby.

[0058] For example, p is equal to 2, that is, each group of clock signal lines 103 includes 8 clock signal lines 103, and the 8 clock signal lines 103 output 8 clock signals CK, which are CK1-CK8 respectively. The clock signals CK output by each group of clock signal lines 103 are the same. The first pull-up module 140 of the 1st row is connected with the 1st clock signal line 103, the first pull-up module 140 of the 2nd row is connected with the 2nd clock signal line 103, and so on, and the first pull-up module 140 of the 8th row is connected with the 8th clock signal line 103. The first pull-up module 140 of the 9th row is connected with the 1st clock signal line 103, and the like. The control signal of the gate driving circuit 130 at the rear stage of the first pull-up module 140 includes the first node PU voltage of the rear stage and the first node PU voltage of the third stage, that is, the first pull-up module 140 of the nth row responds to the first node PUn+1 voltage of the gate driving circuit 130 of the n+1th row or the first node PUn+3 voltage of the gate driving circuit 130 of the n+3th row and the clock signal CK of the nth row to the scanning line 101 of the nth row. Preferably, the control signal for controlling the first pull-up module 140 is the first node PU voltage of the gate driving circuit 130 at the rear stage.

[0059] Each group of clock signal lines 103 includes 8 clock signal lines 103, that is, an 8CK design is adopted, which is beneficial to reduce the load and realize pre-charging. The control signal for controlling the first pull-up module 140 is the first node PU voltage of the gate driving circuit 130 at the rear stage, and in this design, the wiring between the first pull-up module 140 and the gate driving circuit 130 at the rear stage thereof is shorter.

[0060] Referring to Figure 4 and Figure 5As shown, the pull-up control module 131 includes a first transistor M1. The control end of the first transistor M1 is connected with a start signal end, the start signal end outputs a start signal input, the first end of the first transistor M1 is connected with a first voltage end, and the second end of the first transistor M1 is connected with a first node PU. The pull-up stage transmission module 132 includes an eleventh transistor M11. The control end of the eleventh transistor M11 is connected with the first node PU, the first end of the eleventh transistor M11 is connected with the clock signal line 103 of the current row, and the second end of the eleventh transistor M11 is connected with a stage transmission signal end.

[0061] The second pull-up module 133 includes a tenth transistor M10 and a bootstrap capacitor C1. The control end of the tenth transistor M10 is connected with the first node PU, the first end of the tenth transistor M10 is connected with the clock signal line 103 of the current row, and the second end of the tenth transistor M10 is connected with a first scan signal end. The bootstrap capacitor C1 is connected with the first node PU and the first scan signal end.

[0062] The gate drive circuit 130 includes the pull-up control module 131, the pull-up stage transmission module 132 and the second pull-up module 133. The pull-up control module 131 controls the pull-up stage transmission module 132 and the second pull-up module 133 to output the stage transmission signal Tn and the scan signal Gn. The first node PU voltage generated in the working of the gate drive circuit 130 is used to control the first pull-up module 140 of the previous stage. The gate drive circuit 130 does not increase an additional control module, simplifies the structure of the gate drive circuit 130, and is conducive to reducing the manufacturing cost of the array substrate 100.

[0063] Referring to Figure 4 and Figure 5 As shown, the first pull-up module 140 includes a fifteenth transistor M15. The control end of the fifteenth transistor M15 is connected with the first node PU of the gate drive circuit 130 of the next stage, the first end of the fifteenth transistor M15 is connected with the clock signal line 103 of the current row, the second end of the fifteenth transistor M15 is connected with a second scan signal end, the second scan signal end outputs the scan signal Gn, and the scan line 101 is connected with the second scan signal end.

[0064] The first pull-up module 140 includes the fifteenth transistor M15, that is, the double-side driving can be realized by the gate drive circuit 130 and one transistor. Compared with the scheme that the gate drive circuit 130 is arranged on both sides and double-side driving, about half of the devices can be reduced, the structure of the gate drive circuit is simplified, and the manufacturing cost of the array substrate 100 is reduced.

[0065] In some embodiments, the gate driving circuit 130 further comprises a pull-down reset module 134, a pull-down maintaining module 135 and a frame reset module 136. The pull-down reset module 134 is configured to pull the first node PU to a second voltage terminal voltage VSS in response to a reset signal reset, the second voltage terminal voltage VSS being less than a first voltage terminal voltage VGH. The reset signal reset comprises a stage transfer signal Tn of a c-th stage gate driving circuit 130, c being greater than or equal to 2.

[0066] The pull-down maintaining module 135 is configured to pull the first node PU, the stage transfer signal terminal and the first scan signal terminal to the second voltage terminal voltage VSS in response to the first node PU voltage. The frame reset module 136 is configured to pull the first node PU, the stage transfer signal terminal and the first scan signal terminal to the second voltage terminal voltage VSS in response to a frame reset signal CLR.

[0067] c is a parameter related to the number of clock signal lines 103 outputting clock signals CK. For example, the array substrate 100 has two groups of clock signal lines 103, each group of clock signal lines 103 has 8 clock signal lines 103, and the reset signal reset is Tn+6. For the gate driving circuit 130 of the last six stages, the reset signal reset is the frame reset signal CLR.

[0068] The pull-down reset module 134 can clear the first node PU charge at the end of the current row scanning, and the frame reset module 136 can clear the first node PU, the stage transfer signal terminal and the first scan signal terminal charge in the frame blanking area before the end of the current frame and the start of the next frame.

[0069] It should be noted that the gate driving circuit 130 can be provided with two pull-down maintaining modules 135, which are controlled by two low-frequency clock signals LC and work alternately to prolong the service life of the pull-down maintaining module 135.

[0070] In some embodiments, the pull-down reset module 134 comprises a ninth transistor M9. The control terminal of the ninth transistor M9 is connected with a reset signal terminal outputting the reset signal reset, the first terminal of the ninth transistor M9 is connected with the first node PU, and the second terminal of the ninth transistor M9 is connected with a second voltage terminal.

[0071] The pull-down sustaining module 135 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a thirteenth transistor M13, and a fourteenth transistor M14. The control terminal of the fifth transistor M5 is connected to the first voltage terminal, its first terminal is connected to the first voltage terminal, and its second terminal is connected to the second node PD. The control terminal of the sixth transistor M6 is connected to the first node PU, its first terminal is connected to the second node PD, and its second terminal is connected to the second voltage terminal. The control terminal of the seventh transistor M7 is connected to the start signal terminal, its first terminal is connected to the second node PD, and its second terminal is connected to the second voltage terminal. The control terminal of the eighth transistor M8 is connected to the second node PD, its first terminal is connected to the first node PU, and its second terminal is connected to the second voltage terminal. The control terminal of the thirteenth transistor M13 is connected to the second node PD, its first terminal is connected to the stage signal terminal, and its second terminal is connected to the second voltage terminal. The control terminal of the fourteenth transistor M14 is connected to the second node PD, the first terminal of the fourteenth transistor M14 is connected to the first scan signal terminal, and the second terminal of the fourteenth transistor M14 is connected to the second voltage terminal.

[0072] The post-frame reset module 136 includes a second transistor M2, a fourth transistor M4, a twelfth transistor M12, and a third transistor M3. The control terminal of the second transistor M2 is connected to the post-frame reset terminal, which outputs a post-frame reset signal CLR. The first terminal of the second transistor M2 is connected to the first node PU, and the second terminal is connected to the second voltage terminal. The control terminal of the fourth transistor M4 is connected to the post-frame reset terminal. The first terminal of the fourth transistor M4 is connected to the stage signal terminal, and the second terminal is connected to the second voltage terminal. The control terminal of the twelfth transistor M12 is connected to the post-frame reset terminal. The first terminal of the twelfth transistor M12 is connected to the first scan signal terminal, and the second terminal is connected to the second voltage terminal. The control terminal of the third transistor M3 is connected to the post-frame reset terminal. The first terminal of the third transistor M3 is connected to the second node PD, and the second terminal is connected to the second voltage terminal.

[0073] Taking the gate drive circuit 130 in row 5 (n=5) as an example, such as Figure 6 As shown, its start signal (input) is the stage pass signal T1 in row 1, and its reset signal (reset) is the stage pass signal T11 in row 11. When the gate drive circuit is working:

[0074] In the first stage S1, the start signal input is a high level signal, the first transistor M1 and the seventh transistor M7 are opened, the first node PU potential becomes the first voltage terminal voltage VGH, the bootstrap capacitor C1 is charged, the voltage difference across the bootstrap capacitor C1 is VGH-VSS; the seventh transistor M7 is opened and the first node PU potential becomes a high level, so that the sixth transistor M6 is opened, the pull-down maintenance module 135 is not working, that is, the eighth transistor M8, the thirteenth transistor M13 and the fourteenth transistor M14 are closed; because the first node PU becomes a high level, the tenth transistor M10 and the eleventh transistor M11 are opened, and the clock signal CK5 of the clock signal line 103 connected with the tenth transistor M10 and the eleventh transistor M11 is a low level signal;

[0075] In the second stage S2, the start signal input is a low level signal, the first transistor M1 and the seventh transistor M7 are closed, and because of the energy storage function of the bootstrap capacitor C1, the first node PU is still a high level VGH, the sixth transistor M6 remains opened, and the pull-down maintenance module 135 is not working; the tenth transistor M10 and the eleventh transistor M11 remain opened, when the clock signal CK5 becomes a high level, the clock signal CK5 of the clock signal line 103 connected with the tenth transistor M10 writes a high level scanning signal G5, and the clock signal CK5 of the clock signal line 103 connected with the eleventh transistor M11 writes a high level transfer signal T5, because the voltage difference across the bootstrap capacitor C1 is unchanged, the first node PU voltage rises to be higher than VGH; when the clock signal CK5 becomes a low level, the scanning signal G5 and the transfer signal T5 become low levels, and the first node PU voltage is coupled to be pulled down to VGH;

[0076] In the third stage S3, the reset signal reset becomes a high level, the ninth transistor M9 is opened, the bootstrap capacitor C1 is discharged, the first node PU voltage is pulled down to VSS, the sixth transistor M6, the tenth transistor M10 and the eleventh transistor M11 are closed, the second node PD is pulled up to a high level VGH by the fifth transistor M5, and the pull-down maintenance module 135 starts to work, that is, the eighth transistor M8, the thirteenth transistor M13 and the fourteenth transistor M14 are opened, the transfer signal T5, the scanning signal G5 and the first node PU are maintained at a low level VSS.

[0077] Before the end of the current frame and the start of the next frame, the frame reset signal CLR becomes a high level VGH, the second transistor M2, the fourth transistor M4, the twelfth transistor M12 and the third transistor M3 are opened, the first node PU, the second node PD, the transfer signal end and the scanning signal end are pulled down to VSS by the second voltage terminal, the residual charge of the first node PU, the second node PD, the transfer signal end and the scanning signal end is cleared, and the reset of the entire circuit is realized.

[0078] In the operation of the gate drive circuit, the control signal of the fifteenth transistor M15 in the fifth row is the voltage of the first node PU6 of the gate drive circuit 130 in the sixth row, the voltage of the first node PU6 of the gate drive circuit 130 in the sixth row is 1H (1H=(1 / Freq-t) / n, where Freq is the frequency, t is the frame blanking area time, and n is the number of rows of the scan line 101) later than the voltage of the first node PU5 of the gate drive circuit 130 in the fifth row, but the high level interval of the clock signal CK5 coincides with the high level interval of the voltage of the first node PU6, the time of the tenth transistor M10 outputting high and low level signals is consistent with the time of the fifteenth transistor M15 outputting high and low level signals, that is, the waveforms of the scan signals Gn at both ends of the scan line 101 are consistent.

[0079] Embodiment Two

[0080] Referring to Figure 7 As shown in the figure, in this embodiment, the display panel includes an array substrate 100 and a pixel structure layer, and the pixel structure layer is formed on the array substrate 100. The pixel structure layer includes a plurality of pixel units arranged in an array, and the pixel driving circuit 120 of the array substrate 100 is connected to the pixel units one by one. The array substrate 100 includes the array substrate 100 disclosed in Embodiment One.

[0081] The display panel includes a liquid crystal display panel or an organic light-emitting diode display panel. When the display panel is a liquid crystal display panel, the display panel includes an array substrate 100, a counter substrate 200, and a liquid crystal layer 300 disposed between the array substrate 100 and the counter substrate 200. The array substrate 100 can include a pixel electrode layer, the counter substrate 200 can include a common electrode layer, and the pixel structure layer includes the pixel electrode layer, the liquid crystal layer 300, and the common electrode layer. When the display panel is an OLED display panel, the pixel definition layer of the display panel includes an anode layer, a pixel definition layer, an emitting layer, and a cathode layer formed in sequence on the array substrate 100.

[0082] The display panel comprises an array substrate 100, the array substrate 100 comprises n rows of scan lines 101, m columns of data lines 102, a plurality of array arranged pixel driving circuits 120, n rows of gate driving circuits 130 and n rows of first pull-up modules 140, the pixel driving circuit 120 is connected with the scan line 101 in the row and the data line 102 in the column, the gate driving circuit 130 of the 2k-1 row is connected with the first end of the scan line 101, the gate driving circuit 130 of the 2k row is connected with the second end of the scan line 101, the gate driving circuit 130 is used for outputting the clock signal CK of the current row to generate the scan signal Gn of one end of the current row and outputting the stage transmission signal Tn, the first pull-up module 140 is used for outputting the clock signal CK of the current row to generate the scan signal Gn of the other end of the current row, the scan signals Gn output to both ends of the scan line 101 are generated by the same clock signal CK, the rising edge time Tr and the falling edge time Tf have little difference, compared with the scheme of the single side driving of the gate driving circuit 130, the waveform difference of the scan signals Gn at both ends of the scan line 101 is reduced or eliminated, and the display effect of the display panel is improved.

[0083] Embodiment three

[0084] Referring to Figure 8 As shown in the figure, the display device in the embodiment comprises a display panel 10 and a mainboard 20, the mainboard 20 is connected with the display panel 10. The display panel 10 comprises the display panel 10 disclosed in embodiment two.

[0085] The display device comprises a display panel 10, the display panel 10 comprises an array substrate 100, the gate driving circuit 130 and the first pull-up module 140 in the array substrate 100 are arranged and driven on both sides, the waveform difference of the scan signals Gn at both ends of the scan line 101 is reduced or eliminated, and the display effect of the display device is improved.

[0086] The terms "first", "second", and the like are used only for descriptive purposes, and cannot be construed as indicating or implying relative importance or implying the number of the indicated technical features. Therefore, the features defined with "first", "second", and the like can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited and defined.

[0087] In the present application, unless otherwise specifically defined and limited, the terms "assembly", "connection" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For ordinary skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0088] In the description of the specification, the description of the terms "some embodiments", "exemplarily" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0089] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application. However, any changes or modifications made in accordance with the claims and specification of the present application shall be within the scope of the present application.

Claims

1. An array substrate, comprising n rows of scan lines, m columns of data lines, and a plurality of array-arranged pixel driving circuits, the pixel driving circuits corresponding one-to-one to intersections of the scan lines and the data lines, the pixel driving circuits being connected to the scan lines in the rows and the data lines in the columns, n and m being integers greater than or equal to 1, characterized in that, The array substrate comprises: a gate drive circuit, the gate drive circuit of the 2k-1th row is connected with the first end of the scan line, the gate drive circuit of the 2kth row is connected with the second end of the scan line, the gate drive circuit is used for outputting the clock signal of the current row to the scan line and outputting the stage transmission signal to the gate drive circuit of the next stage, k is an integer greater than or equal to 1; a first pull-up module, the first pull-up module of the 2k-1th row is connected with the second end of the scan line, the first pull-up module circuit of the 2kth row is connected with the first end of the scan line, and the first pull-up module is used for outputting the clock signal of the current row to the scan line in response to the control signal of the gate drive circuit of the next stage.

2. The array substrate of claim 1, wherein, The gate drive circuit comprises a pull-up control module, a pull-up stage transmission module and a second pull-up module, the pull-up control module, the pull-up stage transmission module and the second pull-up module are all connected with a first node, the pull-up control module is used for pulling the voltage of the first node to the voltage of a first voltage end in response to a start signal, the start signal comprises the stage transmission signal of the gate drive circuit of the previous a stage, a is greater than or equal to 2, the pull-up stage transmission module is used for outputting the clock signal of the current row to a stage transmission signal end in response to the voltage of the first node, the stage transmission signal end outputs the stage transmission signal, the second pull-up module is used for outputting the clock signal of the current row to a first scan signal end in response to the voltage of the first node, the first scan signal end outputs a scan signal, the scan line is connected with the first scan signal end, and the control signal of the gate drive circuit of the next stage comprises the voltage of the first node.

3. The array substrate of claim 2, wherein, The array substrate further comprises two groups of clock signal lines, the two groups of clock signal lines are arranged on two sides of the array substrate respectively, the gate drive circuit or the first pull-up module is connected with the clock signal line away from the side of the scan line, each group of clock signal lines comprises 4p clock signal lines, p is an integer greater than or equal to 1, the first pull-up module of the 4p-bth row and the gate drive circuit of the 4p-bth row are connected with the 4p-bth clock signal line, b is an integer greater than or equal to 1 and less than 4p, and the control signal of the gate drive circuit of the next stage of the first pull-up module comprises at least the voltage of the first node of the next stage.

4. The array substrate of claim 3, wherein, P is equal to 2, and the control signal of the gate drive circuit of the next stage of the first pull-up module comprises the voltage of the first node of the next stage and the voltage of the first node of the third next stage.

5. The array substrate of claim 2, wherein, The pull-up control module comprises a first transistor, the control end of the first transistor is connected with the start signal end, the start signal end outputs the start signal, the first end of the first transistor is connected with the first voltage end, and the second end of the first transistor is connected with the first node; The pull-up stage transmission module comprises an eleventh transistor, the control end of the eleventh transistor is connected with the first node, the first end of the eleventh transistor is connected with the clock signal line of the current row, and the second end of the eleventh transistor is connected with the stage transmission signal end; The pull-up stage transmission module comprises an eleventh transistor, the control end of the eleventh transistor is connected with the first node, the first end of the eleventh transistor is connected with the clock signal line of the current row, and the second end of the eleventh transistor is connected with the stage transmission signal end; The second pull-up module comprises a tenth transistor and a bootstrap capacitor, a control terminal of the tenth transistor is connected with the first node, a first terminal of the tenth transistor is connected with the clock signal line of the current row, a second terminal of the tenth transistor is connected with the first scan signal end, and the bootstrap capacitor is connected with the first node and the first scan signal end.

6. The array substrate according to claim 2 or 5, wherein, The first pull-up module comprises a fifteenth transistor, a control terminal of the fifteenth transistor is connected with the first node of the gate drive circuit in the next stage, a first terminal of the fifteenth transistor is connected with the clock signal line of the current row, and a second terminal of the fifteenth transistor is connected with a second scan signal end, wherein the second scan signal end outputs the scan signal, and the scan line is connected with the second scan signal end.

7. The array substrate of claim 2, wherein, The gate drive circuit further comprises a pull-down reset module, a pull-down maintenance module and a frame reset module, the pull-down reset module is used for pulling the voltage of the first node to the voltage of a second voltage end in response to a reset signal, the reset signal comprises the stage transmission signal of the gate drive circuit in the next stage, c is greater than or equal to 2, the pull-down maintenance module is used for pulling the first node, the stage transmission signal end and the first scan signal end to the voltage of the second voltage end in response to the voltage of the first node, and the frame reset module is used for pulling the first node, the stage transmission signal end and the first scan signal end to the voltage of the second voltage end in response to a frame reset signal.

8. The array substrate of claim 7, wherein, The pull-down reset module comprises a ninth transistor, a control terminal of the ninth transistor is connected with a reset signal end, the reset signal end outputs the reset signal, a first terminal of the ninth transistor is connected with the first node, and a second terminal of the ninth transistor is connected with the second voltage end. The pull-down maintenance module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a thirteenth transistor and a fourteenth transistor, a control terminal of the fifth transistor is connected with the first voltage end, a first terminal of the fifth transistor is connected with the first voltage end, a second terminal of the fifth transistor is connected with a second node, a control terminal of the sixth transistor is connected with the first node, a first terminal of the sixth transistor is connected with the second node, a second terminal of the sixth transistor is connected with the second voltage end, a control terminal of the seventh transistor is connected with a start signal end, a first terminal of the seventh transistor is connected with the second node, a second terminal of the seventh transistor is connected with the second voltage end, a control terminal of the eighth transistor is connected with the second node, a first terminal of the eighth transistor is connected with the first node, a second terminal of the eighth transistor is connected with the second voltage end, a control terminal of the thirteenth transistor is connected with the second node, a first terminal of the thirteenth transistor is connected with the stage transmission signal end, a second terminal of the thirteenth transistor is connected with the second voltage end, a control terminal of the fourteenth transistor is connected with the second node, a first terminal of the fourteenth transistor is connected with the first scan signal end, and a second terminal of the fourteenth transistor is connected with the second voltage end. The frame reset module comprises a second transistor, a fourth transistor, a twelfth transistor and a third transistor, the control end of the second transistor is connected with a frame reset end, the frame reset end outputs a frame reset signal, the first end of the second transistor is connected with the first node, the second end of the second transistor is connected with the second voltage end, the control end of the fourth transistor is connected with the frame reset end, the first end of the fourth transistor is connected with the stage transmission signal end, the second end of the fourth transistor is connected with the second voltage end, the control end of the twelfth transistor is connected with the frame reset end, the first end of the twelfth transistor is connected with the first scanning signal end, the second end of the twelfth transistor is connected with the second voltage end, the control end of the third transistor is connected with the frame reset end, the first end of the third transistor is connected with the second node, and the second end of the third transistor is connected with the second voltage end.

9. A display panel, characterized by, Comprise: The array substrate according to any one of claims 1-8; A pixel structure layer is formed on the array substrate, and the pixel structure layer comprises a plurality of pixel units arranged in an array, and pixel driving circuits of the array substrate are connected with the pixel units one by one.

10. A display device, characterized by comprising: Comprise: The display panel according to claim 9; A mainboard is connected with the display panel.

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