Intelligent lock communication control method, system and intelligent lock based on digital differential

Abstract

The object of the present invention is to disclose a smart lock communication control method, system and smart lock based on digital differential, which relates to the field of smart lock control technology, comprising the following steps: step S1: the MCU controller at the information sending end generates a data packet for controlling the smart lock; step S2: the MCU controller at the information sending end sends a synchronization packet header through a timer; step S3: the MCU controller at the information sending end encodes each bit of data in sequence according to a preset encoding period; step S4: the MCU controller at the information sending end sends the code in sequence through a timer interrupt program; step S5: the MCU controller at the information receiving end reads the code according to a preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%, if X%-Y%>0%, the code is interpreted as 1, and if X%-Y%<0%, the code is interpreted as 0; step S6: according to steps S3-S5, the transmission of several bits of data is realized in sequence and the data packet is sent, thereby achieving high reliability and stable transmission.

Description

Technical Field

[0001] The present invention relates to the field of intelligent lock control technology, and in particular to an intelligent lock communication control method and system based on digital differential, and an intelligent lock. Background Art

[0002] Current smart locks have independent control systems, meaning one smart lock is installed per door, controlled by its independent control system. However, to achieve centralized control of multiple smart locks installed on multiple doors within a building system, an external bus such as CAN or 485 is required for control, or control is performed via the Internet / Bluetooth. However, external buses such as CAN or 485 are costly and energy-intensive, while Internet / Bluetooth control presents certain security risks. Furthermore, using an external bus such as CAN or 485 is more suitable for long-distance communication, typically employing twisted-pair differential communication technology. This can suppress industrial mode interference during transmission and improve communication reliability. However, twisted-pair differential communication generally requires a dedicated driver or chip, which is relatively expensive.

[0003] In view of this, it is necessary to develop a smart lock communication control method, system and smart lock based on digital differential to overcome the above defects. Summary of the Invention

[0004] In order to solve the above technical problems, the purpose of the present invention is to disclose a smart lock communication control method, system and smart lock based on digital differential.

[0005] The first object of the present invention is to provide a communication control method for an intelligent lock based on digital differential.

[0006] The second object of the present invention is to provide a smart lock.

[0007] The third object of the present invention is to provide an intelligent lock communication system based on digital differential.

[0008] To achieve the above first invention objective, the present invention provides a smart lock communication control method based on digital differential, comprising the following steps:

[0009] Step S1: The MCU controller at the information sending end generates a data packet for controlling the smart lock. The data packet includes a synchronization header and several bits of data. The synchronization header is a string of low-level codes that is greater than the coding period.

[0010] Step S2: the MCU controller at the information sending end sends a synchronization packet header through a timer, and the MCU controller at the information receiving end receives the synchronization packet header and enters a ready state;

[0011] Step S3: The MCU controller at the information sending end encodes each bit of data in sequence according to a preset encoding cycle. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the cycle and the end point of the low level as the end point of the cycle. The absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20%;

[0012] Step S4: The MCU controller of the information sending end sends the codes in sequence through the timer interrupt program;

[0013] Step S5: The MCU controller at the information receiving end reads the code according to the preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%. If X%-Y%>0%, the code is interpreted as 1; if X%-Y%<0%, the code is interpreted as 0;

[0014] Step S6: According to steps S3-S5, a plurality of bits of data are transmitted in sequence and the data packet is sent.

[0015] Preferably, the data packet is encoded and decoded using the MSB or LSB rule.

[0016] Preferably, the number of bits of the encoding is 8 bits, and the sampling frequency is 8 times / encoding cycle to 30 times / encoding cycle.

[0017] Preferably, when the synchronization packet header jumps to a high level, the MCU controller of the information sending end changes from an idle state to a sending state.

[0018] Based on the same inventive principle, in order to achieve the above-mentioned second invention purpose, the present invention provides a smart lock, and the communication protocol of the smart lock is communicated according to the smart lock communication control method based on digital differential described in the first invention.

[0019] Based on the same inventive principle, in order to achieve the above third invention object, the present invention provides a smart lock communication system based on digital differential, including a control center and a plurality of smart locks controlled by the control center;

[0020] The control center includes an MCU processor and a timer module, and the MUC processor includes a signal encoding module;

[0021] The smart lock includes a first MCU processor, and the first MCU processor includes a first signal decoder;

[0022] The MCU processor pre-stores the ID information of the smart lock;

[0023] The signal timer and the first signal decoder communicate with each other via a first signal line.

[0024] Preferably, the control center is the information sending end, and the MCU controller generates a data packet for controlling the smart lock, and the data packet includes a synchronization header and several bit data.

[0025] Preferably, the MCU controller at the information sending end encodes each bit of data in sequence and uses the signal encoding module according to a preset encoding period. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the period and the end point of the low level as the end point of the period. The absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20%, and the encoding is sent in sequence through the signal timer.

[0026] Preferably, the first signal decoder reads the code according to a preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%. If X%-Y%>0%, the code is interpreted as 1; if X%-Y%<0%, the code is interpreted as 0.

[0027] Preferably, the data packet is encoded and decoded according to the MSB or LSB rule, and the synchronization header of the data packet is a string of low-level codes that is greater than the encoding period;

[0028] The number of bits of the encoding is 8 bits, and the sampling frequency is 8 times / encoding cycle to 30 times / encoding cycle;

[0029] When the synchronization packet header jumps to a high level, the MCU controller of the information sending end changes from an idle state to a sending state.

[0030] Compared with the prior art, the technical effects of the present invention are as follows:

[0031] The present invention is applicable to the working conditions where multiple smart locks are installed on multiple doors in the same building system such as villas and large flats, and the multiple smart locks are controlled by a control center; the control center is the information sending end, and the smart lock is the information receiving end. Through the present invention, the information that the control center needs to send is encapsulated into a data packet containing a synchronization header. The synchronization header serves as the transmission starting segment of a data packet, and the starting segment notifies the smart lock to enter the receiving state; the MCU controller at the information sending end encodes each bit of data according to a preset encoding cycle. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the cycle and ends at the low level. The end point is the end point of the cycle; since the conversion point between the high level and the low level may be a high level or a low level, in order to reduce the bit error rate, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20% during encoding; when there is external interference, even if a certain level in the encoding is incorrectly sampled, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is not greatly affected, and during decoding, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is divided by 0%, which is equivalent to setting a 20% redundant space during encoding, thereby reducing external interference; through the present invention, high reliability and stable transmission are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 This is a principle block diagram of the intelligent lock communication system based on digital differential of the present invention.

[0034] Figure 2 This is a schematic diagram of the coding and sampling principles of the present invention.

[0035] Figure 3 This is a flow chart of the intelligent lock communication control method based on digital differential of the present invention.

[0036] Figure 4 It is a schematic diagram of the coding transmission circuit and receiving circuit of the present invention.

[0037] Among them, the information sending end is UART1-TX; the information receiving end is UART1-RX; the first NPN transistor is Q1; the first PNP transistor is Q2; the first diode is D1; ​​the first resistor is R1; the second resistor is R2; the third resistor is R3; the fourth resistor is R4; the fifth resistor is R5; the sixth resistor is R6; the first capacitor is C1; and the first signal line is X. DETAILED DESCRIPTION

[0038] The present invention is described in detail below with reference to the various embodiments shown in the accompanying drawings, but it should be noted that these embodiments are not limitations of the present invention, and any equivalent transformations or substitutions in functions, methods, or structures made by ordinary technicians in this field based on these embodiments are all within the scope of protection of the present invention.

[0039] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operate in a specific direction, and therefore should not be understood as limiting the present invention. Example 1

[0040] Ginseng Figure 1 and Figure 2 As shown, this embodiment discloses a specific implementation of a smart lock communication control method based on digital differential.

[0041] Intelligent lock communication control method based on digital differential, Figure 1 and Figure 2 As shown, the following steps are included:

[0042] Step S1: The MCU controller at the information sending end generates a data packet for controlling the smart lock, the data packet includes a synchronization header and several bit data, the synchronization header is a string of low-level codes greater than the coding period; specifically, see Figure 1 The data packet is encoded and decoded using the MSB or LSB rule. This embodiment is applicable to the working condition where multiple smart locks are installed on multiple doors in the same building system, such as villas and large flats, and the multiple smart locks are controlled by one control center; the control center is the information sending end, and the smart lock is the information receiving end. The information sending end sends information to the information receiving end through the first signal line X.

[0043] Step S2: The MCU controller at the information sending end sends a synchronization packet header through a timer, and the MCU controller at the information receiving end receives the synchronization packet header and enters a ready state; specifically, when there is no need to send information, both the information sending end and the information receiving end are in an idle state. When information needs to be sent, the synchronization packet header is sent first. The synchronization packet header serves as the transmission starting segment of a data packet, and the starting segment notifies the smart lock to enter a receiving state. The reason why the length of the synchronization packet header is greater than the encoding period is to distinguish the synchronization packet header from the actual encoding.

[0044] Step S3: The MCU controller at the information sending end encodes each bit data in sequence according to a preset encoding cycle. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the cycle and the end point of the low level as the end point of the cycle. The absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20%; specifically, see Figure 3 A coding cycle is the length of time a set of codes takes up. The coding cycle ranges from 8 to 20. For example, an 8-bit coding cycle is represented by the code 11111000, where 11111 represents a continuous high level and 000 represents a continuous low level. The high level is used as the starting point of the cycle and the low level as the end point to facilitate determining the status of the information transmitter and receiver. For example, when the synchronization packet header transitions to a high level, the MCU controller on the information transmitter transitions from an idle state to a transmit state, while the MCU controller on the information receiver transitions from an idle state to a ready-to-receive state.

[0045] Step S4: The MCU controller at the information sending end sends the code in sequence through the timer interrupt program; specifically, the timer sends the code formed in step S3, the code is a waveform with a coding period as a period, the peak of the waveform is a high-level band, and the peak and valley of the waveform are low-level bands.

[0046] Step S5: The MCU controller at the information receiving end reads the code according to the preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%. If X%-Y%>0%, the code is interpreted as 1; if X%-Y%<0%, the code is interpreted as 0; specifically, see Figure 3 , Figure 3From top to bottom are waveform m, waveform n and sampling frequency h, the number of bits of code is 8, and the sampling frequency is 8 times / coding cycle to 30 times / coding cycle; waveform m consists of a synchronization header and two groups of codes. The synchronization header is a low level that exceeds the length of the coding cycle. Among the two groups of codes, the sampling frequency is 10 times / coding cycle for explanation. In the first cycle of waveform m, the high level accounts for X% of 35%, and the low level accounts for Y% of 65%. X%-Y%=-30%, and the result is <0%. The code corresponding to this waveform is decoded to 0. Similarly, waveform m The code corresponding to the waveform of the second cycle is also decoded to 0; waveform n consists of a synchronization packet header and two groups of codes. The synchronization packet header is a low level that exceeds the length of the coding cycle. In the two groups of codes, the sampling frequency is 10 for explanation. In the first cycle of waveform n, the high level accounts for X% of 65%, and the low level accounts for Y% of 35%. X%-Y%=30%, and the result is greater than 0%. The code corresponding to the waveform is decoded to 1. Similarly, the code corresponding to the waveform of the second cycle of waveform n is also decoded to 1. In actual sampling, due to the transition point between high and low levels, (Rising edge or falling edge) may be decoded as a high level or a low level. In order to reduce the bit error rate, when encoding, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20%. In one encoding cycle, even if one more high level or one more low level is decoded, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is not greatly affected. When decoding, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is divided by 0%, which is equivalent to setting a 20% redundant space during encoding, thereby reducing the bit error rate. When external interference is present, even if a level within a coding cycle is incorrectly sampled, the absolute value of the difference between the high-level proportion X% and the low-level proportion Y% has little impact. During decoding, the absolute value of the difference between the high-level proportion X% and the low-level proportion Y% is divided by 0%, which is equivalent to setting a 20% redundancy space during encoding. In other words, the results caused by the interference are covered by the absolute value of the difference between the high-level proportion X% and the low-level proportion Y%, with almost no impact on the final decoding result. This reduces external interference and achieves high reliability and stable transmission. Step S6: Transmit a plurality of bits of data and send the data packet in sequence according to steps S3-S5.

[0047] Through this embodiment, the information that the control center needs to send is encapsulated into a data packet containing a synchronization header. The synchronization header serves as the transmission starting segment of a data packet, and the starting segment notifies the smart lock to enter the receiving state; the MCU controller at the information sending end encodes each bit of data according to a preset coding cycle. The coding consists of continuous high levels and continuous low levels. The coding takes the high level as the starting point of the cycle and the end point of the low level as the end point of the cycle; and then, by ensuring that the absolute value of the difference between the high level proportion X% and the low level proportion Y% is greater than 20%, redundancy is improved, bit error rate is reduced, and anti-interference ability is improved, thereby achieving high reliability and stable transmission. Example 2

[0048] See also Figure 1 , Example 2 provides a smart lock, and the communication protocol of the smart lock is carried out according to the smart lock communication control method based on digital differential described in Example 1.

[0049] Specifically, the smart locks are controlled by a control center. This embodiment is applicable to the working conditions where multiple smart locks are installed on multiple doors in the same building system, such as villas and large flats, and multiple smart locks are controlled by one control center. Example 2 takes three smart locks as an example. Each smart lock has an information receiving terminal UART1-RX, an information receiving terminal UART2-RX, and an information receiving terminal UART3-RX. The control center is the information sending terminal, and the smart lock is the information receiving terminal. The information sending terminal synchronously sends information to the information receiving terminal UART1-RX, the information receiving terminal UART2-RX, and the information receiving terminal UART3-RX through the first signal line X. The high level / low level of the information sending terminal is realized by the signal sending circuit, and the high level / low level of the information receiving terminal is realized by the signal receiving circuit. The principles of the sending circuit and the receiving circuit are shown in FIG. Figure 4 ,exist Figure 4 In the example, taking the information transmitting end UART1-TX and the information receiving end UART1-RX, the length of the first signal line X is L, 0m<L≤100m, which realizes the centralized control of the smart locks within a range of 100m. To realize the signal transmission of medium and long distance (100m range), see Figure 4The sending circuit includes a first NPN transistor Q1, a first resistor R1 and a second resistor R2, the first resistor R1 is arranged between the base of the first NPN transistor Q1 and the information sending terminal UART1-TX of the MCU processor, the second resistor R2 is grounded and electrically connected to the information sending terminal UART1-TX of the MCU processor, the emitter of the first NPN transistor Q1 is grounded, and the collector of the first NPN transistor Q1 is electrically connected to the first signal line X; the information receiving end includes a first diode D1, a first PNP transistor Q2, a first capacitor C1, a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a sixth resistor R6, the voltage drop of the first diode D1 is 0.7V, the first diode D1 is electrically connected to the first signal line X, the third resistor R3 It is a pull-up resistor for the first signal line X, the pull-up voltage of the third resistor R3 is 12V-48V, a fourth resistor R4 is set between the base of the first PNP transistor Q2 and the first diode D1, the collector of the first PNP transistor Q2 is electrically connected to the information receiving terminal UART1-RX of the MCU processor, the two ends of the fifth resistor R5 are respectively electrically connected to the collector of the first PNP transistor Q2 and ground, the emitter of the first PNP transistor Q2 is connected to VDD, and the voltage of VDD is 3.3V, the two ends of the sixth resistor R6 are respectively connected to VDD and the anode of the first diode D1, the two ends of the first capacitor C1 are respectively electrically connected to the anode of the first diode D1 and ground, and the sixth resistor R6 and the first capacitor C1 form an RC filter circuit. The forward voltage drop of the first diode D1 is 0.7V and reversely blocked. The first signal line X is exposed to the environment and is susceptible to external interference (electromagnetic, radiation, coupling). When there is external interference, the interference signal on the first signal line X fluctuates around the pull-up voltage of the third resistor R3, which is 12V-48V. When the lowest voltage of the interference signal peak is greater than 2.6V, all interference is reversely blocked by the first diode D1. Only when the voltage on the first signal line X is less than 2.6V can the first diode D1 be passively forward-conducted, so that the first PNP transistor When tube Q2 is turned on, UART1-RX receives a high-level signal caused by an interference signal. Since the pull-up voltage of the third resistor R3 is 12V-48V, the information receiving end UART1-RX has a strong anti-interference capability, and the outside world is not likely to interfere with it. In addition, the RC filter circuit formed by the sixth resistor R6 and the first capacitor C1 further reduces high-frequency glitches or coupled interference that can be transmitted from the first signal line X. This makes the entire receiving circuit module less susceptible to external interference on the first signal line X, and the information receiving end UART1-RX can receive stable, correct and valid signals.

[0050] See also Figure 4Taking the example of the information transmitting end UART1-TX sending a code to the information receiving end UART1-RX, when the information transmitting end UART1-TX outputs a high level, the high level of the information transmitting end UART1-TX is 3.3V, the base of the first NPN transistor Q1 is at a high level and is turned on, and the first NPN transistor Q1 connects the third resistor R3 to the ground through the first signal line X, so that the cathode of the first diode D1 is grounded and turned on, thereby, the base of the first PNP transistor Q2 is grounded and lower than the emitter voltage 3.3V, and the first PNP transistor Q2 is turned on, thereby achieving a voltage of 3.3V at the information receiving end UART1-RX, and achieving the 3.3V high level of the information transmitting end UART1-TX is transmitted to the information receiving end UART1-RX through the first signal line X, and further received by the first MCU processor; when the information transmitting end UART1-TX outputs a low level, the low level of the information transmitting end UART1-TX is 0V, and the first NPN transistor Q2 is connected to the ground. The base of the N-type transistor Q1 is at a low level and is cut off. The pull-up voltage of the third resistor R3 is 12V-48V. Taking the pull-up voltage of the third resistor R3 as 12V for explanation, the first diode D1 is a reverse diode, and the pull-up voltage of 12V is cut off, thereby reducing the base and emitter voltages of the first PNP-type transistor Q2 to 3.3V. The first PNP-type transistor Q2 is cut off, and the voltage of the information receiving end UART1-RX is pulled down to ground by the fifth resistor R5, thereby causing the information receiving end UART1-RX to be at a low level. The 0V low level of the information transmitting end UART1-TX is transmitted to the information receiving end UART1-RX through the first signal line X, and is further received by the first MCU processor. When the information transmitting end UART1-TX sends information to the information receiving end UART1-RX, it sends signals consisting of high and low levels. Through the above-mentioned high and low level signal transmission principle, medium and long distance (100 meters) signal transmission is achieved. The pull-up voltage of the third resistor R3 is 12V-48V. On the one hand, this voltage helps to increase the transmission distance of the first signal line X. On the other hand, it reduces the voltage fluctuation center of the external interference signal on the first signal line X. Combined with the sixth resistor R6 and the first capacitor C1 to form an RC filter circuit, the master-slave mode smart lock control system has a strong anti-interference ability.

[0051] The smart lock described in Example 2 is similar to that in Example 1, so please refer to Example 1 and will not be repeated here. Example 3

[0052] See also Figures 1 to 4This embodiment provides a smart lock communication system based on digital differential, including a control center and several smart locks controlled by the control center; the control center includes an MCU processor and a timer module, the timer module sends a code according to the method described in Example 1 and the circuit of Example 2, the MUC processor includes a signal encoding module, and the signal encoding module is used to generate a code; the smart lock includes a first MCU processor, the first MCU processor includes a first signal decoder, and the first signal decoder performs decoding according to the method described in Example 1 and the circuit of Example 2; the MCU processor pre-stores the ID information of the smart lock, and the data packet needs to encapsulate the ID information of the smart lock. Each smart lock will receive the information, but only the smart lock with matching ID information will act according to the information, such as unlocking; the signal timer and the first signal decoder communicate through the first signal line X.

[0053] Specifically, the control center is the information sending end, and the MCU controller generates a data packet to control the smart lock, and the data packet includes a number of bit data. The data packet includes a synchronization header and a number of bit data. The synchronization header is a string of low-level codes that is greater than the coding period; see Figure 1 The data packet is encoded and decoded using the MSB or LSB rule. This embodiment is applicable to the working condition where multiple smart locks are installed on multiple doors in the same building system, such as villas and large flats, and the multiple smart locks are controlled by one control center; the control center is the information sending end, and the smart lock is the information receiving end. The information sending end sends information to the information receiving end through the first signal line X.

[0054] The MCU controller at the information sending end sequentially and uses the signal encoding module to encode each bit of data according to a preset encoding cycle. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the cycle and the low level as the end point of the cycle. The absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20%. The encoding is sent sequentially through the signal timer; the first signal decoder reads the encoding according to the preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%. If X%-Y%>0%, the encoding is interpreted as 1, and if X%-Y%<0%, the encoding is interpreted as 0. For details, see Figure 3 , Figure 3From top to bottom are waveform m, waveform n and sampling frequency h, the number of bits of code is 8, the sampling frequency is 8 times / coding cycle-30 times / coding cycle; waveform m consists of a synchronization header and two groups of codes. The synchronization header is a low level that exceeds the length of the coding cycle. In the two groups of codes, the sampling frequency is 10 times / coding cycle for explanation. In the first cycle of waveform m, the high level accounts for X% of 35%, and the low level accounts for Y% of 65%. X%-Y%=-30%, and the result is <0%. The code corresponding to this waveform is decoded to 0. Similarly, The code corresponding to the waveform of the second cycle of shape m is also decoded to 0; waveform n consists of a synchronization packet header and two groups of codes. The synchronization packet header is a low level that exceeds the length of the coding cycle. In the two groups of codes, the sampling frequency is 10 for explanation. In the first cycle of waveform n, the high level accounts for X% of 65%, and the low level accounts for Y% of 35%. X%-Y%=30%, and the result is greater than 0%. The code corresponding to this waveform is decoded to 1. Similarly, the code corresponding to the waveform of the second cycle of waveform n is also decoded to 1. In actual sampling, due to the high and low levels, The conversion point (rising edge or falling edge) may be decoded as a high level or a low level. In order to reduce the bit error rate, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20%. In one encoding cycle, even if one more high level or one more low level is decoded, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is not greatly affected. During decoding, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is divided by 0%, which is equivalent to setting a 20% redundancy space during encoding, thereby reducing the bit error rate. When there is external interference, even if a certain level within a coding cycle is sampled incorrectly, it has little impact on the absolute value of the difference between the high level proportion X% and the low level proportion Y%. During decoding, the absolute value of the difference between the high level proportion X% and the low level proportion Y% is divided by 0%, which is equivalent to setting a 20% redundant space during encoding. That is, the result caused by the interference is covered by the absolute value of the difference between the high level proportion X% and the low level proportion Y%, which has almost no effect on the final decoding result, thereby reducing external interference and achieving high reliability and stable transmission.

[0055] The smart lock communication system based on digital differential described in Example 3 is similar to that of Example 1 or Example 2. Please refer to Example 1 or Example 2 and will not be repeated here.

Claims

1. A smart lock communication control method based on digital differential, characterized in that: The following steps are involved: Step S1: The MCU controller at the information sending end generates a data packet for controlling the smart lock. The data packet includes a synchronization header and several bits of data. The synchronization header is a string of low-level codes that is greater than the coding period. Step S2: The MCU controller at the information sending end sends a synchronization packet header through a timer, and the MCU controller at the information receiving end receives the synchronization packet header and enters a ready state; Step S3: The MCU controller at the information sending end encodes each bit of data in sequence according to a preset encoding cycle. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the cycle and the end point of the low level as the cycle end. The absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20% and less than or equal to 30%. When there is external interference, a certain level in a coding cycle is wrongly sampled, and the result of the interference is overwritten by the absolute value of the difference between the high level proportion X% and the low level proportion Y%; Step S4: The MCU controller of the information sending end sends the code in sequence through the timer interrupt program. The ID information of the smart lock is pre-stored in the MCU controller, and the high level / low level of the information sending end is realized by the signal sending circuit; . Step S5: The MCU controller at the information receiving end reads the code according to the preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%, and decodes the transition points of the high level and the low level as high level or low level. If X%-Y%>0%, the code is interpreted as 1; if X%-Y%<0%, the code is interpreted as 0, and the transition point is a rising edge or a falling edge; Step S6: According to steps S3-S5, a plurality of bits of data are transmitted in sequence and the data packet is sent.

2. The intelligent lock communication control method based on digital differential is characterized by: The following steps are involved: Step S1: The MCU controller at the information sending end generates a data packet for controlling the smart lock. The data packet includes a synchronization header and several bits of data. The synchronization header is a string of low-level codes that is greater than the coding period. Step S2: The MCU controller at the information sending end sends a synchronization packet header through a timer, and the MCU controller at the information receiving end receives the synchronization packet header and enters a ready state; Step S3: The MCU controller at the information sending end encodes each bit of data in sequence according to a preset encoding cycle. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the cycle and the end point of the low level as the end point of the cycle. The absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20% and less than or equal to 30%; Step S4: The MCU controller of the information sending end sends the code in sequence through the timer interrupt program. The ID information of the smart lock is pre-stored in the MCU controller, and the high level / low level of the information sending end is realized by the signal sending circuit; Step S5: The MCU controller at the information receiving end reads the code according to the preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%, and decodes the transition points of the high level and the low level as high level or low level. If X%-Y%>0%, the code is interpreted as 1; if X%-Y%<0%, the code is interpreted as 0; Step S6: transmitting a plurality of bits of data in sequence according to steps S3-S5 and sending the data packet; The transmitting circuit includes a first NPN transistor, a first resistor, and a second resistor, wherein the first resistor is arranged between the base of the first NPN transistor and the information transmitting terminal of the MCU controller, the second resistor is grounded and electrically connected to the information transmitting terminal of the MCU controller, the emitter of the first NPN transistor is grounded, and the collector of the first NPN transistor is electrically connected to the first signal line; The information receiving end includes a first diode, a first PNP transistor, a first capacitor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor. The voltage drop of the first diode is 0.7V. The first diode is electrically connected to the first signal line. The third resistor is a pull-up resistor of the first signal line.

3. The intelligent lock communication control method based on digital differential according to claim 1 or 2, characterized in that: The data packets are encoded and decoded using the MSB or LSB rule.

4. The digital differential-based intelligent lock communication control method according to claim 3, characterized in that: The number of bits of the encoding is 8 bits, and the sampling frequency is 8 times / encoding cycle to 30 times / encoding cycle.

5. The intelligent lock communication control method based on digital differential according to claim 4, characterized in that: When the synchronization packet header jumps to a high level, the MCU controller of the information sending end changes from an idle state to a sending state.

6. Smart lock, characterized in that, The communication protocol of the smart lock communicates according to the smart lock communication control method based on digital difference according to any one of claims 1-5.

7. The intelligent lock communication system based on digital differential is characterized by: It includes a control center and several smart locks controlled by the control center; The control center includes an MCU processor and a timer module, and the MCU processor includes a signal encoding module; The smart lock includes a first MCU processor, and the first MCU processor includes a first signal decoder; The MCU processor pre-stores the ID information of the smart lock; The timer module and the first signal decoder communicate with each other via a first signal line, wherein the length of the first signal line is L, 0m<L≤100m; The control center is an information generating end and an information sending end. The MCU processor generates a data packet to control the smart lock. The smart lock is an information receiving end. Each smart lock will receive the data packet sent by the information sending end through the first signal line. Only the smart lock that matches the ID information contained in the data packet will execute the data packet. The high level / low level of the information sending end is realized through the signal sending circuit; The transmitting circuit includes a first NPN transistor, a first resistor, and a second resistor, wherein the first resistor is arranged between the base of the first NPN transistor and the information transmitting terminal of the MCU processor, the second resistor is grounded and electrically connected to the information transmitting terminal of the MCU processor, the emitter of the first NPN transistor is grounded, and the collector of the first NPN transistor is electrically connected to the first signal line; The information receiving end includes a first diode, a first PNP transistor, a first capacitor, a third resistor, a fourth resistor, a fifth resistor and a sixth resistor. The voltage drop of the first diode is 0.7V. The first diode is electrically connected to the first signal line. The third resistor is a pull-up resistor of the first signal line.

8. The digital differential-based intelligent lock communication system according to claim 7, characterized in that: The data packet includes a synchronization header and several bits of data.

9. The digital differential-based intelligent lock communication system according to claim 8, characterized in that: The MCU processor of the information sending end sequentially and uses the signal encoding module to encode each bit of data according to a preset encoding cycle. The encoding consists of continuous high levels and continuous low levels. The encoding takes the high level as the starting point of the cycle and the end point of the low level as the end point of the cycle. The absolute value of the difference between the high level proportion X% and the low level proportion Y% is set to be greater than 20% and less than or equal to 30%. The encoding is sent in sequence through the timer module; When there is external interference, a certain level in a coding cycle is sampled incorrectly, and the result of the interference is covered by the absolute value of the difference between the high level proportion X% and the low level proportion Y%.

10. The digital differential-based intelligent lock communication system according to claim 9, characterized in that: The first signal decoder reads the code according to a preset sampling frequency and calculates the high level proportion X% and the low level proportion Y%. If X%-Y%>0%, the code is interpreted as 1; if X%-Y%<0%, the code is interpreted as 0.

11. The digital differential-based intelligent lock communication system according to claim 10, wherein: The data packet is encoded and decoded according to the MSB or LSB rule, and the synchronization header of the data packet is a string of low-level codes that is greater than the encoding period; the number of bits of the code is 8 bits, and the sampling frequency is 8 times / encoding period to 30 times / encoding period; when the synchronization header jumps to a high level, the MCU processor at the information sending end changes from an idle state to a sending state.

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