A semiconductor device, its fabrication method and its application

Abstract

This invention provides a semiconductor device, its fabrication method, and its application. By setting a multi-layered ring structure outside the X-ray sensitive region, including a P-type charge collection ring, multiple P-type guard rings, and multiple N-type guard rings, the influence of leakage current and external electric fields outside the X-ray sensitive region is effectively shielded, thereby significantly improving signal quality and the stability of the semiconductor device. Furthermore, this structural design effectively suppresses plasma effects, further enhancing the sensitivity and signal-to-noise ratio of the semiconductor device. These performance improvements are crucial for the stable operation of the semiconductor device under high operating voltage environments. The semiconductor device of this invention can achieve a breakdown voltage of at least 600V and an operating voltage of at least 300V under irradiation, fully meeting the requirements of specific applications such as XFELs.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a semiconductor device, its preparation method, and its application. Background Technology

[0002] In large scientific platforms such as synchrotron radiation and X-ray free electron lasers (XFELs), real-time monitoring and diagnosis of beam states are crucial. This is especially true in XFEL systems based on the self-amplified spontaneous emission (SASE) mechanism, where the pulses are essentially resonant amplifications of noise, exhibiting intrinsic randomness—meaning the beam bunches are fluctuating and each bunch may have different characteristics. Therefore, capturing and diagnosing the state information of each beam bunch is essential for the success of scientific experiments.

[0003] To achieve precise monitoring of X-ray photon beams, a range of beam diagnostic devices are widely used, including quadrant beam position monitors (QBPMs) and gas monitors (GMDs). These devices can monitor key parameters of the X-ray photon beam, such as beam size, shape, position, and intensity, ensuring the accuracy and reliability of experimental data.

[0004] However, due to the extremely high beam brightness of XFELs, the pulse intensity typically reaches or exceeds 10. 12 Photons / pulses present challenges to detector design and use. The radiation damage from high-intensity XFEL pulses not only easily leads to the failure or damage of core detectors such as photodiodes (PDs) in beam diagnostic equipment (e.g., QBPM, GMD), rendering them consumables, but also causes severe plasma effects. This significantly weakens the reverse bias field within the device, hindering electron and hole drift and delaying charge collection. In this situation, carrier cloud dissipation mainly occurs through diffusion and electrostatic repulsion, greatly increasing signal readout time, causing pulse accumulation, and resulting in signal distortion, delay, and nonlinear response, affecting detection accuracy. Furthermore, due to the special requirements of diagnostic equipment for detectors, customized and flexible designs of the PD's size, shape, and materials are often necessary to meet specific operating environments and performance requirements.

[0005] Therefore, providing a semiconductor device with high durability and excellent signal response to meet the specific application requirements of XFEL has become an important technical problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device, a fabrication method and its application, to solve the problems of low durability and poor signal response of semiconductor devices for XFEL applications in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a semiconductor device comprising:

[0009] An N-type substrate, wherein a predetermined region of the N-type substrate is divided into an X-ray sensitive area;

[0010] An N-type doped layer is located on the lower surface of the N-type substrate;

[0011] The P-type doped region is located on the upper surface of the N-type substrate and is disposed in the X-ray sensitive region;

[0012] A P-type charge collection ring is located on the upper surface of the N-type substrate and is arranged around the periphery of the X-ray sensitive region;

[0013] Multiple P-type guard rings are located on the upper surface of the N-type substrate and are arranged around the periphery of the P-type charge collection ring. The multiple P-type guard rings are arranged sequentially and at intervals along the direction away from the X-ray sensitive region.

[0014] Multiple N-type guard rings are located on the upper surface of the N-type substrate and are arranged around the outermost P-type guard ring. The multiple N-type guard rings are arranged sequentially and at intervals along a direction away from the X-ray sensitive area.

[0015] Optionally, the semiconductor device further includes:

[0016] An insulating layer is located on the N-type substrate, and the insulating layer has a first contact hole that exposes the P-type doped region at the bottom, a second contact hole that exposes the P-type charge collection ring at the bottom, a third contact hole that exposes the P-type guard ring at the bottom, and a fourth contact hole that exposes the N-type guard ring at the bottom.

[0017] A first electrode layer is located on the insulating layer. The first electrode layer includes a first electrode portion, a second electrode portion, a plurality of third electrode portions, and a plurality of fourth electrode portions. The first electrode portion is located above the P-type doped region and fills into the first contact hole, and is electrically connected to the P-type doped region. The second electrode portion is located above the P-type charge collection ring and fills into the second contact hole, and is electrically connected to the P-type charge collection ring. The third electrode portion is located above the P-type guard ring and fills into the third contact hole, and is electrically connected to the P-type guard ring. The fourth electrode portion is located above the N-type guard ring and fills into the fourth contact hole, and is electrically connected to the N-type guard ring.

[0018] The second electrode layer is located on the lower surface of the N-type doped layer.

[0019] Optionally, the first electrode is electrically connected to the back-end electronic circuit, the second electrode is connected to the ground potential of the back-end electronic circuit, and the plurality of third electrode portions and the plurality of fourth electrode portions are floating.

[0020] Optionally, the third electrode portion and the fourth electrode portion protrude beyond the corresponding P-type protective ring and N-type protective ring in the direction toward the X-ray sensitive region, and the width of the protruding portions of the plurality of third electrode portions and the plurality of fourth electrode portions increases sequentially in the direction away from the X-ray sensitive region.

[0021] This invention also provides a method for fabricating a semiconductor device, comprising the following steps:

[0022] An N-type substrate is provided, wherein a predetermined region of the N-type substrate is divided into an X-ray sensitive region;

[0023] An N-type doped layer is formed on the lower surface of the N-type substrate;

[0024] A P-type doped region, a P-type charge collection ring, multiple P-type guard rings, and multiple N-type guard rings are formed on the upper surface of the N-type substrate. The P-type doped region is disposed in the X-ray sensitive region. The P-type charge collection ring is disposed around the periphery of the X-ray sensitive region. The multiple P-type guard rings are disposed around the periphery of the P-type charge collection ring and are arranged sequentially and at intervals in a direction away from the X-ray sensitive region. The multiple N-type guard rings are disposed around the periphery of the outermost P-type guard ring and are arranged sequentially and at intervals in a direction away from the X-ray sensitive region.

[0025] Optionally, forming the P-type doped region, the P-type charge collection ring, the plurality of P-type guard rings, and the plurality of N-type guard rings on the upper surface of the N-type substrate includes the following steps:

[0026] An insulating layer is formed on the N-type substrate;

[0027] A first photoresist layer is formed on the insulating layer;

[0028] Pattern the first photoresist layer;

[0029] Ion implantation is performed on the N-type substrate based on the patterned first photoresist layer to form the P-type doped region, the P-type charge collection ring, and a plurality of P-type guard rings on the upper surface of the N-type substrate.

[0030] Remove the first photoresist layer;

[0031] A second photoresist layer is formed on the insulating layer;

[0032] Pattern the second photoresist layer;

[0033] Ion implantation is performed on the N-type substrate based on the patterned second photoresist layer to form a plurality of N-type protective rings on the upper surface of the N-type substrate;

[0034] Remove the second photoresist layer.

[0035] Optionally, after forming a P-type doped region, a P-type charge collection ring, a plurality of P-type guard rings, and a plurality of N-type guard rings on the upper surface layer of the N-type substrate, the method further includes the following steps:

[0036] A first contact hole, a second contact hole, a third contact hole, and a fourth contact hole are formed in the insulating layer. The bottom of the first contact hole exposes the P-type doped region, the bottom of the second contact hole exposes the P-type charge collection ring, the bottom of the third contact hole exposes the P-type guard ring, and the bottom of the fourth contact hole exposes the N-type guard ring.

[0037] A first electrode layer is formed on the insulating layer. The first electrode layer includes a first electrode portion, a second electrode portion, a plurality of third electrode portions, and a plurality of fourth electrode portions. The first electrode portion is located above the P-type doped region and fills into the first contact hole, and is electrically connected to the P-type doped region. The second electrode portion is located above the P-type charge collection ring and fills into the second contact hole, and is electrically connected to the P-type charge collection ring. The third electrode portion is located above the P-type guard ring and fills into the third contact hole, and is electrically connected to the P-type guard ring. The fourth electrode portion is located above the N-type guard ring and fills into the fourth contact hole, and is electrically connected to the N-type guard ring.

[0038] A second electrode layer is formed on the lower surface of the N-type doped layer.

[0039] Optionally, the first electrode is electrically connected to the back-end electronic circuit, the second electrode is connected to the ground potential of the back-end electronic circuit, and the plurality of third electrode portions and the plurality of fourth electrode portions are floating.

[0040] Optionally, the third electrode portion and the fourth electrode portion protrude beyond the corresponding P-type protective ring and N-type protective ring in the direction toward the X-ray sensitive region, and the width of the protruding portions of the plurality of third electrode portions and the plurality of fourth electrode portions increases sequentially in the direction away from the X-ray sensitive region.

[0041] The present invention also provides an application of a semiconductor device, wherein the semiconductor device described above is used for X-ray detection or beam diagnostics.

[0042] As described above, the semiconductor device, fabrication method, and application of the present invention, by setting a multi-layered ring structure outside the X-ray sensitive region, including a P-type charge collection ring, multiple P-type guard rings, and multiple N-type guard rings, effectively shields the influence of leakage current and external electric field outside the X-ray sensitive region, thereby significantly improving signal quality and the stability of the semiconductor device. Furthermore, this structural design effectively suppresses plasma effects, further enhancing the sensitivity and signal-to-noise ratio of the semiconductor device. These performance improvements are crucial for the stable operation of the semiconductor device under high operating voltage environments. The semiconductor device of the present invention can achieve a breakdown voltage of at least 600V and an operating voltage of at least 300V under irradiation, fully meeting the requirements of specific applications such as XFELs. Attached Figure Description

[0043] Figure 1 The diagram shown is a cross-sectional view of the semiconductor device of the present invention in one embodiment.

[0044] Figure 2 The diagram shown is a planar layout of the semiconductor device of the present invention in one embodiment.

[0045] Figure 3 The diagram shows a schematic representation of an N-type substrate provided in one embodiment of the method for fabricating a semiconductor device according to the present invention.

[0046] Figure 4 The diagram shown is a schematic diagram of the structure obtained after forming an N-type doped layer in one embodiment of the semiconductor device fabrication method of the present invention.

[0047] Figure 5 The diagram shown is a schematic representation of the structure obtained after forming the first insulating layer in one embodiment of the semiconductor device fabrication method of the present invention.

[0048] Figure 6 The diagram shown is a schematic diagram of the structure obtained after forming an opening region in the first insulating layer in one embodiment of the semiconductor device fabrication method of the present invention.

[0049] Figure 7The diagram shown is a schematic representation of the structure obtained after forming the second insulating layer in one embodiment of the semiconductor device fabrication method of the present invention.

[0050] Figure 8 The diagram shown is a schematic diagram of the structure obtained after forming a P-type doped region, a P-type charge collection ring, a plurality of P-type guard rings and a plurality of N-type guard rings in one embodiment of the semiconductor device fabrication method of the present invention.

[0051] Figure 9 The diagram shown is a schematic diagram of the structure obtained after forming a first contact hole, a second contact hole, a third contact hole, and a fourth contact hole in one embodiment of the semiconductor device fabrication method of the present invention.

[0052] Figure 10 The diagram shown is a schematic diagram of the structure obtained after forming a first electrode portion, a second electrode portion, a third electrode portion and a fourth electrode portion in one embodiment of the semiconductor device fabrication method of the present invention.

[0053] Figure 11 The diagram shown is a schematic representation of the structure obtained after forming the second electrode layer in one embodiment of the semiconductor device fabrication method of the present invention.

[0054] Figure 12 The diagram shown is a schematic diagram of the structure obtained after forming a passivation layer in one embodiment of the semiconductor device fabrication method of the present invention.

[0055] Component designation explanation

[0056] 10 N-type substrate

[0057] 101 X-ray Sensitive Area

[0058] 11 N-type doped layer

[0059] 12 P-type doped regions

[0060] 13 P-type charge collection ring

[0061] 14 P-type protective ring

[0062] 15 N-type protective ring

[0063] 16 Insulation layer

[0064] 161 First Insulation Layer

[0065] 162 Second Insulation Layer

[0066] 163 First contact hole

[0067] 164 Second Contact Hole

[0068] 165 Third contact hole

[0069] 166 Fourth contact hole

[0070] 17 First Electrode Layer

[0071] 171 First Electrode Section

[0072] 172 Second Electrode Section

[0073] 173 Third Electrode Section

[0074] 174 Fourth Electrode Section

[0075] 18 Second electrode layer

[0076] 19. Passivation layer Detailed Implementation

[0077] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0079] Example 1

[0080] This embodiment provides a semiconductor device; please refer to [link / reference]. Figure 1 and Figure 2 ,in, Figure 1 The diagram shown is a cross-sectional view of the semiconductor device in one embodiment. Figure 2The diagram shown is a planar layout of the semiconductor device in one embodiment, including an N-type substrate 10, an N-type doped layer 11, a P-type doped region 12, a P-type charge collection ring 13, multiple P-type guard rings 14, and multiple N-type guard rings 15. A predetermined region of the N-type substrate 10 is divided into an X-ray sensitive region 101. The N-type doped layer 11 is located on the lower surface of the N-type substrate 10. The P-type doped region 12 is located on the upper surface of the N-type substrate 10 and is disposed within the X-ray sensitive region 101. The P-type charge collection rings 13 are located on the N-type substrate... The upper surface layer of the N-type substrate 10 is arranged around the periphery of the X-ray sensitive region 101; a plurality of P-type protective rings 14 are located on the upper surface layer of the N-type substrate 10 and are arranged around the periphery of the P-type charge collection ring 13, and the plurality of P-type protective rings 14 are arranged sequentially and at intervals in a direction away from the X-ray sensitive region 101; a plurality of N-type protective rings 15 are located on the upper surface layer of the N-type substrate 10 and are arranged around the periphery of the outermost P-type protective ring 14, and the plurality of N-type protective rings 15 are arranged sequentially and at intervals in a direction away from the X-ray sensitive region 101.

[0081] As an example, the N-type substrate 10 is preferably made of a semiconductor material with high resistivity and high purity, such as silicon, gallium arsenide, cadmium telluride, cadmium zinc telluride, or other suitable semiconductor materials, to ensure the high performance of the semiconductor device.

[0082] As a preferred example, the N-type substrate 10 is a silicon substrate with a purity greater than 99.9999%, a thickness of 350–500 micrometers, and a resistivity of 5–15 kΩ·cm.

[0083] Specifically, in this embodiment, the crystal orientation of the silicon substrate is... <100> The silicon substrate has a thickness of 500 micrometers and a resistivity of 10 kΩ·cm.

[0084] As an example, the ion implantation dose range of the p-type doped region 12 is 1E14 to 5E16 atoms / cm. 2 The ion implantation dose range of the N-type guard ring 15 is 1E14 to 1E16 atoms / cm. 2 The P-type doped region 12 is used to form a large space charge region within the N-type substrate 10 to facilitate the effective separation and collection of charge carriers.

[0085] Furthermore, the ion implantation doses of the P-type charge collection ring 13 and the P-type guard ring 14 are the same as the ion implantation dose of the P-type doped region 12, and the ion implantation dose of the N-type doped layer 11 is the same as the ion implantation dose of the N-type guard ring 15. The P-type charge collection ring 13 collects leakage current generated outside the X-ray sensitive region 101 and effectively shields current interference in these areas, thereby improving the overall performance of the semiconductor device. The multiple P-type guard rings 14 modulate the electric field distribution of the X-ray sensitive region 101 by gradient-sharing the applied bias voltage, thus preventing the X-ray sensitive region 101 from being affected by external electric fields, thereby enhancing the signal quality and stability of the semiconductor device. Simultaneously, the multiple N-type guard rings 15 help reduce surface leakage current and surface effects, further improving the sensitivity and signal-to-noise ratio of the semiconductor device.

[0086] Specifically, in this embodiment, the ion implantation dose of the P-type doped region 12 is 5E14 atoms / cm². 2 The ion implantation dose of the N-type guard ring 15 is 1E15 atoms / cm. 2 .

[0087] As an example, the number of P-type guard rings 14 is greater than or equal to 5, and the number of N-type guard rings 15 is greater than or equal to 1. It should be noted that the ion implantation dose and quantity parameters of the P-type doped region 12, the P-type guard ring 14, the N-type guard ring 15, and the P-type charge collection ring 13 in this embodiment are data ranges summarized after device simulation and experimental testing verification. The ion implantation dose and quantity parameters of the P-type doped region 12, the P-type guard ring 14, the N-type guard ring 15, and the P-type charge collection ring 13 in the semiconductor device structure need to be within the above data range to ensure that the semiconductor device maintains high yield while having high breakdown voltage, operating voltage, and excellent radiation resistance. In this embodiment, the number of P-type guard rings 14 is preferably 10, and the number of N-type guard rings 15 is preferably 3.

[0088] As an example, the semiconductor device further includes an insulating layer 16, a first electrode layer 17, and a second electrode layer 18. The insulating layer 16 is located on the N-type substrate 10 and has a first contact hole 163 exposing the P-type doped region 12 at its bottom, a second contact hole 164 exposing the P-type charge collection ring 13 at its bottom, a third contact hole 165 exposing the P-type guard ring 14 at its bottom, and a fourth contact hole 166 exposing the N-type guard ring 15 at its bottom. The first electrode layer 17 is located on the insulating layer 16 and includes a first electrode portion 171, a second electrode portion 172, a plurality of third electrode portions 173, and a plurality of fourth electrode portions 174. The first electrode portion 171 is located above the P-type doped region 12 and fills the first contact hole 163, and is electrically connected to the P-type doped region 12. The second electrode portion 172 is located above the P-type charge collection ring 13 and fills the second contact hole 164, and is electrically connected to the P-type charge collection ring 13. The third electrode portion 173 is located above the P-type guard ring 14 and fills the third contact hole 165, and is electrically connected to the P-type guard ring 14. The fourth electrode portion 174 is located above the N-type guard ring 15 and fills the fourth contact hole 166, and is electrically connected to the N-type guard ring 15. The second electrode layer 18 is located on the lower surface of the N-type doped layer 11.

[0089] As an example, the insulating layer 16 includes a first insulating layer 161 and a second insulating layer 162, wherein the thickness of the second insulating layer 162 is less than the thickness of the first insulating layer 161, and the materials of the second insulating layer 162 and the first insulating layer 161 include any one of silicon dioxide, silicon nitride, and aluminum oxide. The insulating layer 16 is used to isolate the first electrode layer 17 from the N-type substrate 10, thereby electrically insulating the first electrode layer 17 from the N-type substrate 10 and reducing the power consumption of the semiconductor device. In this embodiment, the first insulating layer 161 is preferably a silicon dioxide insulating layer, and the second insulating layer 162 is preferably a silicon nitride insulating layer.

[0090] As an example, the thickness of the first insulating layer 161 ranges from 400 to 600 nanometers, and the thickness of the second insulating layer 162 ranges from 50 to 150 nanometers.

[0091] As an example, the first electrode layer 17 and the second electrode layer 18 may be made of aluminum, titanium, copper, silver, gold, or a combination of the above materials, and are not limited to the examples listed herein.

[0092] As an example, the thickness of the first electrode layer 17 and the second electrode layer 18 ranges from 200 to 700 nanometers. If the thickness of the second electrode layer 18 is too thin, it cannot shield visible light; if the thickness of the second electrode layer 18 is too thick, it will result in a large dead zone. In this embodiment, the first electrode layer 17 and the second electrode layer 18 are preferably made of aluminum, with the thickness of the first electrode layer 17 preferably being 600 nanometers and the thickness of the second electrode layer 18 preferably being 700 nanometers.

[0093] As an example, the semiconductor device further includes a passivation layer 19 located on the first electrode layer 17, the passivation layer 19 having an opening that exposes the first electrode portion 171, the second electrode portion 172, the third electrode portion 173 and the fourth electrode portion 174.

[0094] As an example, the passivation layer 19 can be a single-layer thin film or a multi-layer thin film, and is prepared by chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods. The material of the passivation layer 19 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride. The passivation layer 19 provides a protective barrier for the semiconductor device, reducing nonradiative recombination of electron-hole pairs caused by surface defects, thereby reducing dark current, improving quantum efficiency, and signal-to-noise ratio. Furthermore, the passivation layer 19 also protects the semiconductor device from environmental factors such as moisture and oxygen, enhancing the stability and lifespan of the device.

[0095] Specifically, the working principle of the semiconductor device in this embodiment is as follows: When X-ray photons are incident on the X-ray sensitive region 101 of the semiconductor device, the X-ray photons interact with the atoms in the material of the X-ray sensitive region 101 to generate free charge carriers. When a reverse bias voltage is applied to the semiconductor device, these charge carriers separate under the influence of an electric field; electrons drift to the N-type doped layer 11, and holes drift to the P-type doped region 12, forming a current. This current is amplified and converted to form a usable electrical signal for monitoring or data acquisition of XFEL pulses.

[0096] As an example, the first electrode 171 is electrically connected to the back-end electronics circuit via wire bonding, the second electrode 172 is connected to the ground potential of the back-end electronics circuit, and the plurality of third electrode 173 and the plurality of fourth electrode 174 are floating and not connected to any fixed potential.

[0097] As an example, the third electrode portion 173 and the fourth electrode portion 174 protrude from the corresponding P-type protective ring 14 and N-type protective ring 15 in the direction toward the X-ray sensitive region 101, and the width of the protruding portions of the plurality of third electrode portions 173 and the plurality of fourth electrode portions 174 increases sequentially in the direction away from the X-ray sensitive region 101.

[0098] Specifically, the width of these protruding portions, denoted by d, gradually increases with increasing distance from the X-ray sensitive region 101. Specifically, the width d increases in increments of 1 to 1.5 micrometers from a position close to the X-ray sensitive region 101 towards the direction away from it. The design of the third electrode portion 173 and the fourth electrode portion 174 helps reduce the direct effect of radiation on the insulating layer 16 and the N-type substrate 10, effectively reducing radiation-induced charge trapping and interface state generation, thereby optimizing the device's radiation resistance.

[0099] As an example, the area of ​​the X-ray sensitive region 101 ranges from 5 mm × 5 mm to 30 mm × 30 mm. The width of the P-type charge collection ring 13 surrounding the X-ray sensitive region 101 ranges from 80 to 100 micrometers, the width of the plurality of P-type guard rings 14 ranges from 15 to 35 micrometers, and the width of the plurality of N-type guard rings 15 ranges from 25 to 45 micrometers. As the area of ​​the X-ray sensitive region 101 increases, the detection range of the semiconductor device also expands. However, this increase in area also leads to an increase in the capacitance of the semiconductor device, thereby causing increased noise.

[0100] Specifically, in this embodiment, the area of ​​the X-ray sensitive region 101 is preferably 5 mm × 5 mm, the width of the P-type charge collection ring 13 is preferably 90 micrometers, the width of the plurality of P-type guard rings 14 is preferably 25 micrometers, and the width of the plurality of N-type guard rings 15 is preferably 35 micrometers. By optimizing the widths of the P-type charge collection ring 13, the plurality of P-type guard rings 14, the plurality of N-type guard rings 15, and the area of ​​the X-ray sensitive region 101, it is ensured that while expanding the detection range of the semiconductor device, the noise level is effectively controlled, thereby improving the overall performance of the semiconductor device.

[0101] It should be noted that, Figure 2 The illustrated embodiment presents a planar layout of a square semiconductor device. In other embodiments, the semiconductor device may also employ a circular layout design.

[0102] The semiconductor device of this embodiment effectively shields the X-ray sensitive region 101 from the influence of external leakage current and external electric field by setting a multi-layer ring structure, including a P-type charge collection ring 13, multiple P-type guard rings 14, and multiple N-type guard rings 15, thereby significantly improving signal quality and enhancing the radiation resistance and stability of the semiconductor device. Furthermore, this structural design effectively suppresses plasma effects, further improving the sensitivity and signal-to-noise ratio of the semiconductor device. These performance improvements are crucial for the stable operation of the semiconductor device under high operating voltage environments. The semiconductor device of this invention can achieve a breakdown voltage of at least 600V and an operating voltage of at least 300V under irradiation, fully meeting the requirements of specific applications such as XFELs.

[0103] Example 2

[0104] This embodiment provides a method for fabricating a semiconductor device, including the following steps:

[0105] S1: Provide an N-type substrate, wherein a predetermined region of the N-type substrate is divided into an X-ray sensitive region;

[0106] S2: Form an N-type doped layer on the lower surface of the N-type substrate;

[0107] S3: A P-type doped region, a P-type charge collection ring, a plurality of P-type guard rings, and a plurality of N-type guard rings are formed on the upper surface of the N-type substrate. The P-type doped region is disposed in the X-ray sensitive region. The P-type charge collection ring is disposed around the periphery of the X-ray sensitive region. The plurality of P-type guard rings are disposed around the periphery of the P-type charge collection ring and are arranged sequentially and at intervals in a direction away from the X-ray sensitive region. The plurality of N-type guard rings are disposed around the periphery of the outermost P-type guard ring and are arranged sequentially and at intervals in a direction away from the X-ray sensitive region.

[0108] The following is combined Figures 3-12 and Figure 1 , Figure 2 The method for fabricating the semiconductor device in this embodiment will be described in detail.

[0109] Please refer to the following first. Figure 3 In step S1, an N-type substrate 10 is provided, and a preset area of ​​the N-type substrate 10 is divided into an X-ray sensitive area 101.

[0110] As an example, the N-type substrate 10 is preferably made of a semiconductor material with high resistivity and high purity, such as silicon, gallium arsenide, cadmium telluride, cadmium zinc telluride, or other suitable semiconductor materials, to ensure the high performance of the semiconductor device.

[0111] As a preferred example, the N-type substrate 10 is a silicon substrate with a purity greater than 99.9999%, a thickness of 350–500 micrometers, and a resistivity of 5–15 kΩ·cm.

[0112] Specifically, in this embodiment, the crystal orientation of the silicon substrate is... <100> The silicon substrate has a thickness of 500 micrometers and a resistivity of 10 kΩ·cm.

[0113] Please see again Figure 4 Step S2 is performed to form an N-type doped layer 11 on the lower surface of the N-type substrate 10.

[0114] As an example, an N-type doped layer 11 is formed on the lower surface of the N-type substrate 10 using ion implantation, thermal diffusion, or other suitable methods. The thickness of the N-type doped layer 11 is less than or equal to 1 micrometer, and the dopant used to form the N-type doped layer 11 includes any one of phosphorus, arsenic, or antimony.

[0115] Please see again Figures 5-8 Step S3 is executed to form a P-type doped region 12, a P-type charge collection ring 13, a plurality of P-type guard rings 14, and a plurality of N-type guard rings 15 on the upper surface of the N-type substrate 10. The P-type doped region 12 is disposed in the X-ray sensitive region 101. The P-type charge collection ring 13 is disposed around the periphery of the X-ray sensitive region 101. The plurality of P-type guard rings 14 are disposed around the periphery of the P-type charge collection ring 13 and are arranged sequentially and at intervals in a direction away from the X-ray sensitive region 101. The plurality of N-type guard rings 15 are disposed around the periphery of the outermost P-type guard ring 14 and are arranged sequentially and at intervals in a direction away from the X-ray sensitive region 101.

[0116] As an example, forming the P-type doped region 12, the P-type charge collection ring 13, the plurality of P-type guard rings 14, and the plurality of N-type guard rings 15 on the upper surface of the N-type substrate 10 includes the following steps:

[0117] (1) An insulating layer 16 is formed on the N-type substrate 10 by chemical vapor deposition, physical vapor deposition, thermal oxidation or other suitable methods, wherein the material of the insulating layer 16 includes any one or a combination of two or more of silicon dioxide, silicon nitride and aluminum oxide.

[0118] In one embodiment, forming the insulating layer 16 on the N-type substrate 10 includes the following steps:

[0119] (1-1) As Figure 5As shown, a first insulating layer 161 is formed on the N-type substrate 10 using chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods;

[0120] (1-2) such as Figure 6 As shown, an opening region is formed in the first insulating layer 161 through processes such as photolithography and etching, and the opening region exposes the N-type substrate 10;

[0121] (1-3) such as Figure 7 As shown, a second insulating layer 162 is formed on the N-type substrate 10 using chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods. The second insulating layer 162 covers the opening region. The thickness of the second insulating layer 162 is less than the thickness of the first insulating layer 161, and the materials of the second insulating layer 162 and the first insulating layer 161 include any one of silicon dioxide, silicon nitride, and aluminum oxide. In this embodiment, the first insulating layer 161 is preferably a silicon dioxide insulating layer, and the second insulating layer 162 is preferably a silicon nitride insulating layer.

[0122] As an example, the thickness of the first insulating layer 161 ranges from 400 to 600 nanometers, and the thickness of the second insulating layer 162 ranges from 50 to 150 nanometers.

[0123] (2) A first photoresist layer is formed on the insulating layer 16 (not shown) by a coating process;

[0124] (3) The first photoresist layer (not shown) is patterned by ultraviolet exposure and development process;

[0125] (4) Figure 8 As shown, ion implantation is performed on the N-type substrate 10 based on the patterned first photoresist layer to form the P-type doped region 12, the P-type charge collection ring 13 and a plurality of P-type guard rings 14 on the upper surface of the N-type substrate 10.

[0126] (5) Remove the first photoresist layer (not shown) by ashing or wet etching process;

[0127] (6) A second photoresist layer is formed on the insulating layer 16 by a coating process (not shown);

[0128] (7) The second photoresist layer (not shown) is patterned by ultraviolet exposure and development process;

[0129] (8) Continue as follows Figure 8 As shown, ion implantation is performed on the N-type substrate 10 based on the patterned second photoresist layer to form a plurality of N-type protective rings 15 on the upper surface of the N-type substrate 10;

[0130] (9) Remove the second photoresist layer (not shown) by ashing or wet etching process.

[0131] Specifically, the P-type doped region 12, the P-type charge collection ring 13, and multiple P-type guard rings 14 can be formed simultaneously through the same ion implantation process, effectively reducing process complexity, reducing process costs, and improving efficiency.

[0132] As an example, the ion implantation dose range of the p-type doped region 12 is 1E14 to 5E16 atoms / cm. 2 The ion implantation dose range of the N-type guard ring 15 is 1E14 to 1E16 atoms / cm. 2 The P-type doped region 12 is used to form a large space charge region within the N-type substrate 10 to facilitate the effective separation and collection of charge carriers.

[0133] Furthermore, the ion implantation doses of the P-type charge collection ring 13 and the P-type guard ring 14 are the same as the ion implantation dose of the P-type doped region 12, and the ion implantation dose of the N-type doped layer 11 is the same as the ion implantation dose of the N-type guard ring 15. The P-type charge collection ring 13 collects leakage current generated outside the X-ray sensitive region 101 and effectively shields current interference in these areas, thereby improving the overall performance of the semiconductor device. The multiple P-type guard rings 14 modulate the electric field distribution of the X-ray sensitive region 101 by gradient-sharing the applied bias voltage, thus preventing the X-ray sensitive region 101 from being affected by external electric fields, thereby enhancing the signal quality and stability of the semiconductor device. Simultaneously, the multiple N-type guard rings 15 help reduce surface leakage current and surface effects, further improving the sensitivity and signal-to-noise ratio of the semiconductor device.

[0134] Specifically, in this embodiment, the ion implantation dose of the P-type doped region 12 is 5E14 atoms / cm². 2 The ion implantation dose of the N-type guard ring 15 is 1E15 atoms / cm. 2 .

[0135] Furthermore, to ensure sufficient diffusion of the implanted ions to form a PN junction, the ion-implanted semiconductor device can be annealed in an inert gas atmosphere to activate the implanted ions. The annealing time range is 15–25 minutes, and the annealing temperature range is 700–800°C. In this embodiment, annealing is performed in a helium atmosphere at 750°C for 20 minutes to achieve the best ion activation effect.

[0136] As an example, the number of P-type protection rings 14 is greater than or equal to 5, and the number of N-type protection rings 15 is greater than or equal to 1.

[0137] As a preferred example, the periphery of the P-type charge collection ring 13 includes 10 P-type guard rings 14 and 3 N-type guard rings 15.

[0138] For example, please refer to Figures 9-12 After forming a P-type doped region 12, a P-type charge collection ring 13, multiple P-type guard rings 14, and multiple N-type guard rings 15 on the upper surface of the N-type substrate 10, the process further includes the following steps:

[0139] (1) As Figure 9 As shown, a first contact hole 163, a second contact hole 164, a third contact hole 165, and a fourth contact hole 166 are formed in the insulating layer 16 by photolithography and etching processes. The bottom of the first contact hole 163 exposes the P-type doped region 12, the bottom of the second contact hole 164 exposes the P-type charge collection ring 13, the bottom of the third contact hole 165 exposes the P-type guard ring 14, and the bottom of the fourth contact hole 166 exposes the N-type guard ring 15.

[0140] (2) Figure 10 As shown, a first electrode layer 17 is formed on the insulating layer 16 by photolithography and physical vapor deposition, chemical vapor deposition, or other suitable methods. The first electrode layer 17 includes a first electrode portion 171, a second electrode portion 172, a plurality of third electrode portions 173, and a plurality of fourth electrode portions 174. The first electrode portion 171 is located above the P-type doped region 12 and fills into the first contact hole 163 and is electrically connected to the P-type doped region 12. The second electrode portion 172 is located above the P-type charge collection ring 13 and fills into the second contact hole 164 and is electrically connected to the P-type charge collection ring 13. The third electrode portion 173 is located above the P-type guard ring 14 and fills into the third contact hole 165 and is electrically connected to the P-type guard ring 14. The fourth electrode portion 174 is located above the N-type guard ring 15 and fills into the fourth contact hole 166 and is electrically connected to the N-type guard ring 15.

[0141] (3) Figure 11 As shown, a second electrode layer 18 is formed on the lower surface of the N-type doped layer 11.

[0142] As an example, the first electrode layer 17 and the second electrode layer 18 may be made of aluminum, titanium, copper, silver, gold, or a combination of the above materials, and are not limited to the examples listed herein.

[0143] As an example, the thickness of the first electrode layer 17 and the second electrode layer 18 ranges from 200 to 700 nanometers. If the thickness of the second electrode layer 18 is too thin, it cannot shield visible light; if the thickness of the second electrode layer 18 is too thick, it will result in a large dead zone. In this embodiment, the first electrode layer 17 and the second electrode layer 18 are preferably made of aluminum, with the thickness of the first electrode layer 17 preferably being 600 nanometers and the thickness of the second electrode layer 18 preferably being 700 nanometers.

[0144] For example, please refer to Figure 12 It also includes the step of forming a passivation layer 19 on the first electrode layer 17, wherein the passivation layer 19 has an opening that exposes the first electrode portion 171, the second electrode portion 172, the third electrode portion 173 and the fourth electrode portion 174.

[0145] As an example, the passivation layer 19 can be a single-layer thin film or a multi-layer thin film, and is prepared by chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods. The material of the passivation layer 19 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride. The passivation layer 19 provides a protective barrier for the semiconductor device, reducing nonradiative recombination of electron-hole pairs caused by surface defects, thereby reducing dark current, improving quantum efficiency, and signal-to-noise ratio. Furthermore, the passivation layer 19 also protects the semiconductor device from environmental factors such as moisture and oxygen, enhancing the stability and lifespan of the device.

[0146] For example, please refer to Figure 1 The first electrode 171 is electrically connected to the back-end electronic circuit via wire bonding, the second electrode 172 is connected to the ground potential of the back-end electronic circuit, and the plurality of third electrode 173 and the plurality of fourth electrode 174 are floating and not connected to any fixed potential.

[0147] As an example, the third electrode portion 173 and the fourth electrode portion 174 protrude from the corresponding P-type protective ring 14 and N-type protective ring 15 in the direction toward the X-ray sensitive region 101, and the width of the protruding portions of the plurality of third electrode portions 173 and the plurality of fourth electrode portions 174 increases sequentially in the direction away from the X-ray sensitive region 101.

[0148] Specifically, in Figure 1In this diagram, the width of these protruding portions, denoted by d, gradually increases with increasing distance from the X-ray sensitive region 101. Specifically, the width d increases in increments of 1 to 1.5 micrometers from a position close to the X-ray sensitive region 101 towards the distance from the X-ray sensitive region 101. The design of the third electrode portion 173 and the fourth electrode portion 174 helps to reduce the direct effect of radiation on the insulating layer 16 and the N-type substrate 10, effectively reducing radiation-induced charge trapping and interface state generation, thereby optimizing the device's radiation resistance.

[0149] For example, please refer to Figure 2 The diagram shows a planar layout of the semiconductor device in one embodiment. The area of ​​the X-ray sensitive region 101 ranges from 5 mm × 5 mm to 30 mm × 30 mm. The width of the P-type charge collection ring 13 surrounding the X-ray sensitive region 101 ranges from 80 to 100 micrometers, the width of the plurality of P-type guard rings 14 ranges from 15 to 35 micrometers, and the width of the plurality of N-type guard rings 15 ranges from 25 to 45 micrometers. As the area of ​​the X-ray sensitive region 101 increases, the detection range of the semiconductor device also expands. However, this increase in area also leads to an increase in the capacitance of the semiconductor device, thereby causing increased noise.

[0150] Specifically, in this embodiment, the area of ​​the X-ray sensitive region 101 is preferably 5 mm × 5 mm, the width of the P-type charge collection ring 13 is preferably 90 micrometers, the width of the plurality of P-type guard rings 14 is preferably 25 micrometers, and the width of the plurality of N-type guard rings 15 is preferably 35 micrometers. By optimizing the widths of the P-type charge collection ring 13, the plurality of P-type guard rings 14, the plurality of N-type guard rings 15, and the area of ​​the X-ray sensitive region 101, it is ensured that while expanding the detection range of the semiconductor device, the noise level is effectively controlled, thereby improving the overall performance of the semiconductor device.

[0151] It should be noted that, Figure 2 The illustrated embodiment presents a planar layout of a square semiconductor device. In other embodiments, the semiconductor device may also employ a circular layout design.

[0152] The semiconductor device fabrication method of this embodiment employs a multi-layered ring structure design to enhance the stability and radiation resistance of the semiconductor device under irradiation. Specifically, the semiconductor device includes P-type charge collection rings 13 and multiple P-type guard rings 14 arranged sequentially and at intervals around the periphery of the X-ray sensitive region 101, forming a highly efficient protective barrier. This barrier effectively prevents charge leakage and diffusion, thereby significantly improving signal quality and enhancing the radiation resistance and stability of the semiconductor device. Furthermore, the introduction of multiple N-type guard rings 15 further strengthens the device's protective capabilities, ensuring stable operation under irradiation conditions. The semiconductor device fabrication method of this embodiment not only ensures high device yield but also significantly improves its radiation resistance. The semiconductor device produced by the fabrication method of this embodiment can achieve a breakdown voltage of at least 600V and an operating voltage of at least 300V after irradiation, fully meeting the specific application requirements of XFELs.

[0153] Example 3

[0154] This embodiment provides an application of a semiconductor device, wherein the semiconductor device in Embodiment 1 is applied to X-ray detection or beam diagnostics.

[0155] Specifically, when the semiconductor device is applied to X-ray detection, beam diagnostics, or other related fields, it forms a highly efficient barrier by sequentially and intermittently arranging P-type charge collection rings 13 and multiple P-type guard rings 14 around the X-ray sensitive region 101. This structural design effectively prevents charge leakage and diffusion, significantly improving the device's stability. Furthermore, the introduction of multiple N-type guard rings 15 further enhances the device's protective capabilities, ensuring that the semiconductor device can achieve a breakdown voltage of at least 600V and an operating voltage of at least 300V under irradiation conditions, meeting the requirements of specific applications such as XFELs.

[0156] The application of the semiconductor device in this embodiment improves the durability and signal responsiveness of X-ray detection and diagnostic equipment by applying the semiconductor device described in Embodiment 1 to X-ray detection or beam diagnostics.

[0157] In summary, the semiconductor device, fabrication method, and application of this invention, by setting a multi-layered ring structure outside the X-ray sensitive region, including a P-type charge collection ring, multiple P-type guard rings, and multiple N-type guard rings, effectively shields the influence of leakage current and external electric fields outside the X-ray sensitive region, thereby significantly improving signal quality and the stability of the semiconductor device. Furthermore, this structural design effectively suppresses plasma effects, further enhancing the sensitivity and signal-to-noise ratio of the semiconductor device. These performance improvements are crucial for the stable operation of the semiconductor device under high operating voltage environments. The semiconductor device of this invention can achieve a breakdown voltage of at least 600V and an operating voltage of at least 300V under irradiation, fully meeting the requirements of specific applications such as XFELs. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0158] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized by, Comprising: An N-type substrate, a preset region of the N-type substrate is divided into an X-ray sensitive area, an area range of the X-ray sensitive area is 5mm x 5mm~30mm x 30mm, and the semiconductor device is applied to beam diagnosis; An N-type doped layer is located at a lower surface layer of the N-type substrate; A P-type doped region is located at an upper surface layer of the N-type substrate and is arranged in the X-ray sensitive area; A P-type charge collection ring is located at the upper surface layer of the N-type substrate and is arranged at the periphery of the X-ray sensitive area; A plurality of P-type guard rings are located at the upper surface layer of the N-type substrate and are arranged at the periphery of the P-type charge collection ring, and the plurality of P-type guard rings are sequentially and spaced arranged in a direction away from the X-ray sensitive area; A plurality of N-type guard rings are located at the upper surface layer of the N-type substrate and are arranged at the periphery of the outermost P-type guard ring, and the plurality of N-type guard rings are sequentially and spaced arranged in a direction away from the X-ray sensitive area; An insulating layer is located on the N-type substrate, and the insulating layer has a first contact hole exposing the P-type doped region at the bottom, a second contact hole exposing the P-type charge collection ring at the bottom, a third contact hole exposing the P-type guard ring at the bottom, and a fourth contact hole exposing the N-type guard ring at the bottom; A first electrode layer is located on the insulating layer, and the first electrode layer includes a first electrode part, a second electrode part, a plurality of third electrode parts, and a plurality of fourth electrode parts, the first electrode part is located above the P-type doped region and fills the first contact hole and is electrically connected with the P-type doped region, the second electrode part is located above the P-type charge collection ring and fills the second contact hole and is electrically connected with the P-type charge collection ring, the third electrode part is located above the P-type guard ring and fills the third contact hole and is electrically connected with the P-type guard ring, and the fourth electrode part is located above the N-type guard ring and fills the fourth contact hole and is electrically connected with the N-type guard ring; Wherein, the third electrode part and the fourth electrode part protrude in the direction towards the X-ray sensitive area with respect to the corresponding P-type guard ring and N-type guard ring, and the width of the protruding part of the plurality of third electrode parts and the plurality of fourth electrode parts increases in the direction away from the X-ray sensitive area.

2. The semiconductor device according to claim 1, wherein Further comprising: A second electrode layer is located at the lower surface of the N-type doped layer.

3. The semiconductor device of claim 1, wherein: The first electrode part is electrically connected with the back-end electronic circuit, the second electrode part is connected with the ground potential of the back-end electronic circuit, and the plurality of third electrode parts and the plurality of fourth electrode parts are floating ground.

4. A method of manufacturing a semiconductor device, characterized by Comprising the following steps: Providing an N-type substrate, a preset region of the N-type substrate is divided into an X-ray sensitive area, an area range of the X-ray sensitive area is 5mm x 5mm~30mm x 30mm, and the semiconductor device is applied to beam diagnosis; Forming an N-type doped layer at a lower surface layer of the N-type substrate; forming a P-type doped region, a P-type charge collection ring, a plurality of P-type guard rings and a plurality of N-type guard rings on an upper surface of the N-type substrate, the P-type doped region is disposed in the X-ray sensitive region, the P-type charge collection ring is disposed around the periphery of the X-ray sensitive region, a plurality of the P-type guard rings are disposed around the periphery of the P-type charge collection ring and are arranged in sequence and at intervals in a direction away from the X-ray sensitive region, and a plurality of the N-type guard rings are disposed around the periphery of the outermost P-type guard ring and are arranged in sequence and at intervals in a direction away from the X-ray sensitive region; forming a first contact hole, a second contact hole, a third contact hole and a fourth contact hole in the insulating layer, the first contact hole exposes the P-type doped region at the bottom, the second contact hole exposes the P-type charge collection ring at the bottom, the third contact hole exposes the P-type guard ring at the bottom, and the fourth contact hole exposes the N-type guard ring at the bottom; forming a first electrode layer on the insulating layer, the first electrode layer includes a first electrode part, a second electrode part, a plurality of third electrode parts and a plurality of fourth electrode parts, the first electrode part is located above the P-type doped region and fills into the first contact hole, and the P-type doped region is electrically connected, the second electrode part is located above the P-type charge collection ring and fills into the second contact hole, and the P-type charge collection ring is electrically connected, the third electrode part is located above the P-type guard ring and fills into the third contact hole, and the P-type guard ring is electrically connected, and the fourth electrode part is located above the N-type guard ring and fills into the fourth contact hole, and the N-type guard ring is electrically connected; wherein the third electrode part and the fourth electrode part protrude from the corresponding P-type guard ring and N-type guard ring in a direction towards the X-ray sensitive region, and the widths of the protruding parts of the plurality of third electrode parts and the plurality of fourth electrode parts increase in sequence in a direction away from the X-ray sensitive region.

5. The method of producing a semiconductor device according to claim 4, wherein forming the P-type doped region, the P-type charge collection ring, a plurality of the P-type guard rings and a plurality of the N-type guard rings on the upper surface of the N-type substrate includes the following steps: forming an insulating layer on the N-type substrate; forming a first photoresist layer on the insulating layer; patterning the first photoresist layer; based on the patterned first photoresist layer, ion implantation is performed on the N-type substrate to form the P-type doped region, the P-type charge collection ring and a plurality of the P-type guard rings on the upper surface of the N-type substrate; removing the first photoresist layer; forming a second photoresist layer on the insulating layer; patterning the second photoresist layer; based on the patterned second photoresist layer, ion implantation is performed on the N-type substrate to form a plurality of the N-type guard rings on the upper surface of the N-type substrate; removing the second photoresist layer.

6. The method of producing a semiconductor device according to claim 4, wherein after forming the P-type doped region, the P-type charge collection ring, a plurality of the P-type guard rings and a plurality of the N-type guard rings on the upper surface of the N-type substrate, the following steps are further included: forming a second electrode layer on the lower surface of the N-type doped layer.

7. The method of producing a semiconductor device according to claim 4, wherein: The first electrode part is electrically connected with a back-end electronic circuit, the second electrode part is connected with a ground potential of the back-end electronic circuit, and the plurality of third electrode parts and the plurality of fourth electrode parts are set to be floating ground.

Images