A memory and an operating method thereof, a memory system, and an electronic device

Abstract

The embodiments of the present disclosure provide a memory and an operating method thereof, a memory system and an electronic device. The operating method comprises: when performing a read operation on a selected memory cell of a memory string, applying a pass voltage to a word line coupled with an unselected memory cell of the memory string according to a programming order of the selected memory cell; wherein the earlier the programming order of the selected memory cell, the greater the pass voltage applied to the word line coupled with the unselected memory cell of the memory string during the read operation. In the embodiments of the present disclosure, the pass voltage applied to the word line coupled with the unselected memory cell is determined according to the programming order of the selected memory cell, that is, according to the different influence degrees of the selected memory cell on the background image correlation effect, so that the influence of the background image correlation effect can be reduced, and the read disturbance can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, a memory system, and an electronic device. Background Technology

[0002] The main characteristic of flash memory is its ability to retain stored information for extended periods without power. To further increase the bit density of flash memory while reducing bit cost, 3D flash memory technology has developed rapidly.

[0003] However, in the development of 3D flash memory, as the number of stacked layers continues to increase, the structural and electrical characteristics problems it faces also increase. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory and its operation method, a memory system, and an electronic device.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] In a first aspect, embodiments of this disclosure provide an operation method for a memory, the memory including a plurality of memory strings, each memory string including a plurality of memory cells, the operation method including:

[0007] When performing a read operation on a selected memory cell of a memory string, a pass voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cell;

[0008] The earlier the selected memory cell is programmed, the greater the voltage applied to the word line coupled to the unselected memory cell in the memory string during a read operation.

[0009] Secondly, embodiments of this disclosure provide a memory, the memory comprising:

[0010] A storage cell array, comprising multiple storage strings, each of which comprises multiple storage cells;

[0011] Peripheral circuitry, wherein the peripheral circuitry is configured as follows:

[0012] When performing a read operation on a selected memory cell of a memory string, a pass voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cell;

[0013] The earlier the selected memory cell is programmed, the greater the voltage applied to the word line coupled to the unselected memory cell in the memory string during a read operation.

[0014] Thirdly, embodiments of this disclosure provide a memory system, the memory system comprising:

[0015] The memory as described in the above technical solution; and

[0016] A controller coupled to the memory and configured to control the memory.

[0017] Fourthly, embodiments of this disclosure provide an electronic device, the electronic device comprising: a memory system as described in the above technical solutions.

[0018] This disclosure provides a memory, its operation method, a memory system, and an electronic device. The operation method includes: when performing a read operation on selected memory cells of a memory string, applying a voltage to word lines coupled to unselected memory cells of the memory string according to the programming order of the selected memory cells; wherein, the earlier the programming order of the selected memory cells, the greater the voltage applied to the word lines coupled to the unselected memory cells during the read operation. In this disclosure, the voltage applied to the word lines coupled to the unselected memory cells is determined according to the programming order of the selected memory cells, i.e., according to the degree to which the selected memory cells are affected by background image correlation effects. This reduces the impact of background image correlation effects and reduces read interference. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating the operational states of each storage unit during the programming process of the storage string;

[0020] Figure 2 A schematic diagram showing the broadening of the threshold voltage distribution of memory cells due to background image correlation effects;

[0021] Figure 3 This diagram illustrates the read operations performed on the storage unit under different circumstances.

[0022] Figure 4 This is a schematic diagram illustrating the read operation on different storage units of a storage string;

[0023] Figure 5 A flowchart illustrating the operation method of the memory provided in this embodiment of the disclosure;

[0024] Figure 6 This disclosure provides an illustration of a read operation performed after forward programming of the storage unit. Figure 1 ;

[0025] Figure 7 This disclosure provides an illustration of a read operation performed after reverse programming of a storage unit, as per an embodiment of the present disclosure. Figure 1 ;

[0026] Figure 8 A schematic diagram illustrating a read operation performed after programming the storage unit provided in the embodiments of this disclosure;

[0027] Figure 9 A circuit diagram of a storage string provided in an embodiment of this disclosure;

[0028] Figure 10 This disclosure provides an illustration of a read operation performed after forward programming of the storage unit. Figure 2 ;

[0029] Figure 11 This disclosure provides an illustration of a read operation performed after forward programming of the storage unit. Figure 3 ;

[0030] Figure 12 This disclosure provides an illustration of a read operation performed after reverse programming of a storage unit, as per an embodiment of the present disclosure. Figure 2 ;

[0031] Figure 13 This disclosure provides an illustration of a read operation performed after reverse programming of a storage unit, as per an embodiment of the present disclosure. Figure 3 ;

[0032] Figure 14 A block diagram of a memory including a memory cell array and peripheral circuitry is provided for embodiments of this disclosure;

[0033] Figure 15 A block diagram of a system including a memory provided for embodiments of this disclosure;

[0034] Figure 16 A schematic diagram of a memory card including a memory provided for an embodiment of this disclosure;

[0035] Figure 17 A schematic diagram of a solid-state drive including a memory, provided for an embodiment of this disclosure;

[0036] Figure 18 Block diagram of an electronic device including a memory system provided for embodiments of this disclosure;

[0037] The diagram includes: 101, solid line; 102, dashed line; 300, memory; 302, memory cell array; 304, peripheral circuitry; 306, memory block; 308, memory cell; 310, memory string; 312, source select gate; 314, drain select gate; 316, drain select gate line; 318, source line; 320, source select gate line; 322, bit line; 324, word line; 326, memory page; 328, source select transistor; 330, drain select transistor; 400, system; 402, memory system; 404, controller; 406, host; 502, memory card; 504, memory card connector; 506, solid-state drive; 508, solid-state drive connector; 600, electronic device. Detailed Implementation

[0038] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0039] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0040] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0041] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0045] Currently, the number of stacked layers in 3D flash memory is increasing, leading to a greater number of structural and electrical challenges. Among these, background pattern dependency (BPD) is a significant issue arising from increased stacking layers. BPD refers to the positive shift in the threshold voltage (Vt) of a pre-programmed memory cell during the programming verification and reading phases due to changes in series resistance. Furthermore, because different memory strings have different programming patterns, the positive shift in threshold voltage caused by changes in series resistance varies, resulting in a wider threshold voltage distribution and consequently a smaller read window margin.

[0046] refer to Figure 1 , Figure 1 This is a schematic diagram illustrating the operational states of each storage unit during the programming process of the storage string. For example... Figure 1 As shown, a memory string corresponds to a channel structure in a memory, with multiple memory cells extending along the string's direction. Memory cells at different locations correspond to different layers in the memory. In the memory, a word line (WL) is coupled to the gate of each memory cell, and a word line voltage is applied to the gate of the transistor corresponding to that memory cell. Figure 1 The illustrated memory string comprises n memory cells. The drain of the top memory cell MC1 is coupled to the bit line (BL), and the source of the bottom memory cell MCn is coupled to the array common source (ACS). The letter P in the circle representing a memory cell indicates that the memory cell is in the program state, and the letter E in the circle representing a memory cell indicates that the memory cell is in the erase state.

[0047] Figure 1 This diagram illustrates the operational state of the top storage unit MC1 of the storage string in two different scenarios. (See diagram for example.) Figure 1As shown in Figure (a), in the first case, only one storage cell in the storage string (i.e., the top storage cell MC1) is programmed before being read. In this case, during the read operation, the top storage cell MC1 of the storage string is the selected storage cell, while the other storage cells in the storage string (i.e., storage cells MC2 to MCn) are unselected storage cells.

[0048] like Figure 1 As shown in Figure (b), in the second case, after programming operations are performed on all storage units of the storage string (i.e., storage units MC1 to MCn), the top storage unit MC1 is read. In this case, during the read operation, the top storage unit MC1 of the storage string is the selected storage unit, while the other storage units of the storage string (i.e., storage units MC2 to MCn) are unselected storage units. Compared to... Figure 1 The threshold voltage of memory cell MC1 is shown in Figure (a). Figure 1 The threshold voltage of memory cell MC1, as shown in Figure (b), shows a positive shift.

[0049] It should be noted that the smallest unit for programming and reading operations is a page. For a single-level cell (SLC), each cell can store 1 bit of information, so at the physical level, one layer of cells corresponds to one page of information. For a multi-level cell (MLC), each cell can store 2 bits of information, so at the physical level, one layer of cells corresponds to two pages of information. For a triple-level cell (TLC), each cell can store 3 bits of information, so at the physical level, one layer of cells corresponds to three pages of information. For a quad-level cell (QLC), each cell can store 4 bits of information, so at the physical level, one layer of cells corresponds to four pages of information.

[0050] In practice, programming a selected memory cell within a memory string refers to programming the memory cells within the same layer of a memory block. Reading a selected memory cell from a memory string refers to reading the memory cells within the same layer of a memory block. Therefore, after programming a selected memory cell, the threshold voltage of the memory cell exhibits a distribution range. In this embodiment, reading memory cells at different locations within a memory string refers to reading memory cells at different layers within a memory block. For ease of explanation, the following description uses a memory string within a memory block as an example.

[0051] refer to Figure 2 , Figure 2 This is a schematic diagram illustrating the broadening of the threshold voltage distribution of memory cells due to background image correlation effects. (Example) Figure 2 As shown, the horizontal axis represents the threshold voltage (Vt) of the memory cell, and the vertical axis represents the number of memory cells. Figure 2 Taking multi-level memory cell technology as an example, the four threshold voltage distributions of the memory cell are illustrated, namely E state, P1 state, P2 state, and P2 state. Figure 2 (not shown in the image) and P3 state. Among them, the E state corresponds to the erase state, and the P1, P2 and P3 states are all programming states.

[0052] Figure 2 The solid line 101 corresponds to Figure 1 Figure (a) illustrates the threshold voltage distribution curve of memory cell MC1 when only the top memory cell MC1 of the memory string is programmed, and the other memory cells of the memory string (i.e., memory cells MC2 to MCn) are in the erase state. Figure 2 The middle dashed line 102 corresponds to Figure 1 Figure (b) illustrates the threshold voltage distribution curve of memory cell MC1 when all memory cells in the memory string (i.e., memory cells MC1 to MCn) are in the programmed state after programming operations are performed on all memory cells in the memory string.

[0053] It should be noted that there is a certain gap between the threshold voltage distribution curves of adjacent states. This gap refers to the difference between the minimum value of the threshold voltage distribution of the higher state and the maximum value of the threshold voltage distribution of the lower state. This gap can be used to represent the read window of the lower state among adjacent states. If the gap is small, the read window is small; if the gap is large, the read window is large. When all memory cells in the memory string are in the programmed state, the background image correlation effect causes the threshold voltage distribution to widen, resulting in a smaller read window and making it easier to cause read disturbances. Among them, the memory cells that are programmed earlier are more affected by the background image correlation effect, and the greater the positive shift in the threshold voltage distribution of that memory cell.

[0054] refer to Figure 3 , Figure 3 This diagram illustrates the reading operations performed on the storage unit under different circumstances. Figure 3 Figure (a) shows the... Figure 1 Figure (a) illustrates a schematic diagram of a read operation on a storage cell within a storage string. For example... Figure 3 As shown in Figure (a), after programming only one memory cell in the memory string, when reading that memory cell, a read voltage Vread is applied to the word line coupled to the selected memory cell (i.e., the top memory cell MC1), while a pass voltage Vpass is applied to the word lines coupled to the other unselected memory cells (i.e., memory cells MC2 to MCn). Figure 3 Figure (b) is a comparison Figure 1 Figure (b) illustrates a schematic diagram of a read operation on a storage cell within a storage string. Figure 3 As shown in Figure (b), after programming all memory cells in the memory string (i.e., memory cells MC1 to MCn), when reading a memory cell, a read voltage Vread is applied to the word line coupled to the selected memory cell (i.e., the top memory cell MC1), while a pass voltage Vpass + ΔVpass is applied to the word lines coupled to the other unselected memory cells (i.e., memory cells MC2 to MCn). Thus, for... Figure 3 When a read operation is performed on a memory cell of the memory string illustrated in Figure (b), the pass voltage (i.e., Vpass + ΔVpass) applied to the word line coupled to the unselected memory cell is greater than that applied to the memory cell. Figure 3 The through voltage (i.e., Vpass) applied to the word line coupled to the unselected memory cell when a read operation is performed on the memory cell of the memory string shown in Figure (a).

[0055] It should be noted that the pass voltage applied to the word line coupled to the unselected memory cell can be increased, i.e., the pass voltage can be increased from Vpass to Vpass + ΔVpass, thereby reducing the impact of background image correlation. However, while this method reduces the positive shift in the threshold voltage caused by background image correlation, it inevitably causes read interference, and may even increase the impact of read interference. Here, read interference refers to the situation where, while applying a read voltage to the word line coupled to the selected memory cell, a pass voltage is also applied to the word line coupled to the unselected memory cell. A strong electric field is formed between the gate and channel of the unselected memory cell, which may allow electrons to enter the charge trapping layer of the unselected memory cell, resulting in a weak programming effect.

[0056] refer to Figure 4 , Figure 4 This is a schematic diagram illustrating the read operation on different storage units of a storage string. Figure 4This diagram illustrates read operations on memory cells at three different locations within a memory string. In the first case, when reading a memory cell at the top of the memory string, a pass voltage Vpass + ΔVpass is applied to the word line coupled to the unselected memory cell. In the second case, when reading a memory cell at the middle of the memory string, the pass voltage Vpass + ΔVpass is applied to the word line coupled to the unselected memory cell. In the third case, when reading a memory cell at the bottom of the memory string, the pass voltage Vpass + ΔVpass is applied to the word line coupled to the unselected memory cell. Thus, the pass voltage applied to the word line coupled to the unselected memory cell is the same when reading memory cells at different locations within the memory string.

[0057] It should be noted that the earlier a memory cell is programmed, the more affected it is by the background image correlation effect, and the greater the positive shift in its threshold voltage distribution. In other words, memory cells at different locations within the same memory string are affected by the background image correlation effect to varying degrees, resulting in different positive shifts in their threshold voltage distributions. However, when reading memory cells at different locations within the memory string, the same pass voltage is applied to the word lines coupled to the unselected memory cells, which is detrimental to reducing read interference.

[0058] refer to Figure 5 , Figure 5 This is a flowchart illustrating the operation method of the memory provided in an embodiment of this disclosure. Figure 5 As shown, this disclosure provides an operation method for a memory, the memory including multiple memory strings, each memory string including multiple memory cells, the operation method including:

[0059] Step S501: When performing a read operation on a selected memory cell of a memory string, a pass voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cell; wherein, the earlier the programming order of the selected memory cell, the greater the pass voltage applied to the word line coupled to the unselected memory cell of the memory string during the read operation.

[0060] As mentioned earlier, the earlier the memory cell is programmed, the greater the influence of background image correlation effect, and the greater the positive offset of the threshold voltage distribution of that memory cell. In this embodiment, the pass voltage applied to the word line coupled to the unselected memory cell is determined according to the programming order of the selected memory cells, that is, according to the different degrees of influence of the background image correlation effect on the selected memory cells. In this way, the influence of background image correlation effect can be reduced, and read interference can be reduced.

[0061] Specifically, memory cells programmed earlier in the sequence are more significantly affected by background image correlation, resulting in a larger positive shift in their threshold voltage distribution. When reading these cells, a larger voltage is applied to the word lines coupled to the unselected cells, thus increasing the current. Conversely, memory cells programmed later in the sequence are less affected by background image correlation, resulting in a smaller positive shift in their threshold voltage distribution. When reading these cells, a smaller voltage is applied to the word lines coupled to the unselected cells, also increasing the current. Here, both reading earlier and later memory cells can increase the current by adjusting the voltage applied to the word lines coupled to the unselected cells in the memory string, but the degree of current increase differs. Specifically, the earlier the selected memory cell is programmed, the larger the voltage applied to the word lines coupled to the unselected cells in the memory string, and the greater the current increase; conversely, the later the selected memory cell is programmed, the smaller the voltage applied to the word lines coupled to the unselected cells in the memory string, and the smaller the current increase. Therefore, by determining the pass voltage applied to the word line coupled to the unselected memory cell based on the degree to which the selected memory cell is affected by the background image correlation effect, the influence of the background image correlation effect can be reduced, and read interference can be reduced.

[0062] It should be noted that the voltage applied to the word lines coupled to the unselected memory cells varies depending on the degree to which the selected memory cell is affected by the background image correlation effect. If the selected memory cell is the last memory cell in the memory string to be programmed, then this selected memory cell is not affected by the background image correlation effect, and the voltage applied to the word lines coupled to the unselected memory cell is minimal, i.e., Vpass-min. Therefore, compared to selecting the last memory cell in the memory string to be programmed, when the selected memory cell is any other memory cell in the memory string, the voltage applied to the word lines coupled to the unselected memory cell is greater than Vpass-min, which can increase the current.

[0063] In this embodiment of the disclosure, before performing a read operation on a selected storage cell of a storage string, the operation method further includes:

[0064] Perform programming operations on multiple storage units of the storage string.

[0065] Before reading from the memory cells of the memory string, programming operations are required. The memory programming process includes forward programming and reverse programming. Forward programming starts from the bottom memory cell closest to the bottom selector (BST) and proceeds upwards to the top memory cell closest to the top selector (TST). Reverse programming starts from the top memory cell closest to the top selector and proceeds downwards to the bottom memory cell closest to the bottom selector. The bottom selector is also called the source selector (SST), and the top selector is also called the drain selector (DST).

[0066] refer to Figure 6 , Figure 6 This disclosure provides an illustration of a read operation performed after forward programming of the storage unit. Figure 1 .like Figure 6 As shown in this embodiment of the disclosure, when the programming operation is a forward programming operation, during a read operation on a selected memory cell of a memory string, a voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cells, including:

[0067] When performing a read operation on a selected memory cell (i.e., Sel cell) of a memory string, the fewer the number of unselected memory cells between the selected memory cell and the source select transistor SST, the greater the pass voltage applied to the word line coupled to the unselected memory cells (i.e., Unsel cells) of the memory string.

[0068] Here, when the programming operation is a forward programming operation, programming begins from the bottom memory cell MCn, which is closest to the source select transistor SST, and ends at the top memory cell MC1, which is closest to the drain select transistor DST. In other words, when the programming operation is a forward programming operation, the bottom memory cell MCn is programmed first and is most affected by the background image correlation effect; the top memory cell MC1 is programmed last and is least affected by the background image correlation effect (or, is not affected by the background image correlation effect). From the bottom memory cell MCn to the top memory cell MC1, the degree to which the memory cells are affected by the background image correlation effect decreases. That is, the fewer the number of unselected memory cells between the selected memory cell and the source select transistor, the greater the degree to which the selected memory cell is affected by the background image correlation effect, and the greater the positive shift in its threshold voltage distribution.

[0069] Figure 6 The diagram illustrates that when a read operation is performed on memory cell MCn, a pass voltage Vpass,1 is applied to the word lines coupled to the unselected memory cells (i.e., memory cells MC1 to MC(n-1)); when a read operation is performed on memory cell MC(n-1), a pass voltage Vpass,2 is applied to the word lines coupled to the unselected memory cells (i.e., memory cells MCn and MC1 to MC(n-2)); and when a read operation is performed on memory cell MC(n-2), a pass voltage Vpass,3 is applied to the word lines coupled to the unselected memory cells (i.e., memory cells MCn, MC(n-1), and MC1 to MC(n-3)). Wherein, Vpass,1 > Vpass,2 > Vpass,3.

[0070] refer to Figure 7 , Figure 7 This disclosure provides an illustration of a read operation performed after reverse programming of a storage unit, as per an embodiment of the present disclosure. Figure 1 .like Figure 7 As shown in this embodiment of the disclosure, when the programming operation is a reverse programming operation, during a read operation on a selected memory cell of a memory string, a voltage is applied to the word lines coupled to the unselected memory cells of the memory string according to the programming order of the selected memory cells, including:

[0071] When performing a read operation on a selected cell (i.e., Sel cell) of a memory string, the fewer the number of unselected cells between the selected cell and the drain select transistor (DST), the greater the pass voltage applied to the word line coupled to the unselected cells (i.e., Unsel cells) of the memory string.

[0072] Here, when the programming operation is a reverse programming operation, programming begins with the top memory cell MC1, which is closest to the drain select transistor (DST), and ends with the bottom memory cell MCn, which is closest to the source select transistor (SST). In other words, when the programming operation is a reverse programming operation, the top memory cell MC1 is programmed first and is most affected by the background image correlation effect; the bottom memory cell MCn is programmed last and is least affected by the background image correlation effect. From the top memory cell MC1 to the bottom memory cell MCn, the degree to which the memory cells are affected by the background image correlation effect decreases. That is, the fewer the number of unselected memory cells between the selected memory cell and the drain select transistor, the greater the degree to which the selected memory cell is affected by the background image correlation effect, and the greater the positive shift in its threshold voltage distribution.

[0073] Figure 7 This diagram illustrates that when a read operation is performed on memory cell MC1, a pass voltage Vpass,4 is applied to the word lines coupled to the unselected memory cells (i.e., memory cells MC2 to MC(n-1)); when a read operation is performed on memory cell MC2, a pass voltage Vpass,5 is applied to the word lines coupled to the unselected memory cells (i.e., memory cells MC1 and memory cells MC3 to MCn); and when a read operation is performed on memory cell MC3, a pass voltage Vpass,6 is applied to the word lines coupled to the unselected memory cells (i.e., memory cells MC1, MC2, and MC4 to MCn). Wherein, Vpass,4 > Vpass,5 > Vpass,6.

[0074] refer to Figure 8 , Figure 8 This is a schematic diagram illustrating a read operation performed after programming the storage unit provided in the embodiments of this disclosure. Figure 8 As shown in this embodiment of the present disclosure, the operation method includes: when performing a read operation on a selected memory cell (i.e., memory cell MCj) of a memory string, the through voltage Vpass,7 applied to the word line coupled to the first unselected memory cell (i.e., memory cells MC(j+1) to MCn) of the memory string is greater than the through voltage Vpass,8 applied to the word line coupled to the second unselected memory cell (i.e., memory cells MC1 to MC(j-1)) of the memory string; wherein, the first unselected memory cell includes the unselected memory cell located between the selected memory cell (i.e., memory cell MCj) and the source select transistor SST, and the second unselected memory cell includes the unselected memory cell located between the selected memory cell (i.e., memory cell MCj) and the drain select transistor DST.

[0075] As mentioned earlier, the pass voltage applied to the word line coupled to the unselected memory cells during a read operation can be determined based on the programming order of the selected memory cells (i.e., memory cells MCj). Here, based on the selected memory cells in the memory string, the unselected memory cells in the memory string can be divided into first unselected memory cells and second unselected memory cells. The first unselected memory cell is closer to the source select transistor SST, and the second unselected memory cell is closer to the drain select transistor DST. Considering the different contributions of the source and drain resistances to the current, different pass voltages are applied to the first unselected memory cell, which is closer to the source, and the second unselected memory cell, which is closer to the drain.

[0076] refer to Figure 9 , Figure 9 This is a circuit diagram of a storage string provided in an embodiment of this disclosure. The following will be combined with... Figure 9 This section explains in detail the different contributions of the source and drain resistances of a memory string to the current. Multiple memory cells in a memory string are connected in series, and the circuit of the memory string can be represented as... Figure 9 The circuit diagram shown is shown. Figure 9 The selected memory cell of the memory string is shown, and the drain current of the memory string is denoted as I. D Let R be the series resistance between the selected memory cell and the unselected memory cell (i.e., the first unselected memory cell) in the memory string. S Let R be the series resistance between the selected memory cell and the unselected memory cell (i.e., the second unselected memory cell) in the memory string. D . Figure 9 The diagram also illustrates the theoretical voltage difference between the drain and source of the selected memory cell, denoted as Vds, and the theoretical voltage difference between the gate and source of the selected memory cell, denoted as Vgs. The drain current I of the memory string can be calculated using the following equation (1). D .

[0077] I D = k*[(V'gs-Vt)*V'ds] (Equation 1)

[0078] Among them, I D V'gs is the drain current of the memory string, k is a fixed parameter value, V'gs is the effective voltage difference between the gate and source of the selected memory cell, Vt is the threshold voltage of the selected memory cell, and V'ds is the effective voltage difference between the drain and source of the selected memory cell.

[0079] Due to parasitic resistance, the theoretical voltage difference Vds and the effective voltage difference V'ds between the drain and source of the selected memory cell differ, as do the theoretical voltage difference Vgs and the effective voltage difference V'gs between the gate and source of the selected memory cell. Referring to Equation 1, based on the effective voltage difference V'gs between the gate and source of the selected memory cell, the threshold voltage Vt of the selected memory cell, and the effective voltage difference V'ds between the drain and source of the selected memory cell, the drain current I of the memory string can be calculated. D Among them, the effective voltage difference V'gs between the gate and source of the selected memory cell in the memory string, and the effective voltage difference V'ds between the drain and source of the selected memory cell are both related to the source resistance, and the source resistance affects the drain current I. D The contribution of the source image is greater; therefore, when performing a read operation on a selected memory cell, the voltage applied to the first unselected memory cell, which is closer to the source, is greater than the voltage applied to the second unselected memory cell, which is closer to the drain. This better mitigates the impact of background image correlation and reduces read interference.

[0080] In this embodiment, when performing a read operation on a selected memory cell, the voltage applied to the word lines coupled to unselected memory cells can be grouped and controlled according to the degree to which the selected memory cell is affected by the background image correlation effect, thereby reducing the impact of the background image correlation effect. When performing a read operation on a selected memory cell, if the selected memory cell is severely affected by the background image correlation effect, a larger voltage is applied to the word lines coupled to the unselected memory cells in the memory string to increase the current. If the selected memory cell is only slightly affected by the background image correlation effect, a smaller voltage is applied to the word lines coupled to the unselected memory cells in the memory string to increase the current. This reduces the impact of the background image correlation effect and also reduces read interference. Grouping and controlling the voltage during the read operation can more specifically improve the problem of the background image correlation effect affecting memory cells in different memory groups. Furthermore, as the number of memory stacking layers increases, the number of read operations also increases; in this embodiment, grouping and controlling the voltage can also reduce read interference.

[0081] In this embodiment of the disclosure, before performing a read operation on a selected storage cell of a storage string, the operation method further includes:

[0082] Based on the programming order, the multiple storage units of the storage string are divided into multiple storage groups.

[0083] Here, each storage group may include at least one storage unit. In other words, the number of storage groups is less than or equal to the number of storage units. This disclosure does not specifically limit the number of storage groups, nor does it specifically limit the number of storage units within a storage group. In some embodiments, the number of storage units within each storage group may be the same. In other embodiments, the number of storage units within each storage group may be different.

[0084] refer to Figure 10 and Figure 11 , Figure 10 and Figure 11 The present disclosure provides illustrations of reading operations performed after forward programming of the storage unit in the embodiments of this disclosure. Figure 2 and indication Figure 3 . refer to Figure 12 and Figure 13 , Figure 12 and Figure 13 The present disclosure provides illustrations of reading operations performed after reverse programming of the storage unit in the embodiments of this disclosure. Figure 2 and indication Figure 3 .like Figure 10 , Figure 11 , Figure 12 and Figure 13 As shown in this embodiment of the disclosure, according to the programming order, multiple storage units of the storage string are divided into multiple storage groups, including:

[0085] According to the programming order, the multiple storage units of the storage string are divided into the first storage group, the second storage group, and the third storage group;

[0086] The programming order of the first storage group is earlier than that of the second storage group, and the programming order of the second storage group is earlier than that of the third storage group.

[0087] When the selected memory cell belongs to the first memory group, a first pass voltage Vpass_H is applied to the word line coupled to the unselected memory cell in the memory string during a read operation; when the selected memory cell belongs to the second memory group, a second pass voltage Vpass_M is applied to the word line coupled to the unselected memory cell in the memory string during a read operation; when the selected memory cell belongs to the third memory group, a third pass voltage Vpass_L is applied to the word line coupled to the unselected memory cell in the memory string during a read operation.

[0088] Among them, the first through voltage Vpass_H is greater than the second through voltage Vpass_M, and the second through voltage Vpass_M is greater than the third through voltage Vpass_L.

[0089] like Figure 10 and Figure 11As shown in this embodiment, when the programming operation is a forward programming operation, the first memory group is closer to the source select transistor SST, and the third memory group is closer to the drain select transistor DST. The fewer the number of unselected memory cells between the selected memory cell and the source select transistor SST, the greater the through voltage applied to the word line coupled to the unselected memory cell when performing a read operation on the selected memory cell. Figure 10 and Figure 11 Taking the example shown, according to the programming order, or according to the degree of influence of the background image correlation effect on the storage unit, the storage string is divided into three storage groups. The third storage group includes storage units MC1 to MC1, totaling i storage units; the second storage group includes storage units Mc(i+1) to MC(i+j), totaling j storage units; and the first storage group includes storage units MC(i+j+1) to MCn, totaling (nij). Figure 10 and Figure 11 Storage cells MC(i+j) and MC(i+j+1) are not shown.

[0090] like Figure 10 As shown, when the selected memory cell (e.g., memory cell MCn) belongs to the first memory group, a first pass voltage Vpass_H is applied to the word line coupled to the unselected memory cell in the memory string during a read operation. In this case, the unselected memory cells include all memory cells in the second and third memory groups, as well as other memory cells in the first memory group; that is, the unselected memory cells include memory cells MC1 to MC(n-1). When the selected memory cell (e.g., memory cell MC(i+1)) belongs to the second memory group, a second pass voltage Vpass_M is applied to the word line coupled to the unselected memory cell in the memory string during a read operation. In this case, the unselected memory cells include all memory cells in the first and third memory groups, as well as other memory cells in the second memory group; that is, the unselected memory cells include memory cells MC1 to MC1 and memory cells Mc(i+2) to MCn. When the selected memory cell (e.g., memory cell MC1) belongs to the third memory group, a third pass voltage Vpass_L is applied to the word line coupled to the unselected memory cells in the memory string during a read operation. In this case, the unselected memory cells include all memory cells in the first and second memory groups, as well as other memory cells in the third memory group; that is, the unselected memory cells include memory cells MC2 to MCn. The first pass voltage Vpass_H is greater than the second pass voltage Vpass_M, and the second pass voltage Vpass_M is greater than the third pass voltage Vpass_L. The specific voltage values ​​of the first pass voltage Vpass_H, the second pass voltage Vpass_M, and the third pass voltage Vpass_L can be adjusted according to actual conditions.

[0091] like Figure 11 As shown in this embodiment, when the selected memory cell (e.g., memory cell MC(i+1)) belongs to the second memory group, during a read operation, a first sub-pass voltage Vpass_M1 is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the source select transistor SST, and a second sub-pass voltage Vpass_M2 is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the drain select transistor DST; wherein, the first sub-pass voltage Vpass_M1 is greater than the second sub-pass voltage Vpass_M2. Here, the specific voltage magnitudes of the first sub-pass voltage Vpass_M1 and the second sub-pass voltage Vpass_M2 can be adjusted according to actual conditions.

[0092] Here, when the selected memory cell belongs to the second memory group, due to the different contributions of the source-end resistance and drain-end resistance to the current, different through voltages can be applied to the word lines coupled to the unselected memory cells located between the selected memory cell and the source select transistor (SST) and between the selected memory cell and the drain select transistor (DST). That is, the through voltages applied to the word lines coupled to the unselected memory cells above and below the selected memory cell in the memory string are different. More specifically, the applied through voltage can be asymmetrical, meaning the through voltage applied to the word lines coupled to the unselected memory cells closer to the source is greater than the through voltage applied to the word lines coupled to the unselected memory cells closer to the drain. The unselected memory cells are divided into those closer to the source and those closer to the drain, depending on the position of the selected memory cell, and the magnitude of the through voltage can be adjusted according to the actual situation. This can further improve the read interference problem caused by the through voltage applied to the word lines coupled to some memory cells, while reducing the impact of background image correlation effects.

[0093] like Figure 12 and Figure 13 As shown in this embodiment, when the programming operation is a reverse programming operation, the first memory group is closer to the drain select transistor (DST), and the third memory group is closer to the source select transistor (SST). The fewer the number of unselected memory cells between the selected memory cell and the drain select transistor (DST), the greater the through voltage applied to the word line coupled to the unselected memory cell when performing a read operation on the selected memory cell. Figure 12 and Figure 13Taking the example shown, according to the programming order, or according to the degree of influence of the background image correlation effect on the storage units, the storage string is divided into three storage groups. The first storage group includes storage units MC1 to MC1, totaling i storage units; the second storage group includes storage units Mc(i+1) to MC(i+j), totaling j storage units; and the third storage group includes storage units MC(i+j+1) to MCn, totaling (nij). Figure 12 and Figure 13 Storage cells MC(i+j) and MC(i+j+1) are not shown.

[0094] like Figure 12 As shown, when the selected memory cell (e.g., memory cell MC1) belongs to the first memory group, a first pass voltage Vpass_H is applied to the word line coupled to the unselected memory cell in the memory string during a read operation. In this case, the unselected memory cells include all memory cells in the second and third memory groups, as well as other memory cells in the first memory group; that is, the unselected memory cells include memory cells MC2 to MCn. When the selected memory cell (e.g., memory cell MC(i+1)) belongs to the second memory group, a second pass voltage Vpass_M is applied to the word line coupled to the unselected memory cell in the memory string during a read operation. In this case, the unselected memory cells include all memory cells in the first and third memory groups, as well as other memory cells in the second memory group; that is, the unselected memory cells include memory cells MC1 to MC1 and memory cells Mc(i+2) to MCn. When the selected memory cell (e.g., memory cell MCn) belongs to the third memory group, a third pass voltage Vpass_L is applied to the word line coupled to the unselected memory cell in the memory string during a read operation. In this case, the unselected memory cells include all memory cells in the first and second memory groups, as well as other memory cells in the third memory group; that is, the unselected memory cells include memory cells MC1 to MC(n-1). The first pass voltage Vpass_H is greater than the second pass voltage Vpass_M, and the second pass voltage Vpass_M is greater than the third pass voltage Vpass_L. The specific voltage values ​​of the first pass voltage Vpass_H, the second pass voltage Vpass_M, and the third pass voltage Vpass_L can be adjusted according to actual conditions.

[0095] like Figure 13As shown in this embodiment, when the selected memory cell (e.g., memory cell MC(i+1)) belongs to the second memory group, during a read operation, a first sub-pass voltage Vpass_M1 is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the source select transistor SST, and a second sub-pass voltage Vpass_M2 is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the drain select transistor DST; wherein, the first sub-pass voltage Vpass_M1 is greater than the second sub-pass voltage Vpass_M2. Here, the specific voltage magnitudes of the first sub-pass voltage Vpass_M1 and the second sub-pass voltage Vpass_M2 can be adjusted according to actual conditions.

[0096] Here, when the selected memory cell belongs to the second memory group, due to the different contributions of the source-end resistance and drain-end resistance to the current, different through voltages can be applied to the word lines coupled to the unselected memory cells located between the selected memory cell and the source select transistor (SST) and between the selected memory cell and the drain select transistor (DST). That is, the through voltages applied to the word lines coupled to the unselected memory cells above and below the selected memory cell in the memory string are different. More specifically, the applied through voltage can be asymmetrical, meaning the through voltage applied to the word lines coupled to the unselected memory cells closer to the source is greater than the through voltage applied to the word lines coupled to the unselected memory cells closer to the drain. The unselected memory cells are divided into those closer to the source and those closer to the drain, depending on the position of the selected memory cell, and the magnitude of the through voltage can be adjusted according to the actual situation. This can further improve the read interference problem caused by the through voltage applied to the word lines coupled to some memory cells, while reducing the impact of background image correlation effects.

[0097] refer to Figure 14 , Figure 14 A block diagram of a memory including a memory cell array and peripheral circuitry is provided for embodiments of this disclosure. For example... Figure 14 As shown in the present embodiment, the memory 300 includes: a memory cell array 302 and a peripheral circuit 304 coupled to the memory cell array 302; wherein, the memory cell array 302 includes a plurality of memory strings 310, and each memory string 310 includes a plurality of memory cells 308.

[0098] like Figure 14 As shown, each memory string 310 may include a source selection transistor 328 at its source terminal (e.g., Figure 14 (as shown in the dashed circle), the drain selector 330 at its drain terminal (as shown in the dashed circle). Figure 14(As shown in the dashed circle) and a plurality of memory cells 308 located between source select transistor 328 and drain select transistor 330, wherein the gate of source select transistor 328 is the source select gate (SSG) 312, and the gate of drain select transistor 330 is the drain select gate (DSG) 314. Source select gate 312 and drain select gate 314 can be configured to activate the selected memory string 310 (i.e., the column of the array) during read and program operations. In some embodiments, the sources of memory strings 310 in the same memory block 306 are coupled through the same source line (SL) 318 (e.g., a common source line). In other words, in some embodiments, all memory strings 310 in the same memory block 306 have a common source. In some embodiments, the drain of the drain select transistor 330 of each memory string 310 is coupled to a corresponding bit line 322, which can be accessed via an output bus ( Figure 14 Data is read from or written to bit line 322 (not shown). In some embodiments, each memory string 310 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of drain select transistor 330) or a deselect voltage (e.g., 0V) to the corresponding drain select gate 314 via one or more drain select gate lines 316 and / or by applying a selection voltage (e.g., higher than the threshold voltage of source select transistor 328) or a deselect voltage (e.g., 0V) to the corresponding source select gate 312 via one or more source select gate lines 320.

[0099] like Figure 14As shown, memory strings 310 can be organized into multiple memory blocks 306, each of which can have a source line 318 (e.g., a common source line coupled to ground). In some embodiments, each memory block 306 is the smallest unit for an erase operation, i.e., all memory cells 308 on the same memory block 306 are erased simultaneously. To erase memory cells 308 in a selected memory block, an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias the source lines 318 of the selected memory block and unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 308 of adjacent memory strings 310 can be coupled via word lines 324, which select which row of memory cells 308 is affected by read and program operations. In some embodiments, each word line 324 is coupled to a memory page 326 of memory cell 308, where the memory page 326 is the smallest unit for programming operations. The size of a memory page 326, in bits, can be related to the number of memory strings 310 coupled by word lines 324 in a memory block 306. Each word line 324 may include multiple control gates at each memory cell 308 in the corresponding memory page 326 and gate lines coupling the control gates.

[0100] Continue to refer to Figure 14 The peripheral circuitry 304 can be coupled to the memory cell array 302 via bit line 322, word line 324, source line 318, source-select-gate line 320, and drain-select-gate line 316. The peripheral circuitry 304 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 302 by applying voltage and / or current signals to each target memory cell 308 and sensing voltage and / or current signals from each target memory cell 308 via bit line 322, word line 324, source line 318, source-select-gate line 320, and drain-select-gate line 316. The peripheral circuitry 304 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0101] Continue to refer to Figure 14 This disclosure also provides a memory 300, which includes:

[0102] The storage cell array 302 includes multiple storage strings 310, and each storage string 310 includes multiple storage cells 308.

[0103] Peripheral circuit 304 is configured as follows:

[0104] When performing a read operation on a selected memory cell of a memory string, a pass voltage is applied to the word lines coupled to the unselected memory cells of the memory string according to the programming order of the selected memory cells;

[0105] The earlier the selected memory cell is programmed, the greater the voltage applied to the word line coupled to the unselected memory cell in the memory string during a read operation.

[0106] Here, the peripheral circuit 304 is configured to determine the pass voltage applied to the word line coupled to the unselected memory cell based on the programming order of the selected memory cell, that is, based on the degree of influence of the background image correlation effect on the selected memory cell. In this way, the influence of the background image correlation effect can be reduced, and read interference can be reduced.

[0107] In this embodiment of the present disclosure, each memory string 310 further includes a drain select transistor 330 and a source select transistor 328;

[0108] Peripheral circuit 304 is configured as follows:

[0109] When a read operation is performed on a selected memory cell of a memory string, the voltage applied to the word line coupled to the first unselected memory cell of the memory string is greater than the voltage applied to the word line coupled to the second unselected memory cell of the memory string; wherein, the first unselected memory cell includes an unselected memory cell located between the selected memory cell and the source select transistor, and the second unselected memory cell includes an unselected memory cell located between the selected memory cell and the drain select transistor.

[0110] In this embodiment of the disclosure, the peripheral circuit 304 is further configured as follows:

[0111] Before performing a read operation on a selected memory cell of a memory string, programmatic operations are performed on multiple memory cells of the memory string.

[0112] In this embodiment of the disclosure, when the programming operation is a forward programming operation, the peripheral circuit 304 is specifically configured as follows:

[0113] When performing a read operation on a selected memory cell of a memory string, the fewer the number of unselected memory cells between the selected memory cell and the source select transistor, the greater the pass voltage applied to the word line coupled to the unselected memory cell of the memory string.

[0114] In this embodiment of the disclosure, when the programming operation is a reverse programming operation, the peripheral circuit 304 is specifically configured as follows:

[0115] When performing a read operation on a selected memory cell of a memory string, the fewer the number of unselected memory cells between the selected memory cell and the drain select transistor, the greater the through voltage applied to the word line coupled to the unselected memory cell of the memory string.

[0116] In this embodiment of the disclosure, the peripheral circuit 304 is further configured as follows:

[0117] Before performing a read operation on a selected storage unit of a storage string, the multiple storage units of the storage string are divided into multiple storage groups according to the programming order.

[0118] In this embodiment of the disclosure, the peripheral circuit 304 is further configured as follows:

[0119] According to the programming order, the multiple storage units of the storage string are divided into the first storage group, the second storage group, and the third storage group;

[0120] The programming order of the first storage group is earlier than that of the second storage group, and the programming order of the second storage group is earlier than that of the third storage group.

[0121] When the selected memory cell belongs to the first memory group, a first pass voltage is applied to the word line coupled to the unselected memory cell in the memory string during a read operation; when the selected memory cell belongs to the second memory group, a second pass voltage is applied to the word line coupled to the unselected memory cell in the memory string during a read operation; when the selected memory cell belongs to the third memory group, a third pass voltage is applied to the word line coupled to the unselected memory cell in the memory string during a read operation.

[0122] Among them, the first through voltage is greater than the second through voltage, and the second through voltage is greater than the third through voltage.

[0123] In this embodiment of the disclosure, the peripheral circuit 304 is further configured as follows:

[0124] When the selected memory cell belongs to the second memory group, during a read operation, a first sub-pass voltage is applied to the word line coupled to the unselected memory cell between the selected memory cell and the source select transistor, and during a read operation, a second sub-pass voltage is applied to the word line coupled to the unselected memory cell between the selected memory cell and the drain select transistor; wherein, the first sub-pass voltage is greater than the second sub-pass voltage.

[0125] refer to Figure 15 , Figure 15 A block diagram of a system including a memory, provided for embodiments of this disclosure. (e.g.) Figure 15As shown, this disclosure also provides a memory system 402, which includes: a memory 300 as described above; and a controller 404 coupled to the memory 300 and configured to control the memory 300.

[0126] In some embodiments, memory 300 may be any memory disclosed herein. As disclosed in detail below, memory 300 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) may have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0127] In some embodiments, controller 404 may be configured to control operations of memory 300, such as read, erase, and program operations. Controller 404 may also be configured to manage various functions relating to data stored or to be stored in memory 300, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In other embodiments, controller 404 is also configured to process error correcting codes (ECCs) relating to data read from or written to memory 300.

[0128] In some embodiments, controller 404 may also perform any other suitable function, such as formatting memory 300. Controller 404 may communicate with external devices (e.g., host 406) according to a specific communication protocol. For example, controller 404 may communicate with external devices through at least one of various interface protocols, such as Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0129] In some embodiments, the controller 404 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, USB flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0130] In some embodiments, the controller 404 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0131] Continue to refer to Figure 15 System 400 may include host 406 and memory system 402, memory system 402 having one or more memories 300 and controller 404.

[0132] In some embodiments, host 406 may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 406 may be configured to send data to or receive data from memory 300. System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0133] In some embodiments, controller 404 is coupled to memory 300 and host 406 and is configured to control memory 300. Controller 404 can manage data stored in memory 300 and communicate with host 406.

[0134] The controller 404 and one or more memories 300 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 402 can be implemented and packaged into different types of end electronic products.

[0135] refer to Figure 16 , Figure 16 This is a schematic diagram of a memory card including a memory, provided for an embodiment of this disclosure. (See diagram below.) Figure 16 As shown in this embodiment, the controller 404 and a single memory 300 can be integrated into a memory card 502. The memory card 502 may include Personal Computer Memory Card International Association (PCMCIA) cards, CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 may also include a connector for connecting the memory card 502 to a host computer (e.g., ...). Figure 15 The memory card connector 504 is coupled to the host 406.

[0136] refer to Figure 17 , Figure 17This is a schematic diagram of a solid-state drive including a memory, provided as an embodiment of this disclosure. Figure 17 As shown in this embodiment, the controller 404 and multiple memories 300 can be integrated into a solid-state drive 506. The solid-state drive 506 may also include components for connecting the solid-state drive 506 to a host computer (e.g., ...). Figure 15 The solid-state drive connector 508 is coupled to the host 406. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 506 is greater than the storage capacity and / or operating speed of the memory card 502.

[0137] refer to Figure 18 , Figure 18 A block diagram of an electronic device including a memory system provided for embodiments of this disclosure. For example... Figure 18 As shown in the embodiments of this disclosure, an electronic device 600 is also provided, which includes a memory system 402 as described in the above technical solution. The electronic device includes mobile phones, desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, wearable devices, or power banks, etc.

[0138] This disclosure also provides a computer-readable storage medium having a computer program stored thereon, which, when executed, can implement the operation methods in the above-described technical solutions.

[0139] In this embodiment of the disclosure, the computer-readable storage medium may include: random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, read-only optical disk (CD-ROM), or any other form of program code medium known in the art.

[0140] This disclosure provides a memory and its operating method, a memory system, and an electronic device. The operating method includes: when performing a read operation on selected memory cells of a memory string, applying a voltage to word lines coupled to unselected memory cells of the memory string according to the programming order of the selected memory cells; wherein, the earlier the programming order of the selected memory cells, the greater the voltage applied to the word lines coupled to the unselected memory cells during the read operation. In this disclosure, the voltage applied to the word lines coupled to the unselected memory cells is determined according to the programming order of the selected memory cells, i.e., according to the degree to which the selected memory cells are affected by background image correlation effects. This reduces the impact of background image correlation effects and reduces read interference.

[0141] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0142] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for operating a memory, characterized in that, The memory includes multiple memory strings, each memory string including a drain-select transistor, a source-select transistor, and multiple memory cells. The operation method includes: When performing a read operation on a selected memory cell of a memory string, a pass voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cell; when performing a read operation on a selected memory cell of a memory string, the pass voltage applied to the word line coupled to the first unselected memory cell of the memory string is greater than the pass voltage applied to the word line coupled to the second unselected memory cell of the memory string; wherein, the first unselected memory cell includes an unselected memory cell located between the selected memory cell and the source select transistor, and the second unselected memory cell includes an unselected memory cell located between the selected memory cell and the drain select transistor; The earlier the selected memory cell is programmed, the greater the voltage applied to the word line coupled to the unselected memory cell in the memory string during a read operation.

2. The method for operating the memory according to claim 1, characterized in that, Before performing a read operation on a selected storage unit of the storage string, the operation method further includes: Programming operations are performed on the plurality of storage units of the storage string.

3. The method for operating the memory according to claim 2, characterized in that, When the programming operation is a forward programming operation, during the read operation on a selected memory cell of the memory string, a pass voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cells, including: When a read operation is performed on a selected memory cell of a memory string, the fewer the number of unselected memory cells between the selected memory cell and the source select transistor, the greater the pass voltage applied to the word line coupled to the unselected memory cell of the memory string.

4. The method for operating the memory according to claim 2, characterized in that, When the programming operation is a reverse programming operation, during the read operation on a selected memory cell of the memory string, a pass voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cells, including: When a read operation is performed on a selected memory cell of a memory string, the fewer the number of unselected memory cells between the selected memory cell and the drain select transistor, the greater the pass voltage applied to the word line coupled to the unselected memory cell of the memory string.

5. The method for operating the memory according to claim 1, characterized in that, Before performing a read operation on a selected storage unit of the storage string, the operation method further includes: According to the programming order, the multiple storage units of the storage string are divided into multiple storage groups.

6. The method of operating the memory according to claim 5, characterized in that, The step of dividing the multiple storage units of the storage string into multiple storage groups according to the programming order includes: According to the programming order, the plurality of storage units of the storage string are divided into a first storage group, a second storage group, and a third storage group; The programming order of the first storage group is earlier than that of the second storage group, and the programming order of the second storage group is earlier than that of the third storage group. When the selected memory cell belongs to the first memory group, a first pass voltage is applied to the word line coupled to the unselected memory cell of the memory string during a read operation; when the selected memory cell belongs to the second memory group, a second pass voltage is applied to the word line coupled to the unselected memory cell of the memory string during a read operation; when the selected memory cell belongs to the third memory group, a third pass voltage is applied to the word line coupled to the unselected memory cell of the memory string during a read operation. Wherein, the first through voltage is greater than the second through voltage, and the second through voltage is greater than the third through voltage.

7. The method of operating the memory according to claim 6, characterized in that, When the selected memory cell belongs to the second memory group, during a read operation, a first sub-pass voltage is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the source select transistor, and during a read operation, a second sub-pass voltage is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the drain select transistor; wherein, the first sub-pass voltage is greater than the second sub-pass voltage.

8. A memory, characterized in that, The memory includes: A memory cell array includes multiple memory strings, each memory string including a drain select transistor, a source select transistor and multiple memory cells; Peripheral circuitry, wherein the peripheral circuitry is configured as follows: When performing a read operation on a selected memory cell of a memory string, a pass voltage is applied to the word line coupled to the unselected memory cell of the memory string according to the programming order of the selected memory cell; when performing a read operation on a selected memory cell of a memory string, the pass voltage applied to the word line coupled to the first unselected memory cell of the memory string is greater than the pass voltage applied to the word line coupled to the second unselected memory cell of the memory string; wherein, the first unselected memory cell includes an unselected memory cell located between the selected memory cell and the source select transistor, and the second unselected memory cell includes an unselected memory cell located between the selected memory cell and the drain select transistor; The earlier the selected memory cell is programmed, the greater the voltage applied to the word line coupled to the unselected memory cell in the memory string during a read operation.

9. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: Before performing a read operation on a selected storage cell of the storage string, a plurality of the storage cells of the storage string are programmed.

10. The memory according to claim 9, characterized in that, When the programming operation is a forward programming operation, the peripheral circuit is specifically configured as follows: When a read operation is performed on a selected memory cell of a memory string, the fewer the number of unselected memory cells between the selected memory cell and the source select transistor, the greater the pass voltage applied to the word line coupled to the unselected memory cell of the memory string.

11. The memory according to claim 9, characterized in that, When the programming operation is a reverse programming operation, the peripheral circuit is specifically configured as follows: When a read operation is performed on a selected memory cell of a memory string, the fewer the number of unselected memory cells between the selected memory cell and the drain select transistor, the greater the pass voltage applied to the word line coupled to the unselected memory cell of the memory string.

12. The memory according to claim 8, characterized in that, The peripheral circuit is also configured to: Before performing a read operation on a selected storage unit of a storage string, the multiple storage units of the storage string are divided into multiple storage groups according to the programming order.

13. The memory according to claim 12, characterized in that, The peripheral circuit is also configured to: According to the programming order, the plurality of storage units of the storage string are divided into a first storage group, a second storage group, and a third storage group; The programming order of the first storage group is earlier than that of the second storage group, and the programming order of the second storage group is earlier than that of the third storage group. When the selected memory cell belongs to the first memory group, a first pass voltage is applied to the word line coupled to the unselected memory cell of the memory string during a read operation; when the selected memory cell belongs to the second memory group, a second pass voltage is applied to the word line coupled to the unselected memory cell of the memory string during a read operation; when the selected memory cell belongs to the third memory group, a third pass voltage is applied to the word line coupled to the unselected memory cell of the memory string during a read operation. Wherein, the first through voltage is greater than the second through voltage, and the second through voltage is greater than the third through voltage.

14. The memory according to claim 13, characterized in that, The peripheral circuit is also configured to: When the selected memory cell belongs to the second memory group, during a read operation, a first sub-pass voltage is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the source select transistor, and during a read operation, a second sub-pass voltage is applied to the word line coupled to the unselected memory cell located between the selected memory cell and the drain select transistor; wherein, the first sub-pass voltage is greater than the second sub-pass voltage.

15. A memory system, characterized in that, The memory system includes: The memory as described in any one of claims 8 to 14; and A controller coupled to the memory and configured to control the memory.

16. An electronic device, characterized in that, The electronic device includes: the memory system as described in claim 15.

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