A memory operation method, a memory reading method, a memory and a storage system

Abstract

Embodiments of the present application provide a memory operation method, a memory reading method, a memory and a storage system. The memory operation method comprises: determining a first variation of a threshold voltage of a memory cell in a single layer cell (SLC) erase state; comparing the first variation with a reference threshold value; and when a comparison result is that a set relationship is not met between the first variation and the reference threshold value, adjusting the threshold voltage of the memory cell in the SLC erase state to have a second variation, so that the set relationship is met between the second variation and the reference threshold value.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a memory operation method, a memory reading method, a memory, and a storage system. Background Technology

[0002] Recently, with the development of memory, memory can be either volatile or non-volatile. Non-volatile memory can retain data even when no power is applied, and therefore has been widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. One example is the widespread application of 3D charge-trapping flash memory (CTF). 3D charge-trapping flash memory achieves its data storage function by trapping and storing charge in the gate dielectric layer of its contained memory cells. Random telegraph noise (RTN) caused by charge trapping and loss in the gate dielectric layer of the memory cells can affect the correctness of reading the data stored in the memory cells. Summary of the Invention

[0003] In view of this, this application provides a memory operation method, a read method, a memory, and a storage system, which adjusts the amplitude of the RTN corresponding to the storage cell to reduce read interference caused by the RTN.

[0004] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0005] In a first aspect, embodiments of this application provide a method for operating a memory, including:

[0006] Determine the first change in the threshold voltage of the memory cell in the memory during the single-level cell (SLC) erase state;

[0007] Compare the first change with the reference threshold;

[0008] When the comparison result shows that the first change amount and the reference threshold do not satisfy the set relationship, the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change amount, so that the second change amount and the reference threshold satisfy the set relationship.

[0009] Secondly, embodiments of this application also provide a method for reading a memory, including:

[0010] When performing a read operation on a memory cell, a read voltage is provided to the selected word line coupled to the memory cell;

[0011] Provide a pass voltage to the unselected word line that is coupled to other memory cells in the same memory cell string as the memory cell;

[0012] The voltage is determined based on the total recorded offset and the default voltage.

[0013] Thirdly, embodiments of this application also provide a memory, including: a memory array, the memory array including memory cells;

[0014] and peripheral circuitry coupled to the memory array and configured to control the memory array;

[0015] The peripheral circuit is configured to operate as described in any of the preceding descriptions.

[0016] Fourthly, embodiments of this application also provide a storage system, including: one or more of the aforementioned memories; and a memory controller coupled to the memories; the memory controller being configured to: send various operation commands to the memories.

[0017] This application provides an operation method, a reading method, a memory, and a storage system for a memory. The operation method includes: determining a first change in the threshold voltage of a memory cell in a single-level cell (SLC) erase state; comparing the first change with a reference threshold; and adjusting the threshold voltage of the memory cell in the SLC erase state to have a second change when the comparison result indicates that the first change does not satisfy a predetermined relationship with the reference threshold, such that the second change satisfies the predetermined relationship with the reference threshold. The memory operation method provided in this application compares the RTN (Read Tolerance Node) of the memory cell with a reference threshold, and adjusts the comparison result to satisfy the predetermined relationship when it does not satisfy the predetermined relationship, thereby reducing read interference caused by the RTN. In layman's terms, the operation method provided in this application embodiment is to adjust the amplitude of the RTN of the memory cell (the change in the threshold voltage during the SLC erase state of the memory cell characterizes the amplitude of the RTN) to a known minimum amplitude (reference threshold, for example, this minimum RTN amplitude can be the amplitude of the RTN corresponding to the memory cell adjacent to the bit line) so as to reduce read interference caused by RTN so as to be able to correctly read the data stored in the memory cell. Attached Figure Description

[0018] The aspects of this application can be best understood from the following specific embodiments when read in conjunction with the accompanying drawings. Note that, according to standard practice in industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0019] Figure 1 A block diagram of an exemplary system with memory in the related art is shown;

[0020] Figure 2 A schematic diagram of an exemplary memory card with memory is shown;

[0021] Figure 3 A schematic diagram showing an exemplary solid-state drive (SSD) with memory is shown;

[0022] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown;

[0023] Figure 5 A side view of a cross section of an exemplary memory array comprising strings of memory cells, according to some aspects of this application, is shown;

[0024] Figure 6 A block diagram of an exemplary memory including a storage array and peripheral circuitry is shown.

[0025] Figure 7 A schematic diagram showing the threshold voltage distribution of an MLC-type memory cell;

[0026] Figure 8 A schematic diagram showing the threshold voltage distribution of a TLC type memory cell;

[0027] Figure 9 A schematic diagram showing the threshold voltage distribution of a QLC type memory cell;

[0028] Figure 10 A schematic diagram illustrating three factors that affect the RWM of a memory cell is shown.

[0029] Figure 11 This illustration shows a flowchart of a memory operation method provided in an embodiment of this application;

[0030] Figure 12 This application provides a schematic flowchart for determining the first change in random telegraph noise according to an embodiment of the present application. Figure 1 ;

[0031] Figure 13 A schematic diagram of the read voltage in the first read condition is shown;

[0032] Figure 14 This application provides a schematic flowchart for determining the first change in random telegraph noise according to an embodiment of the present application. Figure 2 ;

[0033] Figure 15 This application provides a schematic flowchart for determining the first change in random telegraph noise according to an embodiment of the present application. Figure 3 ;

[0034] Figure 16 This diagram illustrates the distribution of threshold voltage changes in memory cells coupled to word lines WL0, WL31, and WL63 during SLC erase state, as provided in an embodiment of this application.

[0035] Figure 17 This diagram illustrates the 3σ distribution of the threshold voltage variation of each word-line coupled memory cell in the SLC erase state, as provided in an embodiment of this application.

[0036] Figure 18 This diagram illustrates the process of adjusting the amount of change in the SLC erase state of the storage unit provided in the embodiments of this application;

[0037] Figure 19 This illustration shows a flowchart of an embodiment of the present application, illustrating the timing for adjusting the amount of change in the SLC erase state of a storage cell.

[0038] Figure 20 The diagram shows a flowchart of the reading method provided in an embodiment of this application;

[0039] Figure 21 This application illustrates a CTF utilization method including 64 word lines provided in an embodiment. Figure 18 A flowchart illustrating the process of determining the total offset of the pass voltage applied to the unselected word line coupled to the unselected memory cell relative to the default pass voltage;

[0040] Figure 22 This illustration shows a flowchart of an embodiment of the present application for determining whether RTN adjustment is needed for the current programming / erasing count;

[0041] Figure 23 This illustration shows a flowchart of an embodiment of the present application that adjusts the magnitude of the RTN for unselected memory cells when the current number of programming / erasing cycles reaches a preset number. Detailed Implementation

[0042] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this application. Of course, these are merely examples and not limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0043] Furthermore, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein for ease of description to describe the relationship between one element or feature and (one or more) another element or feature as shown in the figures. Spatial relative terms are intended to cover different orientations in the use or operation of the device other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0044] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0045] Figure 1 A block diagram of an exemplary system with memory in the related art is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. For example... Figure 1 As shown, system 100 may include a host 108 and a storage system 102, wherein the storage system 102 has one or more memories 104 and a memory controller 106; the host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), wherein the SoC may be, for example, an application processor (AP). The host 108 may be configured to send data to or receive data from the memory 104. Specifically, the memory 104 may be any memory disclosed in this application, such as phase-change random access memory (PCRAM), three-dimensional NAND flash memory, etc.

[0046] According to some embodiments, memory controller 106 is coupled to memory 104 and host 108, and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as on Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones in low duty cycle environments. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment, such as on solid-state drives (SSDs) or embedded multimedia cards (eMMCs), where SSDs or eMMCs are used as data storage for mobile devices in high duty cycle environments such as smartphones, tablets, and laptops, as well as enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECCs) relating to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0047] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a connector for the memory card to a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 3 In another example shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 302. The SSD may also include components for connecting the SSD to a host computer (e.g., Figure 1 The SSD connector 304 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card. Furthermore, the memory controller 106 can also be configured to control erase, read, and write operations of the memory 104.

[0048] Figure 4 A schematic diagram of an exemplary memory including peripheral circuitry is shown. Figure 4As shown, memory 104 may include a memory array 401 and peripheral circuitry 402 coupled to the memory array 401. The memory array 401 may be a NAND flash memory array, wherein memory cells 406 are provided in the form of an array of NAND memory strings 408, each NAND memory string 408 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 408 includes a plurality of memory cells 406 coupled in series and stacked vertically. Each memory cell 406 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the storage region of the memory cell 406. Each memory cell 406 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0049] In some embodiments, each memory cell 406 is a single-level cell (SLC) having two possible data states and thus capable of storing one bit of data. For example, a first data state "0" may correspond to a first voltage range, and a second data state "1" may correspond to a second voltage range. In some embodiments, the first and second voltage ranges may be referred to as the threshold voltage distribution of the memory cell. In some embodiments, each memory cell 406 is a multi-level cell (MLC) capable of storing a single bit of data in multiple four data states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary level cell (TLC), or four bits per cell (also known as a quadruple level cell (QLC)). Regardless of the application type, the data states of the memory cell include an erase state and a programmable state. When performing a programming operation on the memory cell, the memory cell in the erase state is programmed to a certain programming state. Generally, the voltage value in the voltage range corresponding to the programming state of the memory cell is relatively large.

[0050] like Figure 4As shown, each NAND memory string 408 may include a source select gate (SSG) 410 at its source end and a drain select gate (DSG) 412 at its drain end. SSG 410 and DSG 412 can be configured to activate the selected NAND memory string 408 (column of the array) during read and program (or write) operations. In some embodiments, the sources of NAND memory strings 408 in the same block 404 are coupled via the same source line (SL) 414 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some embodiments, the DSG 412 of each NAND memory string 408 is coupled to a corresponding bit line 416, from which data can be read and written via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG412) or a deselection voltage (e.g., 0 volts (V)) to the corresponding DSG412 via one or more DSG lines 413 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG410) or a deselection voltage (e.g., 0V) to the corresponding SSG410 via one or more SSG lines 415.

[0051] like Figure 4As shown, NAND memory strings 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to ground). In some embodiments, each block 404 is a basic data unit with an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase memory cells 406 in a selected block 404, a source line 414 biased to the selected block 404 and unselected blocks 404 on the same plane as the selected block 404 can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks. Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 receives read and program operations. In some embodiments, memory cells 406 coupled to the same word line 418 are referred to as pages 420. A page 420 is a basic unit of data used for programming or reading operations, and the size of a page 420, measured in bits, can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) at each memory cell 406 within the corresponding page 420, as well as gate lines coupling the control gates.

[0052] Figure 5 A side view of a cross-section of an exemplary memory array 401 including NAND memory cell strings 408 according to some aspects of this application is shown. Figure 5 As shown, the NAND memory cell string 408 can extend vertically through the memory stack layer 502 above the substrate 501. The substrate 501 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0053] The memory stack layer 502 may include alternating gate conductive layers 503 and gate-to-gate dielectric layers 504. The number of pairs of gate conductive layers 503 and gate-to-gate dielectric layers 504 in the memory stack layer 502 determines the number of memory cells 406 in the memory array 401. The gate conductive layers 503 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 503 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 503 includes a doped polysilicon layer. Each gate conductive layer 503 may include a control gate surrounding the memory cell 406 and may extend laterally at the top of the memory stack layer 502 as a DSG line 413, at the bottom of the memory stack layer 502 as an SSG line 415, or between DSG lines 413 and SSG lines 415 as a word line 418.

[0054] like Figure 5 As shown, the NAND memory cell string 408 includes a channel structure 505 extending vertically through the memory stack layer 502. In some embodiments, the channel structure 505 includes channel holes filled with one or more semiconductor materials and one or more dielectric materials. In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure 505 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0055] Return to reference Figure 4Peripheral circuitry 402 can be coupled to memory array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 401 by applying voltage and / or current signals to each target memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413, and by sensing voltage and / or current signals from each target memory cell 406. Peripheral circuitry 402 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 402 includes a page buffer / sensor amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic unit 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional components may be included. Figure 6 Additional peripheral circuitry not shown.

[0056] Page buffer / sensor amplifier 604 can be configured to read data from memory array 401 and program (write) data to memory array 401 according to control signals from control logic unit 612. In one example, page buffer / sensor amplifier 604 can store a page of programming data (write data) to be programmed into a page 420 of memory array 401. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 406 coupled to selected word line 418. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 416 representing a data bit stored in memory cell 406 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic unit 612 and select one or more NAND memory strings 408 by applying a bit line voltage generated from voltage generator 610.

[0057] The row decoder / word line driver 608 can be configured to be controlled by the control logic unit 612 and to select / deselect block 404 of the memory array 401 and to select / deselect word line 418 of block 404. The row decoder / word line driver 608 can also be configured to drive word line 418 using word line voltages generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive SSG line 415 and DSG line 413. As described in detail below, the row decoder / word line driver 608 is configured to perform an erase operation on memory cell 406 coupled to one or more selected word lines 418. The voltage generator 610 can be configured to be controlled by the control logic unit 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.

[0058] Control logic unit 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 614 can be coupled to control logic unit 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic unit 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 612, as well as to buffer status information received from control logic unit 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bit line driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 401.

[0059] For the storage system and memory described above, the Read Window Margin (RWM) is a crucial parameter for correctly reading data from storage cells. There are two definitions of RWM: First, RWM is the sum of the intervals between the threshold voltage distributions corresponding to two adjacent data states of a storage cell, for example... Figure 7 The threshold voltage distribution of the MLC type memory cell is illustrated. For example... Figure 7 As shown, the first RWM of an MLC-type memory cell can be the voltage range between the erase state S1 and the programmable state S2. Alternatively, the RWM can be defined as the voltage range between the programming verification voltage of the memory cell's programming state and the read voltage used to distinguish the programming state from its adjacent data state, for example... Figure 7 The RWM included is: V RD1 To VFY1 The voltage range between, V RD2 To V FY2 The voltage range between and V RD3 To V FY3 The voltage range between, where V RD1 V RD2 V RD3 To distinguish the read voltage between erase state S1 and programming state S2, the read voltage between erase state S2 and programming state S3, and the read voltage between erase state S3 and programming state S4; V FY1 V FY2 V FY3 These are the programming verification voltages for programming state S2, programming state S3, and programming state S4, respectively. As the data density that a single memory cell can store further increases, the width of the RWM decreases, for example... Figure 8 The threshold voltage distribution of the TLC type memory cell shown and Figure 9 The threshold voltage distribution of the QLC type memory cell shown, and the RWM ratio exhibited by the two. Figure 7 The MLC type memory cell shown has a narrower read width (RWM). A sufficiently wide RWM is required to correctly read data from the memory cell during a read operation. Many factors influence the RWM, such as... Figure 10 As shown, this diagram illustrates three main factors affecting read read performance (RWM) of a memory cell. Among these factors, the impact of programming precision and word line coupling on RWM has been extensively studied, but research on the impact of read frequency response (RTN) on RWM and how to reduce read interference caused by RTN is relatively limited.

[0060] Research indicates that Resonant Voltage Noise (RTN) caused by electron trapping and loss in memory cells is one of the main factors contributing to threshold voltage fluctuations in planar NAND flash memory during read operations. These threshold voltage fluctuations cause changes in Residual Voltage Width (RWM), meaning that RTN affects RWM and consequently, the correct retrieval of data stored in the memory cell. RTN is a non-Gaussian noise inherent in electronic devices, caused by charge migration disturbances resulting from the trapping and release of charges by defects or traps within the device; macroscopically, this manifests as current fluctuations. Therefore, for memories containing a channel structure 505 made of polysilicon, such as 3D NAND flash memory or 3D charge trap flash memory (CTF), the channel structure 505 containing polysilicon has defects or pitfalls. Combined with the aforementioned description of the principle of data storage in memory cells, the charge trapping layer of the memory cell needs to capture and release charges to store and erase data. In this case, the presence of RTN in the channel corresponding to the memory cell will cause fluctuations in the threshold voltage of the memory cell, thereby affecting the RWM of the memory and thus affecting the correct reading of the memory cell.

[0061] To solve the above technical problems, see Figure 11 This application provides a method for operating a memory. Specifically, the method includes:

[0062] S1101: Determine the first change in the threshold voltage of the memory cell in the memory when it is in the single-cell (SLC) erase state.

[0063] It should be noted that the structure of the memory described herein may include the aforementioned Figures 1 to 7 The described structure may also include other known structures. Essentially, the memory includes a string of memory cells, which comprises sequentially electrically connected bit lines, multiple memory cells, and source lines. Each layer of the multiple memory cells is coupled to the same word line, forming a physical memory page. Further descriptions of the structure of the string of memory cells can be found above. Figures 1 to 6 This will not be elaborated upon here.

[0064] Because numerous factors influence the read-time mean squared (RWM) of a memory cell, to eliminate the influence of other factors and address only the read interference caused by the impact of read frequency (RTN) on RWM, research has shown that the amplitude of the RTN corresponding to a memory cell can be measured by the change in the threshold voltage of the memory cell during SLC erasure. Furthermore, the amplitude of the RTN is positively correlated with the change in the threshold voltage of the memory cell during SLC erasure; the greater the change in the threshold voltage of the memory cell during SLC erasure, the greater the amplitude of the RTN corresponding to the memory cell. Additionally, the impact of the RTN corresponding to a memory cell on the RWM of the memory cell is also positively correlated with the amplitude of the RTN; that is, the greater the amplitude of the RTN, the greater its impact on the threshold voltage distribution of the memory cell, thus leading to a greater impact on the RWM (narrowing the RWM), and consequently, greater interference during read operations. In other words, the change in the threshold voltage of the memory cell during single-level cell SLC erasure is used to measure the amplitude of the RTN corresponding to the memory cell.

[0065] In some embodiments, for step S1101, an optional implementation may be found in [reference needed]. Figure 12 The specific process may include:

[0066] S1201: Perform an erase operation on the storage block where the storage unit is located, so that all the storage units contained in the storage block are erased to the SLC erase state;

[0067] S1202: Perform multiple read operations on the storage unit based on the first read condition;

[0068] S1203: Obtain the voltage value of the threshold voltage of the memory cell read each time;

[0069] S1204: Determine the first change amount based on each voltage value.

[0070] It should be noted that, as explained above, the magnitude of the RTN corresponding to a memory cell is measured based on the change in the threshold voltage of the memory cell in the SLC erase state. Therefore, it is necessary to perform an erase operation on the memory block containing the memory cell to bring the memory cell to the SLC erase state. Thus, the first step in obtaining the first change in the threshold voltage of the memory cell in the SLC erase state is to perform an erase operation on the memory block containing the memory cell, so that all memory cells contained in the memory block are erased to the SLC erase state.

[0071] Subsequently, multiple read operations are performed on the storage unit according to the first read condition. The number of reads can be designed according to specific circumstances and is not limited here. In one example, the storage unit can be read 10 times consecutively according to the first read condition.

[0072] Here, the first read condition may include:

[0073] A set of read voltages is applied to the selected word line coupled to the memory cell;

[0074] Apply a default pass voltage to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell;

[0075] The set of read voltages includes a set of voltage values ​​between the minimum and maximum voltage values ​​of the threshold voltage distribution corresponding to the SLC erase state.

[0076] Here, the set of read voltages refers to a set of voltage values ​​between the minimum and maximum voltage values ​​of the threshold voltage distribution corresponding to the SLC erase state. For example... Figure 13 The diagram illustrates the threshold voltage distribution of an SLC-type memory cell according to an embodiment of the present invention. The threshold voltage distribution corresponding to the L0 state is the same as the threshold voltage distribution corresponding to the SLC erase state. The memory cell is erased to the L0 state when multiple read operations are performed consecutively. An example of the set of read voltages is... Figure 13 The V1 to V7 mentioned above.

[0077] The aforementioned multiple read operations performed on the memory cell based on the first read condition can refer to continuously performing multiple rounds of read operations on the memory cell according to the first read condition. In each round of read operations, the read voltage applied to the selected word line coupled to the memory cell is sequentially applied by scanning the maximum value from the set of read voltages. A corresponding default pass voltage Vpass0 is applied to the unselected word lines coupled to other memory cells belonging to the same memory cell string as the memory cell. Then, the threshold voltage values ​​of the multiple memory cells in this round of read operations are calculated. Multiple rounds of read operations are performed sequentially to obtain multiple voltage values ​​for each round of read operations. Then, the first change amount is determined based on each voltage value.

[0078] For example, suppose we consider one example of a set of read voltages, namely... Figure 13 V1 to V7 refer to the process of performing a certain round of read operations on the memory cell, that is, applying the read voltage from V1 to V7 sequentially to the selected word line coupled to the memory cell. In this round, during each read operation, a default pass voltage Vpass0 is applied to the unselected word lines in the other memory cell strings. The threshold voltage value of each read operation of the memory cell is measured based on the sensing amplifier circuit included in the peripheral circuit.

[0079] It should be noted that when performing a read operation on the memory, the memory cell to be read in a certain memory cell string is the selected memory cell, and the word line coupled to the memory cell is the selected word line; during the same read operation, other memory cells in the same memory cell string that do not need to be read are unselected memory cells, and the word line coupled to the unselected memory cells is the unselected word line.

[0080] The default pass voltage Vpass0 mentioned above refers to the voltage value provided to the unselected word line coupled to the unselected memory cell when performing a read operation on the memory. It can be an empirical value or a factory default value.

[0081] After performing multiple read operations on the storage unit, in some embodiments, step S1203 may include:

[0082] The average voltage value of the threshold voltage of the memory cell is obtained based on each of the voltage values;

[0083] The first change is determined based on any one of the voltage values ​​and the average voltage value.

[0084] Specifically, the first change can be calculated using the following formula:

[0085] ΔV th0 =V th,i -V th,avg (1)

[0086] Where, ΔV th0 V is the first change in the threshold voltage of the memory cell during the SLC erase state; th,i V represents the threshold voltage value of the memory cell measured during the i-th read operation in a multi-round read operation, where i is any one of the multi-round read operations; th,avg The average value is the average voltage value of the threshold voltage of the storage cell measured by the multiple read operations.

[0087] The above calculation formula means that the first change is determined based on any one of the voltage values ​​and the average voltage value.

[0088] In other embodiments, for step 1102, see [link to relevant documentation]. Figure 14 This demonstrates another alternative implementation method. The specific process may include:

[0089] S1401: Perform an erase operation on the storage block where the storage unit is located, so that all the storage units contained in the storage block are erased to the SLC erase state;

[0090] S1402: Based on the first read condition, perform multiple read operations on each memory cell coupled to the selected word line to obtain the distribution of the change in the threshold voltage of each memory cell; the selected word line is the word line in the memory block coupled to the memory cell;

[0091] S1403: Determine 3σ of the distribution of the change as the first change.

[0092] It should be noted that step S1401 is the same as the aforementioned step S1201, and will not be repeated here. In the actual reading process, the first change amount can also be 3σ, which is the change in the threshold cell distribution of the storage cell in the SLC erase state. The methods for obtaining 3σ can include, but are not limited to, the following two methods: one method is to perform the aforementioned... Figure 12 One approach is to obtain the change in threshold voltage for each memory cell in the SLC erase state, thus forming a distribution of the change in the SLC erase state, and then determine the corresponding 3σ based on this distribution; another approach is to perform the aforementioned steps on each memory cell in all memory cells within the same memory block as the memory cell. Figure 12 The steps are as follows: obtain the change in threshold voltage corresponding to each memory cell in the SLC erase state to form the change distribution in the SLC erase state, and then determine the corresponding 3σ based on this change distribution.

[0093] In some embodiments, the method further includes: waiting for a first preset time after performing an erase operation on the storage block.

[0094] It should be noted that the above-mentioned erasure operation and waiting period are to avoid the influence of Background Pattern Dependency (BPD) response and the unstable charge of the storage cells contained in the storage block immediately after erasure. The first preset duration can be set according to actual conditions. For example, the first preset duration can be 30 minutes.

[0095] Based on the foregoing description, a specific and feasible process for evaluating the magnitude of the RTN of the storage cell is as follows: Figure 15 As shown, it may include:

[0096] S1501: Perform an erase operation on the storage block where the storage unit is located, so that all the storage units contained in the storage block are erased to the SLC erase state;

[0097] S1502: Wait 30 minutes after the erase operation;

[0098] S1503: Read the storage block or the storage unit 10 times consecutively according to the first reading condition;

[0099] S1504: Calculate the distribution of the change in threshold voltage of the memory cells contained in the memory block or the change in threshold voltage of the memory cells.

[0100] S1505: Take the change as the first change; or obtain 3σ of the change distribution and take the 3σ as the first change.

[0101] It should be noted that this is only an example to illustrate how to evaluate the magnitude of the RTN corresponding to the memory cell. The calculation of the change in the threshold voltage of the memory cell in step S1504, or the 3σ of the change distribution, has already been explained in detail above and will not be repeated here.

[0102] S1102: Compare the first change with the reference threshold.

[0103] Here, the reference threshold can be an evaluation value of the RTN amplitude corresponding to the memory cell with the least read interference caused by RTN in the memory. Studies have shown that, as Figure 16 and Figure 17 As shown, within the same memory cell string, the amplitude of the RTN decreases sequentially from the cell closest to the source line to the cell closest to the bit line. This means that the RTN amplitude corresponding to the memory cell adjacent to the bit line is the smallest, thus having the least impact on the RWM of the memory cell. Therefore, the first change in the threshold voltage of the memory cell is compared with a reference threshold. If the comparison result shows that the first change and the reference threshold do not satisfy a set relationship, the relationship is adjusted to satisfy the set relationship, thereby reducing the amplitude of the RTN corresponding to the memory cell and thus reducing read interference caused by RTN. It should be noted that... Figure 16 The vertical axis represents the probability value, which can refer to the probability that all memory cells coupled to a word line are subject to a certain threshold voltage change. This probability can be obtained by comparing the number of memory cells subject to a certain threshold voltage change with the total number of memory cells coupled to a word line. Figure 16 The horizontal axis represents the change in the threshold voltage of the storage cell in the SLC erase state under the first read condition. Figure 16 The distribution of threshold voltage variation of memory cells on word lines WL0, WL31, and WL63 in the SLC erase state is depicted, wherein word lines WL0, WL31, and WL63 are positioned sequentially from bottom to top in the memory cell string (or, sequentially deployed from near the source line to near the bit line in the memory cell string). Figure 17 The horizontal axis represents the character line; the vertical axis represents the size of 3σ.

[0104] Therefore, in some embodiments, the reference threshold is the change in the threshold voltage of the memory cell adjacent to the bit line in the memory cell string during the SLC erase state.

[0105] S1103: When the comparison result shows that the first change amount and the reference threshold do not satisfy the set relationship, the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change amount, so that the second change amount and the reference threshold satisfy the set relationship.

[0106] In some embodiments, adjusting the threshold voltage of the memory cell in the single-level cell (SLC) erase state to have a second change when the comparison result indicates that the first change amount and the reference threshold do not satisfy a set relationship may include:

[0107] The storage cell is erased to the SLC erase state;

[0108] The first read condition is gradually adjusted, and multiple read operations are performed on the storage cell based on the first read condition after each adjustment, until the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change amount.

[0109] It should be noted that each time the RTN amplitude of a memory cell is determined, the memory cell needs to be erased to the SLC erase state to eliminate the influence of other factors on RWM. Here, the method of erasing the memory cell to the SLC erase state is the same as that described in steps S1201 and S1401 above, and will not be repeated here.

[0110] Here, the set relationship may include the absolute value of the difference between the change in the threshold voltage of the storage cell and the reference threshold being less than or equal to a preset threshold. The preset threshold can be set according to actual conditions and may be an empirical value. For example, the preset threshold may be the product of the reference threshold and a set percentage, where a smaller set percentage results in a higher probability of correct reading. The set percentage can be set, but is not limited to, 10%.

[0111] Based on the foregoing description, the process described above means that when the comparison result shows that the first change amount and the reference threshold do not satisfy the set relationship, it is necessary to adjust the change amount of the threshold voltage of the storage cell in the SLC erasure state so that the change amount of the adjusted threshold voltage satisfies the set relationship with the reference threshold, thereby minimizing the amplitude of the RTN corresponding to the storage cell, minimizing the impact on the RWM of the storage cell, and thus improving the accuracy of reading the data stored in the storage cell.

[0112] It should be noted that another way of saying that the second change amount of the adjusted storage cell satisfies the set relationship with the reference threshold is to consider that the second change amount is approximately equal to the reference threshold. That is, when the absolute value of the difference between the second change amount and the reference threshold is less than or equal to the preset threshold, the second change amount can be considered equal to the reference threshold.

[0113] In some embodiments, the gradual adjustment of the first reading condition may include:

[0114] A set of read voltages applied to the selected word line coupled to the memory cell remains constant;

[0115] The pass voltage applied to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell is gradually increased by a set offset based on the default pass voltage.

[0116] It should be noted that, according to research, the amplitude of the RTN corresponding to the memory cell decreases as the voltage across the unselected word line in the same memory cell string increases. Therefore, when the first change amount and the reference threshold do not satisfy the set relationship, the first read condition is gradually adjusted, and the change amount of the threshold voltage of the memory cell is obtained according to the adjusted first read condition until the obtained second change amount and the reference threshold satisfy the set relationship. The method of gradually adjusting the first read condition is as follows: the read voltage applied to the selected word line remains constant, and the voltage across the unselected word line in the same memory cell string is gradually increased based on the default voltage according to a set offset. This set offset can be a default offset provided by the system.

[0117] For example, suppose a total of 3 adjustments are needed to make the threshold voltage of the memory cell in the SLC erase state reach the second change amount; set the offset to P; and the read voltage to the aforementioned V1 to V7. Based on this, the first read condition is adjusted step by step, that is: the first adjustment of the first read condition results in the read voltage to the aforementioned V1 to V7, and the pass voltage to Vpass0+P; the second adjustment of the first read condition results in the read voltage to the aforementioned V1 to V7, and the pass voltage to Vpass0+2P; the third adjustment of the first read condition results in the read voltage to the aforementioned V1 to V7, and the pass voltage to Vpass0+3P.

[0118] It should be noted that the required value of Vpass0 for unselected word lines at different positions within the same memory cell string is different. In other words, the default pass voltage Vpass0 applied to unselected word lines at different positions within the same memory cell string can be different during the application process. Correspondingly, the set offset for word lines at different positions may also be different.

[0119] For example, suppose the word lines of a memory cell string are sequentially arranged from bottom to top as: WL0, WL1, ..., WLn, ...; When reading a memory cell coupled to word line WLn, the default pass voltage Vpass0 applied to the other word lines is shown in Table 1, which are different voltage values ​​Vpass0-1, Vpass0-2, and Vpass0-3. Based on this, the default pass voltage Vpass0 applied to the unselected word lines at different locations is different. The set offset corresponding to the unselected word lines at different locations may be the same or different, depending on what the voltage generator in the memory's external circuitry can provide. For example, when they are all different, the set offset corresponding to Vpass0-1 may be 50 millivolts (mV); the set offset corresponding to Vpass0-2 may be 20 mV; and the set offset corresponding to Vpass0-3 may be 10 mV. For example, when all are the same, the set offsets corresponding to Vpass0-1, Vpass0-2, and Vpass0-3 can be any voltage increment step that the system can provide, such as 50mV, 20mV, or 10mV. The set offsets corresponding to the unselected word lines at different positions can also be partially the same and partially different, and can be in any possible combination, which will not be elaborated here.

[0120] Table 1

[0121] Word line WL The default voltage value of voltage Vpass0 WLn&above Vpass0-2 WLn+3 Vpass0-2 WLn+2 Vpass0-2 WLn+1 Vpass0-1 WLn Vread WLn-1 Vpass0-1 WLn-2 Vpass0-3 WLn-3 Vpass0-3 WLn-4&WL16 Vpass0-3 WL2-WL15 Vpass0-3 WL0-WL1 Vpass0-3

[0122] The above adjustment process involves gradually increasing the pass voltage provided to unselected memory cells belonging to the same memory cell string as the memory cell (i.e., increasing the pass voltage applied to the unselected word line coupled to the unselected memory cell), based on the default pass voltage. The amplitude of the RTN corresponding to the memory cell (i.e., the change in the threshold voltage of the memory cell in the SLC erase state) is determined after each increase in pass voltage, until, under a certain increase in pass voltage, the change in the threshold voltage of the memory cell in the SLC erase state satisfies a set relationship with the reference threshold. At this point, the change in the threshold voltage of the selected memory cell in the SLC erase state is the aforementioned second change, thus completing the adjustment of the amplitude of the RTN corresponding to the memory cell. It should be noted that after each increase in the pass voltage on the unselected word line, the memory cell is read multiple times according to the read voltage in the first read condition, or all memory cells belonging to the same word line as the memory cell are read multiple times, or all memory cells belonging to the same memory block as the memory cell are read multiple times, to obtain the second change in the threshold voltage of the memory cell in the SLC erase state.

[0123] In some embodiments, the method further includes:

[0124] When the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change, the total offset of the pass voltage applied to the unselected word line relative to the default pass voltage is recorded.

[0125] Here, the total offset is the offset of the pass voltage applied to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell when the threshold voltage change of the memory cell in the SLC erase state, obtained previously, satisfies the set relationship with the reference threshold, relative to the default pass voltage. In other words, according to the operation method provided in the embodiments of this application, the total offset of the pass voltage relative to the default pass voltage that minimizes the amplitude of the RTN corresponding to the memory cell can be obtained. During subsequent read operations, this total offset is added to the default pass voltage to obtain the pass voltage provided to the memory cell, under which read interference is minimized.

[0126] In some embodiments, when the comparison result shows that the first change and the reference threshold satisfy the set relationship, feedback indication information is provided or a second preset time is waited to end the adjustment of the threshold voltage of the storage cell in the SLC erase state.

[0127] It should be noted that the second preset time can be customized manually and is not restricted in this application.

[0128] To understand the amplitude adjustment process of the RTN described above, please refer to... Figure 18 As shown. The specific adjustment method of the RTN amplitude of the storage unit includes:

[0129] S1801: Based on the first read condition, determine the change in threshold voltage of the memory cell adjacent to the bit line that belongs to the same memory cell string as the memory cell when it is in the SLC erase state, and obtain a reference threshold.

[0130] S1802: Determine the first change in the threshold voltage of the memory cell in the memory during the SLC erase state based on the first read condition;

[0131] S1803: Compare the first change with the reference threshold;

[0132] S1804: When the comparison result shows that the first change and the reference threshold satisfy the set relationship, feedback indication information or wait for a second preset time to end the adjustment of the threshold voltage of the storage cell in the SLC erase state and end the process.

[0133] S1805: When the comparison result shows that the first change amount and the reference threshold do not satisfy the set relationship, the storage cell is erased to the SLC erase state; the first read condition is gradually adjusted, and multiple read operations are performed on the storage cell based on the first read condition after each adjustment, until the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change amount, and the second change amount and the reference threshold satisfy the set relationship, and the process ends.

[0134] It should be noted that in step S1805, the first read condition is gradually adjusted, and steps 1802 to 1803 are re-executed until the second change amount of the storage cell and the reference threshold satisfy the set relationship, at which point the process ends. The process ending here refers to the process ending when the RTN of a specific storage cell in the storage cell string is adjusted. The adjustment of the RTN amplitude of any storage cell in the same storage cell string can be performed according to steps 1801 to S1805.

[0135] It should be noted that the reference threshold, the first change, and the second change in this process have been explained in detail above and will not be repeated here.

[0136] In practical applications, the magnitude of the RTN corresponding to the storage unit increases with the number of erase / programmable cycles of the memory. Therefore, the adjustment of the RTN magnitude of the storage unit needs to be performed multiple times within the erase / programmable lifespan of the storage unit to reduce interference from subsequent reads.

[0137] Therefore, in some embodiments, the method may further include:

[0138] Determine the number of programming / erasing operations that have been performed on the storage block containing the storage unit;

[0139] Determine whether the number of programming / erasing operations has reached the preset number;

[0140] When the number of programming / erasing operations reaches the preset number, the third change in the threshold voltage of the storage unit in the SLC erasure state is redefined; and when the third change does not satisfy the set relationship with the reference threshold, the change in the threshold voltage of the storage unit in the SLC erasure state is adjusted so that the change satisfies the set relationship with the reference threshold.

[0141] It should be noted that this describes adjusting the amplitude of the RTN of the memory cell described above when the number of programming / erasing operations reaches a preset number, so as to obtain the total offset of the voltage provided to the unselected memory cell during subsequent read operations, thereby reducing read interference caused by RTN.

[0142] In some embodiments, the preset number of times is determined based on the maximum number of programming / erasing cycles of the storage cell and a set evaluation period; wherein the set evaluation period is used to reflect the time interval between two consecutive adjustments to the threshold voltage of the storage cell in the SLC erase state.

[0143] It should be noted that the maximum number of programming / erasing cycles refers to the maximum number of programming / erasing operations that can be performed within the erase / programming lifetime of the memory cell. The set evaluation period is a manually designed time interval used to reflect the change in the threshold voltage of the memory cell during two consecutive adjustments in the SLC erase state. In other words, it specifies how many programming / erasing cycles are required to adjust the RTN amplitude of the memory cell within the maximum number of programming / erasing cycles. Determining the preset number may include: first, dividing the maximum number of programming / erasing cycles by the set evaluation period to obtain the number of times the RTN needs to be adjusted within the maximum number of programming / erasing cycles; then, multiplying all integers from 0 to the number of times the RTN needs to be adjusted by the set evaluation period sequentially to obtain the preset number.

[0144] For example, assuming the maximum number of programming / erasing cycles is 1000 and the evaluation cycle is set to 100, then the number of times the RTN needs to be adjusted is 10. In this case, the preset number of cycles is 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000.

[0145] The specific process for determining when to adjust the RTN amplitude corresponding to the storage unit can be as follows: Figure 19 As shown, the process includes:

[0146] S1901: Determine the maximum number of programming / erasing cycles for the memory cell as M;

[0147] S1902: Determine the current number of programming / erasing operations on the memory cell as Z;

[0148] S1903: Determine whether the number of programming / erasing cycles has reached the preset number;

[0149] It should be noted that, in S1903, the determination of whether the number of programming / erasing operations has reached the preset number can be made using the following formula: whether Z is equal to n*M / N, where N is the quotient of the maximum number of programming / erasing operations M and the set evaluation period, for example, N=10; and n is any integer from 0 to 10.

[0150] S1904: When the number of programming / erasing operations reaches a preset number, the third change in the threshold voltage of the storage unit in the SLC erasure state is re-determined; and when the third change does not satisfy the set relationship with the reference threshold, the change in the threshold voltage of the storage unit in the SLC erasure state is adjusted so that the change and the reference threshold satisfy the set relationship.

[0151] S1905: If the number of programming / erasing cycles has not reached the preset number, the change in the threshold voltage of the storage cell in the SLC erasure state will not be adjusted, and the process will end.

[0152] In some embodiments, the method further includes: when the current programming / erase count is zero, directly determining a third change in the threshold voltage of the memory cell in the SLC erase state based on a first read condition.

[0153] In some embodiments, the method may further include:

[0154] When the current programming / erase count is not zero and the preset count is reached, the total recorded offset is obtained; the total offset is the offset of the through voltage applied to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell when the threshold voltage change of the memory cell in the SLC erase state obtained previously satisfies the set relationship with the reference threshold, relative to the default through voltage.

[0155] The second reading condition is obtained based on the total offset and the first reading condition;

[0156] Based on the second read condition, a third change in the threshold voltage of the storage cell during the SLC erase state is determined.

[0157] It should be noted that this description refers to the first adjustment of the RTN corresponding to the memory cell when the preset number of attempts is 0, and the total voltage offset has not been recorded previously. Therefore, the first read condition is the condition for obtaining the third change in the threshold voltage of the memory cell in the SLC erase state. When the preset number of attempts is not 0, the total offset has already been recorded; therefore, the second read condition is the condition for obtaining the third change in the threshold voltage of the memory cell in the SLC erase state. This second read condition is determined by the recorded total offset and the first read condition; that is, the default voltage in the first read condition plus the total offset.

[0158] Based on the aforementioned operating methods, such as Figure 20 As shown in the embodiments of this application, a reading method is also provided, which may include:

[0159] S2001: When performing a read operation on a memory cell of the memory, a read voltage is provided for the selected word line coupled to the memory cell;

[0160] S2002: Provide a pass voltage to unselected word lines coupled to other memory cells in the same memory cell string as the memory cell; wherein the pass voltage is determined based on the total offset of the records and the default pass voltage.

[0161] It should be noted that the above description refers to the voltage required for unselected memory cells within the same memory cell string during a read operation. The specific method for obtaining this voltage has already been clearly described and will not be repeated here.

[0162] The memory operation method provided in this application compares the RTN of a memory cell with a reference threshold. If the comparison result does not satisfy a set relationship, the comparison result is adjusted to satisfy the set relationship, thereby reducing read interference caused by the RTN. In simpler terms, the operation method provided in this application adjusts the amplitude of the RTN of the memory cell (the change in threshold voltage during the SLC erase state of the memory cell characterizes the amplitude of the RTN) to a known minimum amplitude (a reference threshold, for example, this minimum amplitude could be the amplitude of the RTN corresponding to a memory cell adjacent to a bit line), so as to reduce read interference caused by the RTN and facilitate the correct reading of data stored in the memory cell.

[0163] To understand the operation and reading methods provided in the embodiments of this application, the following description uses a 3DCTF containing 64 word lines as an example. See details below. Figures 21 to 23 As shown.

[0164] Figure 21 This illustration shows a flowchart of a CTF (Content Transfer Function) with 64 word lines provided in this application, which uses RTN to obtain the total offset of the through voltage of the unstored cell corresponding to each word line relative to the default through voltage. Specifically, in step S2101, the memory cell coupled to word line WL63 is placed in SLC erase state, and a certain memory block of 3D CTF is continuously read multiple times based on the first read condition; wherein, the first read condition includes: the pass voltage Vusel provided to the unselected word line in the same memory cell string is the default pass voltage Vpass0, and the read voltage Vsel provided to the selected word line in the same memory cell string is Vread; in step S2102, the change in threshold voltage of the memory cell coupled to word line WL63 in SLC erase state is calculated to obtain a reference threshold; specifically, this includes: placing the memory cell coupled to word line WL63 in SLC erase state; selecting the memory cell coupled to word line WL63 as the selected memory cell, and the rest as unselected memory cells; after reading multiple times according to the above first read condition, the distribution of the change in threshold voltage of the memory cell coupled to word line WL63 is obtained; based on this distribution of change, 3σ corresponding to the distribution of the change in threshold voltage of the memory cell coupled to word line WL63 is obtained, denoted as σ. 63 , the σ 63 As a reference threshold; in step S2103, 3σ corresponding to the distribution of the change in threshold voltage of the memory cells coupled to word lines WL0 to WL62 in the SLC erase state is obtained respectively, and denoted as σ0~σ 62 Each of these can be referred to as the first change. The specific calculation process is described in step S2102 and will not be repeated here. In step S2104, the 3σ corresponding to word lines WL0 to WL62 is respectively compared with the reference threshold σ. 63 Comparison, if the σ corresponding to a certain word-line coupled memory cell is... i Equal to the reference threshold σ 63 (σ 63 Approximately equal to σ i If the two conditions described above satisfy the set relationship, then the amplitude of the RTN corresponding to the memory cell coupled to the word line does not need to be adjusted. At this time, when the memory cell coupled to the word line is not selected, the voltage supplied to other unselected memory cells can be the default voltage Vpass0. If the σ of a memory cell coupled to a certain word line... i Greater than the reference threshold σ 63 Then the amplitude of the RTN corresponding to the memory cell coupled to that word line needs to be adjusted by increasing the through voltage of other unselected word lines until it reaches σ. i Equal to σ63(σ63 Approximately equal to σ i That is, until the two conditions described above are met (i.e., the established relationship is satisfied). It should be noted that the adjustment may not be completed in one step and may require multiple steps to achieve σ. i It equals σ63. Here, the RTN adjustment is achieved through steps S2105 and S2106. Step S2105 determines whether the voltage has increased to its maximum value (the voltage cannot be increased indefinitely, as this may introduce other read interference problems); in step S2106, the new read conditions are obtained, where ΔV is the set offset by which the voltage is increased each time the RTN is adjusted. In step S2107, σ... i After equaling σ63, the total offset of the pass voltage applied to the word line relative to the default pass voltage is obtained by the formula ΔVpass(i)=Vpass(i)-Vpass; in step S2108, ΔVpass(i) is sent to the microcontroller of the memory controller or control logic unit for storage, for use in subsequent read operations.

[0165] It should be noted that Vusel represents the pass voltage applied to the unselected word line; Vsel represents the read voltage applied to the selected word line. The evaluation of the RTN corresponding to the memory cell in steps S2102 and S2103 is performed as described above and will not be repeated here.

[0166] Figure 22 This illustration shows a flowchart of an embodiment of the present application for determining whether RTN adjustment is needed based on the current programming / erasing count. Figure 22 As shown, in step S2201, the maximum number of programming / erasing cycles for the memory is determined, denoted as M; in step S2202, programming / erasing is performed on a certain memory block; in step S2203, the current number of programming / erasing cycles for the memory block is determined, denoted as Z; in step S2204, a conditional statement `if Z = n*M / N?` is used to determine whether the preset number of cycles has been reached; if the preset number of cycles has been reached, step S2205 is executed. Figure 21 The adjustment process is as follows; if the preset number of times is not reached, the process ends.

[0167] When the current programming / erasing count reaches the preset count, there are two scenarios for adjusting the RTN, such as... Figure 23 As shown.

[0168] In step S2301, it is determined whether the current programming / erasing count is zero. If it is zero, step S2302 is executed, and the program is directly used... Figure 21The process shown adjusts the amplitude of the RTN corresponding to the memory cell coupled to each word line to obtain the total offset of the voltage across other unselected word lines relative to the default voltage when each word line is selected, for subsequent reading. If the offset is not zero, step S2303 is executed to obtain the total offset of each word line corresponding to the previous RTN adjustment. After obtaining the recorded total offset ΔVpass(i), step S2304 is executed to obtain the new reading conditions. Then, step S2305 is executed to perform the reading according to the new reading conditions. Figure 21 The process shown adjusts the amplitude of the RTN corresponding to the memory cell coupled to each word line to obtain a new total offset of the through voltage relative to the default through voltage when each word line is an unselected word line, for use in subsequent read operations.

[0169] The operation method provided in this application essentially adjusts the amplitude of the RTN of the memory cell to obtain the pass voltage provided for unselected word lines during subsequent read operations. This reduces read interference caused by the corresponding RTN when performing read operations on the memory cell. This method can improve the amplitude of the RTN of memory cells at different locations, thereby effectively mitigating the impact of word line position differences on RWM consistency. This results in advantages such as effectively improving the RTN consistency of memory cells with word lines coupled on the same memory cell string; effectively reducing the impact of word line position on RTN and read window margin; compensating for RTN amplitude calibration based on memory usage; and requiring no additional process improvements.

[0170] This application embodiment also provides a memory, including: a memory array for storing data; and peripheral circuitry coupled to the memory array and used for controlling the memory array; wherein the peripheral circuitry is configured to implement the operation method described in any of the preceding claims.

[0171] In some embodiments, the peripheral circuitry includes a register for storing the total offset of the record.

[0172] It should be noted that this memory belongs to the same inventive concept as the aforementioned method for erasing memory. The terms used in this memory description have been explained in detail in the aforementioned programming method and are equally applicable here, and will not be repeated. It should be understood that only the structure of the memory most relevant to the technology of this application is described here; other structures can be as described above. Figures 1 to 6 The structure shown can also be the structure of other memory.

[0173] Based on the same inventive concept, this application also provides a storage system, which includes one or more of the aforementioned memories;

[0174] and a memory controller coupled to the memory; the memory controller is used to send various operation commands to the memory. These various operation commands include, for example, read, program, and erase commands.

[0175] In some embodiments, the storage system is a solid-state drive (SSD) or a memory card.

[0176] It should be noted that this storage system includes the aforementioned memory; therefore, the two share the same technical features. All terms appearing in this storage system have been explained in detail in the aforementioned memory, and are equally applicable here, without further repetition. It should be understood that only the structure of the storage system most relevant to the technology of this application is described here; other structures can be as described above. Figures 1 to 6 The structure shown can also be the structure of other storage systems.

[0177] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application.

Claims

1. A method of operating a memory, the method comprising: include: Determine the first change in the threshold voltage of the memory cell in the memory during the single-level cell (SLC) erase state; Compare the first change with the reference threshold; When the comparison result shows that the first change amount and the reference threshold do not satisfy the set relationship, the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change amount, so that the second change amount and the reference threshold satisfy the set relationship.

2. The method of claim 1, wherein, Determining the first change in the threshold voltage of a memory cell in the memory during a single-level cell (SLC) erase state includes: An erase operation is performed on the storage block containing the storage unit, so that all the storage units contained in the storage block are erased to the SLC erase state; Perform multiple read operations on the storage unit based on the first read condition; Obtain the threshold voltage value of the memory cell read each time; The first change is determined based on each of the voltage values.

3. The operating method according to claim 1, characterized in that, Determining the first change in the threshold voltage of a memory cell in the memory during a single-level cell (SLC) erase state includes: An erase operation is performed on the storage block containing the storage unit, so that all the storage units contained in the storage block are erased to the SLC erase state; Based on the first read condition, multiple read operations are performed on each memory cell coupled to the selected word line to obtain the distribution of the threshold voltage change of each memory cell; the selected word line is the word line in the memory block coupled to the memory cell; Determine the distribution of the change in 3 This is the first change.

4. The operating method according to claim 2, characterized in that, The first reading conditions include: A set of read voltages is applied to the selected word line coupled to the memory cell; Apply a default pass voltage to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell; The set of read voltages includes a set of voltage values ​​between the minimum and maximum voltage values ​​of the threshold voltage distribution corresponding to the SLC erase state.

5. The operating method according to claim 2, characterized in that, Determining the first change based on each voltage value includes: The average voltage value of the threshold voltage of the memory cell is obtained based on each of the voltage values; The first change is determined based on any one of the voltage values ​​and the average voltage value.

6. The operating method according to claim 2 or 3, characterized in that, The method further includes: waiting for a first preset time after performing an erase operation on the storage block.

7. The operating method according to claim 1, characterized in that, The reference threshold is the change in threshold voltage of the memory cell adjacent to the bit line in the memory cell string during the SLC erase state.

8. The operating method according to claim 1, characterized in that, When the comparison result indicates that the first change amount and the reference threshold do not satisfy a set relationship, adjusting the threshold voltage of the memory cell in the single-layer cell SLC erase state to have a second change amount includes: The storage cell is erased to the SLC erase state; The first read condition is gradually adjusted, and multiple read operations are performed on the storage cell based on the first read condition after each adjustment, until the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change amount.

9. The operating method according to claim 8, characterized in that, The gradual adjustment of the first reading condition includes: A set of read voltages applied to the selected word line coupled to the memory cell remains constant; The pass voltage applied to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell is gradually increased by a set offset based on the default pass voltage.

10. The operating method according to claim 9, characterized in that, The method further includes: When the threshold voltage of the storage cell in the SLC erase state is adjusted to have a second change, the total offset of the pass voltage applied to the unselected word line relative to the default pass voltage is recorded.

11. The operating method according to claim 1, characterized in that, The set relationship includes the absolute value of the difference between the change in the threshold voltage of the storage cell and the reference threshold being less than or equal to a preset threshold.

12. The operating method according to claim 1, characterized in that, The method further includes: Determine the number of programming / erasing operations that have been performed on the storage block containing the storage unit; Determine whether the number of programming / erasing operations has reached the preset number; When the number of programming / erasing operations reaches the preset number, the third change in the threshold voltage of the storage unit in the SLC erasure state is redefined; and when the third change does not satisfy the set relationship with the reference threshold, the change in the threshold voltage of the storage unit in the SLC erasure state is adjusted so that the change satisfies the set relationship with the reference threshold.

13. The operating method according to claim 12, characterized in that, The preset number of times is determined based on the maximum number of programming / erasing times of the storage cell and a set evaluation period; wherein, the set evaluation period is used to reflect the time interval between two consecutive adjustments of the threshold voltage of the storage cell in the SLC erase state.

14. The operating method according to claim 12, characterized in that, The method further includes: When the current number of programming / erasing cycles is zero, the third change in the threshold voltage of the memory cell in the SLC erasure state is directly determined based on the first read condition.

15. The operating method according to claim 12, characterized in that, The method further includes: When the current programming / erase count is not zero and the preset count is reached, the total recorded offset is obtained; the total offset is the offset of the through voltage applied to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell when the threshold voltage change of the memory cell in the SLC erase state obtained previously satisfies the set relationship with the reference threshold, relative to the default through voltage. The second reading condition is obtained based on the total offset and the first reading condition; Based on the second read condition, a third change in the threshold voltage of the storage cell during the SLC erase state is determined.

16. The operating method according to claim 1, characterized in that, The change in the threshold voltage of the storage cell during the single-level cell (SLC) erase state is used to measure the amplitude of the random telegraph noise (RTN) corresponding to the storage cell.

17. The operating method according to claim 1, characterized in that, The method further includes: When the comparison result shows that the first change and the reference threshold satisfy the set relationship, feedback indication information is provided or a second preset time is waited to end the adjustment of the threshold voltage of the storage cell in the SLC erase state.

18. A method for reading a memory, characterized in that, include: When performing a read operation on a memory cell, a read voltage is provided to the selected word line coupled to the memory cell; Provide a pass voltage to the unselected word line that is coupled to other memory cells in the same memory cell string as the memory cell; The voltage applied is determined based on the total recorded offset and the default voltage applied. The total offset is the offset of the voltage applied to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell when the threshold voltage of the memory cell in the single-level cell SLC erase state obtained previously satisfies the set relationship with the reference threshold.

19. A memory, characterized in that, include: Storage arrays used for storing data; And peripheral circuitry coupled to the memory array and used to control the memory array; wherein the peripheral circuitry is configured to implement the operating method according to any one of claims 1 to 17.

20. The memory according to claim 19, characterized in that, The peripheral circuit includes: a register for storing the total offset of the record; the total offset is the offset of the pass voltage applied to the unselected word line coupled to other memory cells in the same memory cell string as the memory cell when the change in the threshold voltage of the memory cell in the SLC erase state obtained previously satisfies the set relationship with the reference threshold, relative to the default pass voltage.

21. A storage system, characterized in that, include: One or more memories according to any one of claims 19 to 20; and the memory controller coupled to the memory; The memory controller is used to send various operation commands to the memory.

22. The storage system according to claim 21, characterized in that, The storage system is a solid-state drive (SSD) or a memory card.

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