Display device and electronic terminal

Abstract

The present application provides a display device and an electronic terminal, wherein a light emitting unit in a display panel comprises a light emitting element, a data writing unit for writing a data signal in a first stage, a driving unit connected to the light emitting element and the data writing unit, and a conduction control unit connected between the light emitting element and a first voltage line, the driving unit is used to generate a driving current according to the data signal to drive the light emitting element to emit light in the first stage, and the light emitting element is driven to emit light without the driving current in a second stage, the first voltage line is used to transmit a first sub-voltage signal and a second sub-voltage signal respectively in the first stage and the second stage, so that the first voltage line and the light emitting element are electrically disconnected and connected respectively, and the first voltage line is used to detect whether the light emitting element emits light in the second stage, so as to determine whether a lighting problem is caused by the light emitting element.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to the manufacture of display devices, specifically to display apparatus and electronic terminals. Background Technology

[0002] In the fabrication process of silicon-based microdisplay devices, the manufacturing process of the light-emitting device can easily lead to display defects. Therefore, after the fabrication is completed, a lighting test is required to confirm whether there are any defects.

[0003] However, existing lighting tests, which involve driving light-emitting devices with pixel driving circuits, require complex driving signals to be added to the pixel driving circuits, resulting in high costs for the test fixtures and making it difficult to determine whether the lighting problem is caused by the pixel driving circuit or the light-emitting device. Summary of the Invention

[0004] The present invention provides a display device and an electronic terminal to improve the problem of difficulty in determining whether a lighting problem is caused by a light-emitting element.

[0005] This invention provides a display device, including a display panel and a driver for driving the display panel to display an image. The display panel includes a plurality of light-emitting units, each light-emitting unit comprising:

[0006] Light-emitting elements;

[0007] A data writing unit is used to write data signals in the first stage.

[0008] A driving unit, connected to the light-emitting element and the data writing unit, is used to generate a driving current according to the data signal in the first stage to drive the light-emitting element to emit light, and in the second stage, which is different from the first stage, no driving current is used to drive the light-emitting element to emit light.

[0009] A conduction control unit is connected between the light-emitting element and the first voltage line;

[0010] The first voltage line is used to transmit a first sub-voltage signal in the first stage to control the conduction control unit to turn off, so that the first voltage line and the light-emitting element are electrically disconnected. The first voltage line is also used to transmit a second sub-voltage signal in the second stage to control the conduction control unit to turn on, so that the first voltage line and the light-emitting element are electrically connected, for detecting whether the light-emitting element emits light.

[0011] In some embodiments, the conduction control unit includes a PN junction, wherein the N-region of the PN junction is electrically connected to the anode of the light-emitting element, and the P-region of the PN junction is electrically connected to the first voltage line;

[0012] The cathode of the light-emitting element is electrically connected to the second voltage line, and the amplitude of the second voltage signal transmitted by the second voltage line is smaller than the amplitude of the second sub-voltage signal.

[0013] In some embodiments, the light-emitting unit includes at least one N-type metal-oxide-semiconductor and at least one P-type metal-oxide-semiconductor. The P-well of the N-type metal-oxide-semiconductor is provided with a corresponding P-type substrate and two N-doped regions spaced apart. The N-well of the P-type metal-oxide-semiconductor is provided with a corresponding N-type substrate and two P-doped regions spaced apart.

[0014] The P-type metal-oxide-semiconductor is disposed within the P-well of the N-type metal-oxide-semiconductor, or the P-type metal-oxide-semiconductor is disposed within the N-well of the P-type metal-oxide-semiconductor.

[0015] In some embodiments, the light-emitting unit further includes:

[0016] A switching unit is connected between the driving unit and the light-emitting element. In the second stage, the switching unit is used to control the driving unit and the light-emitting element to be electrically disconnected. In the first stage, the switching unit is used to control the driving unit and the light-emitting element to be electrically connected.

[0017] In some embodiments, the switching unit includes one of the N-type metal-oxide-semiconductor and the P-type metal-oxide-semiconductor, and the data writing unit includes at least the other of the N-type metal-oxide-semiconductor and the P-type metal-oxide-semiconductor;

[0018] Wherein, the P-type substrate in the P-well of the N-type metal-oxide-semiconductor is electrically connected to the third voltage line for transmitting the third voltage signal, and the N-type substrate in the N-well of the P-type metal-oxide-semiconductor is electrically connected to the fourth voltage line for transmitting the fourth voltage signal, wherein the amplitude of the third voltage signal is smaller than the amplitude of the fourth voltage signal.

[0019] Wherein, the P-region of the PN junction is a P-type substrate within the P-well of the N-type metal-oxide-semiconductor, and the N-region of the PN junction is located within the N-well of the P-type metal-oxide-semiconductor, or the N-region of the PN junction is located within the P-well of the N-type metal-oxide-semiconductor.

[0020] In some embodiments, the display panel includes a first insulating layer on the P-well of the N-type metal-oxide-semiconductor and the N-well of the P-type metal-oxide-semiconductor, a third voltage line and a fourth voltage line on the first insulating layer, and the N-region of the PN junction is electrically connected to the light-emitting element through a first via penetrating the first insulating layer.

[0021] In some embodiments, the switching transistor in the switching unit is a P-type metal-oxide-semiconductor, the active layer of the switching transistor includes a corresponding N-well and two P-doped regions spaced apart within the N-well, the gate of the switching transistor is located on the corresponding N-well, the source of the switching transistor is electrically connected to one of the P-doped regions through a third via, and the drain of the switching transistor is electrically connected to the other P-doped region through a fourth via.

[0022] In some embodiments, the data writing transistor in the data writing unit is an N-type metal-oxide-semiconductor, the active layer of the data writing transistor includes a corresponding P-well and two N-doped regions spaced apart within the P-well, the gate of the data writing transistor is located on the corresponding P-well, the source of the data writing transistor is electrically connected to one of the N-doped regions through a fifth via, and the drain of the data writing transistor is electrically connected to the other N-doped region through a sixth via.

[0023] In some embodiments, the light-emitting unit further includes:

[0024] A mirror current unit is electrically connected to the drive unit and is used to transmit mirror current to the drive unit;

[0025] The driving unit is used to generate the driving current based on the data signal and the mirror current.

[0026] Embodiments of the present invention also provide an electronic terminal, including any of the display devices described above.

[0027] This invention provides a display device and an electronic terminal. Based on a data writing unit writing data signals in a first stage, a driving unit connected to the light-emitting element and the data writing unit generates a driving current according to the data signal in the first stage to drive the light-emitting element to emit light. In a second stage, no driving current drives the light-emitting element to emit light. A conduction control unit connected between the light-emitting element and a first voltage line is provided. By setting the first voltage line to transmit a first sub-voltage signal and a second sub-voltage signal in the first and second stages respectively to control the conduction control unit to be cut off and turned on respectively, the first voltage line and the light-emitting element are electrically disconnected and electrically connected respectively. This is used in the second stage to detect whether the light-emitting element emits light, thereby determining whether the lighting problem is caused by the light-emitting element. Attached Figure Description

[0028] Figure 1 This is an architectural diagram of a display device provided in an embodiment of the present invention.

[0029] Figure 2 The circuit diagram of the light-emitting unit provided in the embodiment of the present invention.

[0030] Figure 3 The waveform diagram is shown for some signals or nodes in the light-emitting unit provided in the embodiment of the present invention.

[0031] Figure 4 and Figure 5 The figures shown are cross-sectional views of a display panel provided in an embodiment of the present invention and current diagrams in two different cases.

[0032] Figure 6 and Figure 7 The figures show cross-sectional views of another display panel provided in the embodiments of the present invention and current diagrams in two different cases. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0034] The terms "comprising" and "having," and any variations thereof, used in this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the steps or modules listed, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to such process, method, product, or apparatus.

[0035] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] The present invention provides a display device, which may include, but is not limited to, the following embodiments and combinations thereof.

[0037] In some embodiments, combined with Figure 1 and Figure 2 As shown, the display device 100 includes a display panel 10 and a driver 20 for driving the display panel 10 to display an image. The display panel 10 includes a plurality of light-emitting units 30. Each light-emitting unit 30 includes a light-emitting element 301, a data writing unit 302, a driving unit 303, and a conduction control unit 304. The data writing unit 302 is used to write a data signal Data in a first stage. The driving unit 303 is connected to the light-emitting element 301 and the data writing unit 302, and is used to generate a driving current based on the data signal Data in the first stage to drive the light-emitting element 301 to emit light. In a second stage different from the first stage, no driving current drives the light-emitting element 301 to emit light. The conduction control unit 304 is connected between the light-emitting element 301 and a first voltage line L1. The first voltage line L1 is used to transmit a first sub-voltage signal VSS1 in the first stage to control the conduction control unit 304 to be turned off, so that the first voltage line L1 and the light-emitting element 301 are electrically disconnected. The first voltage line L1 is also used to transmit a second sub-voltage signal VSS2 in the second stage to control the conduction control unit 304 to be turned on, so that the first voltage line and the light-emitting element 301 are electrically connected, for detecting whether the light-emitting element 301 emits light.

[0038] The display panel 10 can be a self-emissive display panel, controlling the light emission of multiple light-emitting elements 301 in the multiple light-emitting units 30 through a data signal Data, thereby presenting a complete display image. The light-emitting elements 301 can be OLED (Organic Light-Emitting Diode), LED (Light-Emitting Diode), or micro-LED. Figure 2 and Figure 3The display panel 10 shown may include multiple positive data lines electrically connected to the driver 20. Each positive data line may be electrically connected to a corresponding plurality of light-emitting units 30. The data signal Data may include multiple sub-data signals (e.g., data1, data2, data3 up to datan) corresponding to the plurality of light-emitting units 30 (e.g., n, where n is a positive integer).

[0039] In this embodiment, the first stage can be understood as the display stage after leaving the factory, that is, the display panel 10 displays the screen under the control of multiple data signals Data transmitted by multiple positive phase data lines. The second stage can be understood as the testing stage before leaving the factory, that is, the display panel 10 no longer receives multiple data signals Data, but judges whether the light-emitting element 301 is normal based on whether the light-emitting element 301 emits light after the second sub-voltage signal VSS2 transmitted by the conduction control unit 304 acts on it, so as to ensure that the screen can be displayed normally in the corresponding first stage after testing and improvement.

[0040] Understandably, in this embodiment, the driving unit 303 generates a driving current based on the data signal Data (corresponding sub-data signal) in the first stage to drive the light-emitting element 301 to emit light and achieve normal screen display function. At this time, the first voltage line L1 transmits the first sub-voltage signal VSS1 to control the conduction control unit 304 to be turned off. The signal transmitted by the first voltage line L1 affects the light emission of the light-emitting element 301. At the same time, the first voltage line L1 is also used to transmit the second sub-voltage signal VSS2 in the second stage to control the conduction control unit 304 to be turned on, so that the second sub-voltage signal VSS2 is transmitted to the light-emitting element 301. At this time, it can be considered that the driving unit 303 does not generate a driving current or makes the driving current not transmitted to the light-emitting element 301 to affect its detection. At this time, it can be considered that if the light-emitting element 301 is normal, it is normal; otherwise, it is abnormal.

[0041] In some embodiments, such as Figure 2 As shown, the conduction control unit 304 includes a PN junction D0, the N region of which is electrically connected to the anode of the light-emitting element 301, and the P region of which is electrically connected to the first voltage line L1; wherein, the cathode of the light-emitting element 301 is electrically connected to the second voltage line L2, and the amplitude of the second voltage signal AVEE transmitted by the second voltage line L2 is less than the amplitude of the second sub-voltage signal VSS2.

[0042] In this process, the internal electric field of PN junction D0 points from the N region to the P region. To make PN junction D0 conduct and form a current, a larger electric field with the opposite direction to the internal electric field needs to be applied. As discussed above, in the second stage (i.e., the detection stage), the amplitude of the second sub-voltage signal VSS2 transmitted by the first voltage line L1 electrically connected to the P region is greater than the amplitude of the second voltage signal AVEE transmitted by the second voltage line L2 connected to the N region. It is assumed that the voltage difference between the second sub-voltage signal VSS2 and the second voltage signal AVEE is sufficient to make both the light-emitting element 301 (if it is normal) and PN junction D0 conduct. In this case, if the light-emitting element 301 emits light, it is considered normal; otherwise, it is considered abnormal.

[0043] In some embodiments, such as Figure 2 As shown, the light-emitting unit 30 further includes a switching unit 305 connected between the driving unit 303 and the light-emitting element 301. In the second stage, the switching unit 305 controls the driving unit 303 and the light-emitting element 301 to be electrically disconnected. In the first stage, the switching unit 305 controls the driving unit 303 and the light-emitting element 301 to be electrically connected. As discussed above, in this embodiment, by setting a switching unit 305 between the driving unit 303 and the light-emitting element 301, the two are electrically connected in the first stage to allow the driving current to be transmitted to the light-emitting element 301 to achieve normal light emission and thus present the entire image. In the second stage, the connection is electrically disconnected to detect whether the light-emitting element 301 is functioning properly.

[0044] In some embodiments, such as Figure 2 As shown, the light-emitting unit 30 further includes a mirror current unit 306 electrically connected to the driving unit 303, the mirror current unit 306 being used to transmit mirror current to the driving unit 303; wherein, the driving unit 303 is used to generate the driving current according to the data signal Data and the mirror current.

[0045] Furthermore, the driving unit 303 may include a seventh transistor M2, the switching unit 305 may include an eighth transistor M3, and the light-emitting unit 30 may also include a ninth transistor M1 electrically connected to the current mirror unit 306 and the seventh transistor M2 (its drain can be loaded with a third power supply signal VDD). The connection relationship between the seventh transistor M2, the eighth transistor M3, the ninth transistor M1, and the current mirror unit 306 can be referenced. Figure 2 .

[0046] For example Figure 2The diagram illustrates the first row of light-emitting units 30. The gate of the seventh transistor M2 is electrically connected to the data writing unit 302. The gate of the ninth transistor M1 is electrically connected to the current mirroring unit 306. The gate of the eighth transistor M3 is loaded with the first row of switching signals PWM. The source of the eighth transistor M3 is electrically connected to the control unit 304 through the first node A. The drain of the eighth transistor M3 is electrically connected to the source of the seventh transistor M2 through the second node B. The drain of the seventh transistor M2 is electrically connected to the source of the ninth transistor M1. The drain of the ninth transistor M1 is loaded with the third power supply signal VDD.

[0047] Specifically, such as Figure 2 As shown, the data writing unit 302 includes a first transistor T2 belonging to the first sub-data writing unit 3021, a second transistor T2' belonging to the second sub-data writing unit 3022, and a third transistor T4, a fourth transistor T5, a fifth transistor T6, and a sixth transistor T7 belonging to the stabilization module 309. The gates of the first transistor T2 and the second transistor T2' are electrically connected to the gate line for transmitting the gate signal WL. The source of the first transistor T2 is electrically connected to the positive data line for transmitting the data signal Data, and the source of the second transistor T2' is electrically connected to... For the inverting data line used to transmit the inverted data signal Data', the drain of the first transistor T2 is electrically connected to the gate of the third transistor T4 and the gate of the fifth transistor T6; the drain of the second transistor T2' is electrically connected to the gate of the fourth transistor T5 and the gate of the sixth transistor T7; the source of the third transistor T4 and the source of the fourth transistor T5 are both electrically connected to the high-voltage line used to transmit the first power supply signal VGH; and the source of the fifth transistor T6 and the source of the sixth transistor T7 are both electrically connected to the low-voltage line used to transmit the second power supply signal VGL. Other connections can be referenced. Figure 2 As shown.

[0048] Combination Figure 2 and Figure 3As shown, for multiple light-emitting units 30 connected to the same set of positive and negative data lines, in the first stage, at the first time t1, the gate signal WL of the first row changes from its low potential to its high potential, so that the first transistor T2 and the second transistor T2' are both turned on; at the second time t2, the data signal Data is data1 corresponding to the first row of light-emitting units 30 (for example, one of high potential and low potential, the former is taken as an example here), and the negative data signal Data' is the negative signal corresponding to data1 (for example, the other of high potential and low potential, the latter is taken as an example here), thereby controlling the fifth transistor T6 to turn on, the third transistor T4 to turn off, the fourth transistor T5 to turn on, and the sixth transistor T7 to turn off. Therefore, the first power supply signal VGH is transmitted to the gate of the fifth transistor T6 so that the fifth transistor T6 is further turned on, so as to transmit the second power supply signal VGL to the seventh transistor. The gate of M2 is turned on to conduct the seventh transistor M2, and at this time, the mirror current unit 306 can control the magnitude of the current generated by the ninth transistor M1 (i.e., the aforementioned driving current) by controlling the amplitude of its output fourth power supply signal V_bias. At the third time t3, the gate signal WL changes from its high potential to its low potential. At the fourth time t4, the data2 corresponding to the second row of light-emitting units 30 (e.g., one of high potential or low potential) and its inverted signal are written. At the fifth time t5, the switching signal PWM of the first row changes from its high potential to its low potential to turn on the eighth transistor M3, and the aforementioned driving current flows through the light-emitting element 301 to make it emit light normally. At the sixth time t6, the switching signal PWM of the first row changes from its low potential to its high potential to turn off the eighth transistor M3, and the light-emitting element 301 does not emit light until a new sub-data signal is written to the row in the next frame to emit light.

[0049] It should be noted that if the above data1 is at a low potential (that is, its inverted signal is at a high potential), the seventh transistor M2 will be turned off by the stabilization module 309. At this time, the driving current will no longer flow through the seventh transistor M2 to the light-emitting element 301, and the light-emitting element 301 will not emit light.

[0050] In some embodiments, such as Figures 4 to 7 As shown, the light-emitting unit 30 includes at least one N-type metal-oxide-semiconductor 01 and at least one P-type metal-oxide-semiconductor 02. The N-type metal-oxide-semiconductor 01 has a corresponding P-type substrate 011 and two spaced-apart N-doped regions 012 within its P-well. The P-type metal-oxide-semiconductor 02 has a corresponding N-type substrate 021 and two spaced-apart P-doped regions 022 within its N-well. For example... Figures 4 to 7 As shown, the P-type metal-oxide-semiconductor 02 is disposed within the P-well of the N-type metal-oxide-semiconductor 01, or, unlike... Figures 4 to 7As shown, the P-type metal-oxide-semiconductor 01 is disposed in the N-well of the P-type metal-oxide-semiconductor 02.

[0051] Specifically, in this embodiment, at least one of the multiple transistors (first transistor T2 to ninth transistor M1) in the light-emitting unit 30 can be the N-type metal-oxide-semiconductor 01, and at least one can be the P-type metal-oxide-semiconductor 02. The type of different transistors can be set according to the position and function of the transistor in the light-emitting unit 30. The gate-source voltage of the transistor corresponding to the N-type metal-oxide-semiconductor 01 is turned on when it is greater than its threshold voltage (greater than 0), and the gate-source voltage of the transistor corresponding to the P-type metal-oxide-semiconductor 02 is turned on when it is less than the threshold voltage (less than 0).

[0052] For example Figure 2 As shown, in this embodiment, the first transistor T2, the second transistor T2', the fifth transistor T6, and the sixth transistor T7 can all be the above-mentioned N-type metal-oxide-semiconductor 01, and the third transistor T4, the fourth transistor T5, the seventh transistor M2, the eighth transistor M3, and the ninth transistor M1 can all be the above-mentioned P-type metal-oxide-semiconductor 01 as an example, but are not limited thereto.

[0053] Among them, such as Figures 4 to 7 As shown here, the example only illustrates the placement of a P-type metal-oxide-semiconductor 02 within the P-well of an N-type metal-oxide-semiconductor 01. For instance, the P-well of the N-type metal-oxide-semiconductor 01 (understood as a single film layer) may contain a corresponding P-type substrate 011, two spaced-apart N-doped regions 012, and the aforementioned P-type metal-oxide-semiconductor 02. Of course, when a P-type metal-oxide-semiconductor 01 is placed within the N-well of the P-type metal-oxide-semiconductor 02, it can also be understood that the N-well of the P-type metal-oxide-semiconductor 02 (understood as a single film layer) contains a corresponding N-type substrate 021, two spaced-apart P-doped regions 022, and the aforementioned P-type metal-oxide-semiconductor 01.

[0054] Among them, combined Figures 2 to 7 As shown, the switching unit 305 (i.e., the eighth transistor M3) includes one of the N-type metal-oxide-semiconductor 01 and the P-type metal-oxide-semiconductor 02 (the figure only illustrates the latter as an example), and the data writing unit 302 includes at least the other of the N-type metal-oxide-semiconductor and the P-type metal-oxide-semiconductor (the figure only illustrates the former as an example); wherein, as Figures 4 to 7As shown, the P-type substrate 011 in the P-well of the N-type metal-oxide-semiconductor 01 is electrically connected to the third voltage line L3 for transmitting the third voltage signal VSS, and the N-type substrate 021 in the N-well of the P-type metal-oxide-semiconductor 02 is electrically connected to the fourth voltage line L4 for transmitting the fourth voltage signal (e.g., the aforementioned third power supply signal VDD). The amplitude of the third voltage signal VSS is smaller than the amplitude of the fourth voltage signal (e.g., the aforementioned third power supply signal VDD).

[0055] Among them, combined Figures 2 to 7 As shown, the P-region of the PN junction D0 is the P-type substrate 011 within the P-well of the N-type metal-oxide-semiconductor 01, and as... Figure 4 and Figure 5 As shown, the N-region of the PN junction D0 is located within the N-well of the P-type metal-oxide-semiconductor O2, or as... Figure 6 and Figure 7 As shown, the N-region of the PN junction D0 is located within the P-well of the N-type metal-oxide-semiconductor O1.

[0056] It should be noted that for the N-type metal-oxide-semiconductor 01, a P-type substrate 011 needs to be set in the corresponding P-well and a third voltage signal VSS with a lower potential needs to be applied to it to prevent current from flowing directly from the N-doped region 012 of the N-type metal-oxide-semiconductor 01 into the P-type substrate 011, so that the PN junction formed between the P-type substrate 011 and the N-doped region 012 is reverse biased. Similarly, for the P-type metal-oxide-semiconductor 02, an N-type substrate 021 needs to be set in the corresponding N-well and an N-type substrate 021 with a higher potential needs to be applied to it to prevent current from flowing directly from the P-doped region 022 of the P-type metal-oxide-semiconductor 02 into the N-type substrate 021, so that the PN junction formed between the N-type substrate 021 and the P-doped region 022 is reverse biased.

[0057] Understandably, since the P-well of the N-type metal-oxide-semiconductor 01 contains a P-type substrate 011, the combination... Figures 2 to 7 As shown, its P-type substrate 011 can be reused as the P-region of the PN junction DO in this invention; however, although the N-well of the P-type metal-oxide-semiconductor 02 is provided with an N-type substrate 021, considering that the drain of the eighth transistor M3 is electrically connected to the conduction control unit 304 through the first node A, and the source of the eighth transistor M3 is electrically connected to the drain of the seventh transistor M2 through the second node B, therefore, as Figure 4 and Figure 5 As shown, it is necessary to form the N-region of the PN junction D0 (electrically connected to the first node A) within the N-well of the P-type metal-oxide-semiconductor O2 through doping; of course, as Figure 6 and Figure 7 As shown, the N region of PN junction D0 can also be located in the P well of N-type metal-oxide-semiconductor O1. That is, the N region of PN junction D0 can be formed in the P well of N-type metal-oxide-semiconductor O1 by doping (electrically connected to the first node A).

[0058] Among them, combined Figures 2 to 7 As shown, the P-region of the PN junction D0 is the P-type substrate 011 within the P-well of the N-type metal-oxide-semiconductor 01, and as... Figure 4 and Figure 5 As shown, the N-region of the PN junction D0 is located within the N-well of the P-type metal-oxide-semiconductor O2, or as... Figure 6 and Figure 7 As shown, the N-region of the PN junction D0 is located within the P-well of the N-type metal-oxide-semiconductor O1.

[0059] In some embodiments, references, but not limited to, are made to, but not limited to, Figures 2 to 7 As shown, the display panel 10 includes a first insulating layer 901 located on the P-well of the N-type metal-oxide-semiconductor 01 and the N-well of the P-type metal-oxide-semiconductor 02, a third voltage line L3 and a fourth voltage line L4 located on the first insulating layer 901, and the N-region of the PN junction is electrically connected to the light-emitting element 301 through a first via 902 penetrating the first insulating layer 901.

[0060] For example, the figure Figures 2 to 7 As shown, the P-type metal-oxide-semiconductor 02 is disposed within the P-well of the N-type metal-oxide-semiconductor 01, regardless of whether the N-region of the PN junction DO is located within the N-well of the P-type metal-oxide-semiconductor 02 (e.g., the eighth transistor M3) (refer to...). Figure 4 and Figure 5 ) or located within the P-well of the N-type metal-oxide-semiconductor O1 (refer to, for example) Figure 6 and Figure 7 The N-regions of the PN junctions are all electrically connected to the light-emitting element 301 through the first via 902 penetrating the first insulating layer 901; for example, different from Figures 2 to 7 As shown, the N-type metal-oxide-semiconductor 01 is disposed in the N-well of the P-type metal-oxide-semiconductor 02. At this time, the N-region of the PN junction DO can also be located in the P-well of the N-type metal-oxide-semiconductor 01 or the N-well of the P-type metal-oxide-semiconductor 02. The N-region of the PN junction DO can still be electrically connected to the light-emitting element 301 through the second via (not shown) penetrating the first insulating layer 901.

[0061] Among them, combined Figures 2 to 7As shown, this explanation only uses the example of setting a P-type metal-oxide-semiconductor 02 within the P-well of an N-type metal-oxide-semiconductor 01. Regardless of... Figure 4 and Figure 5 The N-region of the PN junction D0 is formed in the N-well of a P-type metal-oxide-semiconductor O2 by doping, as shown below. Figure 6 and Figure 7 The N-region of the PN junction DO formed in the P-well of the N-type metal-oxide-semiconductor 01 by doping can be electrically connected to the first node A by forming a first via 902 in the first insulating layer 901 in the row. Furthermore, the display panel 10 may also include a second insulating layer 903 located on the third voltage line L3 and the fourth voltage line L4. The second insulating layer 903 may include a plurality of second sub-insulating layers stacked together. The first node A can be electrically connected to the light-emitting element 301 through the conductive material filled in the via in at least one second sub-insulating layer and the metal layer located on at least one second sub-insulating layer.

[0062] In some embodiments, combined with Figures 2 to 7 As shown, the switching transistor (i.e., the eighth transistor M3 mentioned above) in the switching unit 305 is a P-type metal-oxide-semiconductor 02. The active layer of the switching transistor includes the corresponding N-well and two P-doped regions 022 spaced apart within the N-well. The gate 904 of the switching transistor is located on the corresponding N-well. The source 905 of the switching transistor (e.g., connected to the second node B) is electrically connected to one of the P-doped regions 022 through a third via (penetrating the first insulating layer 901). The drain 906 of the switching transistor (e.g., connected to the first node A) is electrically connected to the other P-doped region 022 through a fourth via (penetrating the first insulating layer 901).

[0063] In this embodiment, the switching transistor (i.e., the eighth transistor M3 mentioned above) is a P-type metal-oxide-semiconductor 02. Its gate 904 can also be electrically connected to the switching signal line L5 of the row through the conductive material filled in the via in at least one second sub-insulating layer and the metal layer on the at least one second sub-insulating layer to load the switching signal PWM of the first row. Its source 905 and drain 906 can transmit signals through the path formed by the corresponding two P-doped regions 022 and the N-well located between them.

[0064] Among them, combined Figure 2 , Figure 4 and Figure 6As shown, when the light-emitting unit 30 is working normally (i.e., the first stage mentioned above), the first sub-voltage signal VSS1 transmitted by the first voltage line L1 (its corresponding low potential) controls the turn-on control unit 304 to be turned off. When the switch signal PWM of this row is at the corresponding low potential, it turns on the eighth transistor M3, and when its corresponding sub-data signal turns on the seventh transistor M2, the driving current (its flow direction is as follows) is generated. Figure 4 and Figure 6 (As shown by the arrow in the image) flows from the second node B to the first node A and then into the light-emitting element 301 to control its light emission.

[0065] Among them, combined Figure 2 , Figure 5 and Figure 7 As shown, when the light-emitting unit 30 is in the pre-shipment testing stage (i.e., the second stage mentioned above), the switching signal PWM of all rows is at the corresponding high potential, so that the eighth transistor M3 of all rows is turned off, and the driving current cannot flow into the light-emitting element 301. At this time, the second sub-voltage signal VSS2 (at its corresponding high potential) transmitted by the first voltage line L1 controls the control unit 304 of all rows to be turned on. Then, whether there is a test current (its flow direction is as follows) is determined. Figure 5 and Figure 7 (As indicated by the arrow in the diagram) flows from the first voltage line L1 to the first node A to detect whether the light-emitting element 301 is functioning properly.

[0066] In some embodiments, combined with Figures 2 to 7 As shown, the data writing transistor in the data writing unit 302 (e.g., the first transistor T2, the second transistor T2', the fifth transistor T6, or the sixth transistor T7) is the N-type metal-oxide-semiconductor 01. The active layer of the data writing transistor includes the corresponding P-well and two N-doped regions 012 spaced apart within the P-well. The gate 907 of the data writing transistor is located on the corresponding P-well. The source 908 of the data writing transistor is electrically connected to one of the N-doped regions 012 through a fifth via (penetrating the first insulating layer 901). The drain 909 of the data writing transistor is electrically connected to the other N-doped region 012 through a sixth via (penetrating the first insulating layer 901).

[0067] Similarly, in this embodiment, the data writing transistor (e.g., the first transistor T2, the second transistor T2', the fifth transistor T6, or the sixth transistor T7) is an N-type metal-oxide-semiconductor 01. Its gate 907 can also be electrically connected to the corresponding metal line on the first insulating layer 901 through the conductive material filled in the via through the first insulating layer 901. Its source 908 and drain 909 can transmit signals through the path formed by the corresponding two N-doped regions 012 and the P-well located between them.

[0068] This invention also provides an electronic terminal, which may include, but is not limited to, any of the display devices described above.

[0069] The display device and electronic terminal provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that, The display panel includes a display panel and a driver for driving the display panel to display an image. The display panel includes multiple light-emitting units, each light-emitting unit comprising: Light-emitting elements; A data writing unit is used to write data signals in the first stage. A driving unit, connected to the light-emitting element and the data writing unit, is used to generate a driving current according to the data signal in the first stage to drive the light-emitting element to emit light, and in the second stage, which is different from the first stage, no driving current is used to drive the light-emitting element to emit light. A conduction control unit is connected between the light-emitting element and the first voltage line; Wherein, the first voltage line is used to transmit a first sub-voltage signal in the first stage to control the conduction control unit to be cut off, so that the first voltage line and the light-emitting element are electrically disconnected. The first voltage line is also used to transmit a second sub-voltage signal in the second stage to control the conduction control unit to be turned on, so that the first voltage line and the light-emitting element are electrically connected, so as to detect whether the light-emitting element emits light. The conduction control unit includes a PN junction, the N region of which is electrically connected to the anode of the light-emitting element, and the P region of which is electrically connected to the first voltage line. The cathode of the light-emitting element is electrically connected to the second voltage line, and the amplitude of the second voltage signal transmitted by the second voltage line is smaller than the amplitude of the second sub-voltage signal. The light-emitting unit includes at least one N-type metal-oxide-semiconductor and at least one P-type metal-oxide-semiconductor. The P-well of the N-type metal-oxide-semiconductor is provided with a corresponding P-type substrate and two N-doped regions spaced apart. The N-well of the P-type metal-oxide-semiconductor is provided with a corresponding N-type substrate and two P-doped regions spaced apart. The P-type metal-oxide-semiconductor is disposed within the P-well of the N-type metal-oxide-semiconductor, or the P-type metal-oxide-semiconductor is disposed within the N-well of the P-type metal-oxide-semiconductor.

2. The display device according to claim 1, characterized in that, The light-emitting unit further includes: A switching unit is connected between the driving unit and the light-emitting element. In the second stage, the switching unit is used to control the driving unit and the light-emitting element to be electrically disconnected. In the first stage, the switching unit is used to control the driving unit and the light-emitting element to be electrically connected.

3. The display device according to claim 2, characterized in that, The switching unit includes one of the N-type metal-oxide-semiconductor and the P-type metal-oxide-semiconductor, and the data writing unit includes at least the other of the N-type metal-oxide-semiconductor and the P-type metal-oxide-semiconductor; Wherein, the P-type substrate in the P-well of the N-type metal-oxide-semiconductor is electrically connected to the third voltage line for transmitting the third voltage signal, and the N-type substrate in the N-well of the P-type metal-oxide-semiconductor is electrically connected to the fourth voltage line for transmitting the fourth voltage signal, wherein the amplitude of the third voltage signal is smaller than the amplitude of the fourth voltage signal. Wherein, the P-region of the PN junction is a P-type substrate within the P-well of the N-type metal-oxide-semiconductor, and the N-region of the PN junction is located within the N-well of the P-type metal-oxide-semiconductor, or the N-region of the PN junction is located within the P-well of the N-type metal-oxide-semiconductor.

4. The display device according to claim 3, characterized in that, The display panel includes a first insulating layer on the P-well of the N-type metal-oxide-semiconductor and the N-well of the P-type metal-oxide-semiconductor, a third voltage line and a fourth voltage line on the first insulating layer, and the N-region of the PN junction is electrically connected to the light-emitting element through a first via penetrating the first insulating layer.

5. The display device according to claim 3, characterized in that, The switching transistor in the switching unit is a P-type metal-oxide-semiconductor. The active layer of the switching transistor includes a corresponding N-well and two P-doped regions spaced apart within the N-well. The gate of the switching transistor is located on the corresponding N-well. The source of the switching transistor is electrically connected to one of the P-doped regions through a third via. The drain of the switching transistor is electrically connected to the other P-doped region through a fourth via.

6. The display device according to claim 3 or 5, characterized in that, The data writing transistor in the data writing unit is an N-type metal-oxide-semiconductor. The active layer of the data writing transistor includes a corresponding P-well and two N-doped regions spaced apart within the P-well. The gate of the data writing transistor is located on the corresponding P-well. The source of the data writing transistor is electrically connected to one of the N-doped regions through a fifth via, and the drain of the data writing transistor is electrically connected to the other N-doped region through a sixth via.

7. The display device according to claim 1, characterized in that, The light-emitting unit further includes: A mirror current unit is electrically connected to the drive unit and is used to transmit mirror current to the drive unit; The driving unit is used to generate the driving current based on the data signal and the mirror current.

8. An electronic terminal, characterized in that, Includes the display device as described in any one of claims 1 to 7.

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