Heuristic-based domain-specific wafer-level chip design optimization method, system and storage medium

Abstract

The present invention relates to the field of electronic design automation technology of chips, and more particularly to a method, system and storage medium for optimizing wafer-level chip design based on a heuristic method, wherein application analysis is performed for a certain type of application field, operators are obtained from the abstract analysis of computing applications, and an operator library is established, and the operators can constitute a directed acyclic graph to represent computing applications; a wafer-level chip architecture design space description is performed from a physical design dimension; computing applications are mapped to a wafer-level chip architecture for application deployment, and the performance of chip architecture and application deployment in a certain type of application field is evaluated through a total cost function; the architecture design space description is changed, application deployment is fine-tuned and the result is evaluated through multiple cycles and iterations, and the deployment scheme of wafer-level chip architecture and application is continuously optimized, and the optimal design is finally found. The present invention realizes efficient optimization of field-specific wafer-level chip design.

Description

Technical Field

[0001] The present invention relates to the field of electronic design automation technology for chips, and in particular to a heuristic-based field-specific wafer-level chip design optimization method, system and storage medium. Background Art

[0002] At present, the industry generally uses methods based on linear programming and machine learning to optimize the architecture of wafer-level chips, but they are not domain-specific, and cannot perform application analysis for a certain type of specific application and automatically design a better wafer-level chip architecture. Linear programming methods are less effective in solving large-scale problems, and the computational complexity increases exponentially, and the solution time also increases sharply; while methods such as machine learning require long-term training and tuning to have better performance on data sets. When facing different fields, machine learning and other methods need to be used again for a long time. Compared with traditional chip architectures, domain-specific wafer-level chip architecture optimization has the characteristics of large scale and domain-specific. Traditional chip architecture optimization methods such as linear programming or machine learning methods have shortcomings when facing this problem.

[0003] The application number is 202310110451 X, and its name is "Multi-core chip operator placement strategy generation method based on deep reinforcement learning". In this invention patent, training the deep reinforcement learning model requires a large amount of data and computing resources, and the training process takes a long time; the algorithm performance is limited by the accuracy of the simulator, and the actual performance on the hardware may differ from the simulation results; for new or unforeseen chip architectures and operator types, the generalization ability of the model needs to be verified. Summary of the invention

[0004] The present invention aims to solve the time-consuming and labor-intensive problem of manual design of domain-specific wafer-level chips, and proposes a heuristic-based domain-specific wafer-level chip design optimization method, system and storage medium to improve design efficiency and optimization effect; through application analysis, comprehensive consideration of architecture design parameters, operator deployment mapping, constraints and optimization goals, a heuristic algorithm is used to quickly search for the optimal design solution.

[0005] To achieve the above purpose, the technical solution adopted is:

[0006] A heuristic-based domain-specific wafer-level chip design optimization method, comprising:

[0007] Conduct application analysis for a certain application field, abstract operators from computing applications, establish an operator library, and operators can form a directed acyclic graph to represent computing applications;

[0008] Describe the wafer-level chip architecture design space from the physical design dimension;

[0009] Map computing applications to wafer-level chip architectures for application deployment, and use total cost functions to evaluate the performance of chip architectures and application deployments in certain application areas;

[0010] Through multiple iterative cycles, we change the architectural design space description, fine-tune the application deployment, and evaluate the results, continuously optimizing the wafer-level chip architecture and application deployment solutions to ultimately find the optimal design.

[0011] According to the heuristic domain-specific wafer-level chip design optimization method based on the present invention, further, the operator library contains relevant information of each operator, and the relevant information includes the execution time on different hardware, the type of operator and the requirement for storage space; multiple operators in the operator library are implemented through multiple language codes.

[0012] According to the heuristic domain-specific wafer-level chip design optimization method of the present invention, further, in the directed acyclic graph composed of operators, the nodes represent the operators, the edges represent the data dependencies between the operators, the weights of the nodes represent the execution time of the operators, and the weights of the edges represent the communication volume between the operators.

[0013] According to the heuristic-based field-specific wafer-level chip design optimization method of the present invention, further, the architecture design space refers to all possible combinations of architecture design parameters, and the architecture design parameters include wafer chip size, core size, core layout, and core interconnection and wiring.

[0014] According to the heuristic domain-specific wafer-level chip design optimization method of the present invention, further, the total cost function The calculation formula is as follows:

[0015]

[0016] in, is the execution time cost, which represents the time required for the application to execute on the wafer-level chip architecture; is the resource utilization cost, which indicates the efficiency of resource utilization of wafer-level chip architecture in specific field applications; is the power consumption cost, which represents the total power consumption of each chip when performing tasks; is the area cost, which represents the area occupied by the layout of multiple cores in the wafer-level chip architecture; are weight coefficients, the sum of these coefficients is 1.

[0017] According to the heuristic domain-specific wafer-level chip design optimization method of the present invention, further, multiple loop iterations are performed through heuristic methods and greedy strategies to gradually search for the optimal architecture and application deployment of the wafer-level chip. After multiple iterations, when the termination conditions are met, the wafer-level chip architecture and the deployment plan of the computing application in the field are output.

[0018] According to the heuristic domain-specific wafer-level chip design optimization method of the present invention, further, the changes in the architecture design space description include replacing core particles, adding and deleting core particles, and exchanging core particle layout disturbances, thereby generating some candidate architectures.

[0019] According to the heuristic domain-specific wafer-level chip design optimization method of the present invention, further, application deployment fine-tuning includes randomly mapping an operator to different core particles and mapping the operator to the new core particle to explore application deployment.

[0020] Furthermore, the present invention also proposes a domain-specific wafer-level chip design optimization system based on heuristics, including an application analysis and operator library establishment module, an architecture design space description module, an application deployment and result evaluation module, and an optimal design exploration and iteration module, wherein:

[0021] The application analysis and operator library building module is used to perform application analysis on a certain application field, abstract operators from computing applications, and build an operator library. Operators can form a directed acyclic graph to represent computing applications.

[0022] The architecture design space description module is used to describe the wafer-level chip architecture design space from the physical design dimension;

[0023] The application deployment and result evaluation module is used to map computing applications to wafer-level chip architectures for application deployment, and to evaluate the performance of chip architectures and application deployments in certain application fields through a total cost function;

[0024] The optimal design exploration iteration module is used to modify the architecture design space description, fine-tune the application deployment, and evaluate the results through multiple cycles of iteration, continuously optimizing the wafer-level chip architecture and application deployment solutions, and ultimately finding the optimal design.

[0025] Furthermore, the present invention also provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps of the above method when executed by a processor.

[0026] The beneficial effects achieved by adopting the above technical solution are:

[0027] The present invention aims to propose a heuristic-based domain-specific wafer-level chip design optimization method, which realizes efficient optimization of domain-specific wafer-level chip design by combining application analysis within the domain, architecture design space exploration, task deployment mapping exploration, heuristic search algorithm, etc., and automatically generates domain-specific wafer-level chip architecture and computing application deployment mapping scheme. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings of the embodiments of the present invention, wherein the drawings are only used to illustrate some embodiments of the present invention, but not to limit all embodiments of the present invention thereto.

[0029] Figure 1 1 is a flow chart of a heuristic-based field-specific wafer-level chip design optimization method according to Embodiment 1 of the present invention;

[0030] Figure 2 It is a block diagram of a heuristic-based domain-specific wafer-level chip design optimization method according to Embodiment 1 of the present invention;

[0031] Figure 3 is a directed acyclic graph formed by operators in the second embodiment of the present invention;

[0032] Figure 4 is a layout diagram of the sequence pair (<4 3 1 6 2 5>, <6 3 5 4 1 2>) of the second embodiment of the present invention;

[0033] Figure 5 is a schematic diagram of a core particle interconnection structure according to a second embodiment of the present invention;

[0034] Figure 6 It is a diagram of dividing and mapping tasks on a wafer-level chip according to the second embodiment of the present invention;

[0035] Figure 7 This is a diagram of the mission critical path of the second embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings of specific embodiments of the present invention to clearly and completely describe the exemplary scheme of the embodiment of the present invention. Unless otherwise defined, the technical terms or scientific terms used in the present invention should be the common meanings understood by people with ordinary skills in the field. Embodiment 1

[0037] like Figure 1 and Figure 2 As shown, this embodiment discloses a heuristic-based field-specific wafer-level chip design optimization method, through which agile development of wafer-level chips is performed for applications in the field, specifically including the following contents:

[0038] Step S101: Perform application analysis on a certain application field, abstract operators from computing applications, establish an operator library, and the operators can form a directed acyclic graph to represent computing applications.

[0039] Perform application analysis and abstraction for a certain type of application field, and split the operators therein. For example, in the field of machine learning, various functional operation units such as convolution kernels, pooling kernels, matrix operations, nonlinear functions, etc. are split and abstracted to establish a unified operator library. The operator library contains relevant information of each operator, such as the execution time on different hardware, the type of operator, and the demand for storage space. These operators are abstracted and analyzed from the application, and the operators can form a directed acyclic graph to represent the computing application. In the directed acyclic graph, the node represents the operator, the edge represents the data dependency between the operators, the node weight represents the execution time of the operator, and the edge weight represents the communication volume between the operators.

[0040] Step S102: Describe the wafer-level chip architecture design space from the physical design dimension, where the architecture design space refers to all possible combinations of architecture design parameters.

[0041] Wafer chip size: The wafer size is 8 inches, 12 inches or other sizes.

[0042] Die size: The size of the die that can be mounted on a wafer-level chip, the length and width of the bare die.

[0043] Chip layout: The layout of the chips on the wafer and their relative positions on the wafer.

[0044] Chip interconnection and wiring, etc.: The interconnection routing of the chip on the wafer and the wiring information on the interposer, etc.

[0045] Step S103: Map the computing application to the wafer-level chip architecture for application deployment, and evaluate the performance of the chip architecture and application deployment in a certain application field through a total cost function.

[0046] In the wafer-level chip architecture of mounted chips, application deployment and result evaluation are key steps to ensure system performance, power consumption and reliability. Chiplet technology integrates different functional modules in the form of small chips (chiplets) to achieve efficient modular design. Task mapping is to map specific computing tasks to different chiplets to ensure task load balancing and efficient resource utilization, that is, to reasonably and efficiently divide each operator of the directed acyclic graph that constitutes the computing application to a specific chip.

[0047] Based on the current wafer-level chip architecture and application deployment, the chip evaluation results can be obtained, including the specific execution time, resource utilization, power consumption and area evaluation of the computing application, and then the application effect of the current architecture and deployment scheme for a certain application field can be evaluated. In wafer-level chip design optimization, the total cost function It is the core indicator for evaluating the performance of the current architecture and application deployment in specific field applications. This function measures chip performance by weighted sum of the following four main cost items:

[0048] Execution time cost : It indicates the time required for an application to execute on a wafer-level chip architecture, reflecting the computing efficiency of the chip.

[0049] Resource utilization cost : Indicates the resource utilization efficiency of wafer-level chip architecture in specific application fields.

[0050] Power consumption : It represents the total power consumption of each core particle when performing tasks, reflecting the energy consumption performance of the architecture.

[0051] Area cost : Represents the area occupied by the layout of multiple cores in the wafer-level chip architecture, measuring the space efficiency of the architecture.

[0052] These cost items are multiplied by their corresponding weight coefficients , and the sum of these coefficients is 1. The chip design optimization problem is a multi-objective optimization problem. The goal is to reduce the total cost To improve the overall performance of the chip. Each iteration of optimization aims to reduce , thereby achieving better chip design in multiple dimensions such as execution efficiency, resource utilization, power consumption and area.

[0053] Step S104: Modify the architecture design space description, fine-tune the application deployment, and evaluate the results through multiple cycles of iteration, continuously optimize the wafer-level chip architecture and application deployment plan, and finally find the optimal design. This process can be divided into the following two main steps, and the design is gradually improved through multiple cycles of iteration.

[0054] Changes to the architecture design space description: Explore new architectures based on the current architecture, including replacing core particles, adding and deleting core particles, and changing and swapping core particle layouts, thereby generating some candidate architectures. The candidate architectures are fine-tuned based on the current architecture.

[0055] Fine-tuning application deployment and result evaluation: Based on some of the candidate architectures currently being explored, explore application deployment. By fine-tuning the current application deployment, including randomly mapping an operator to different core particles and mapping operators to new core particles, better deployment results can be obtained and evaluated.

[0056] Multiple iterations are implemented through heuristic methods and greedy strategies, using simulated annealing algorithms to gradually search for the optimal design of wafer-level chips. After multiple iterations, when the termination conditions are met, the wafer-level chip architecture and the deployment plan for computing applications in the field are output. Termination condition: Set the cooling temperature of the simulated annealing algorithm, that is, the termination temperature parameter. When the simulated annealing algorithm is reduced from the starting temperature to the termination temperature, the solution space exploration is terminated, and the wafer-level chip architecture and the deployment plan for computing applications in the field are output.

[0057] Corresponding to the above method, this embodiment also proposes a domain-specific wafer-level chip design optimization system based on heuristics, including an application analysis and operator library establishment module, an architecture design space description module, an application deployment and result evaluation module, and an optimal design exploration and iteration module, wherein:

[0058] The application analysis and operator library establishment module is used to perform application analysis on a certain type of application field, abstract operators from computing applications, establish an operator library, and the operators can form a directed acyclic graph to represent computing applications.

[0059] The architecture design space description module is used to describe the wafer-level chip architecture design space from the physical design dimension.

[0060] The application deployment and result evaluation module is used to map computing applications to wafer-level chip architecture for application deployment, and to evaluate the performance of chip architecture and application deployment in a certain application field through a total cost function.

[0061] The optimal design exploration iteration module is used to modify the architecture design space description, fine-tune the application deployment, and evaluate the results through multiple cycles of iteration, continuously optimizing the wafer-level chip architecture and application deployment solutions, and ultimately finding the optimal design.

[0062] This embodiment also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented. Embodiment 2

[0063] This embodiment provides a domain-specific wafer-level chip design optimization method based on heuristics, which specifically includes the following contents:

[0064] Step S201: Analysis of domain applications and establishment of operator library.

[0065] 1) Select a variety of typical applications in the field, perform operator abstraction, split the computing application into a directed acyclic graph of operators, abstract multiple operators one by one to form an operator library. The directed acyclic graph of operators is as follows: Figure 3 shown.

[0066] 2) Implement various operators in the operator library through codes in multiple languages, such as C / C++, Python, CUDA, etc., and compile various operators into executable files through the compiler.

[0067] 3) The executable file compiled by the operator is simulated through the simulator, and the execution of the operator on different hardware is simulated to obtain the execution time. The operator library information is shown in Table 1.

[0068] Table 1 Operator library information

[0069]

[0070] Step S201: Architecture design space description.

[0071] 1) Design a coreparticle library, which contains various coreparticle information, such as the cost, performance, power consumption and area of ​​various CPU, GPU, CGRA, FPGA and other coreparticles, as shown in Table 2.

[0072] Table 2 Core library information

[0073]

[0074] 2) Use automated tools to synthesize information such as the area and power consumption of various chiplets. First, provide a functional description of the chiplet, usually using a hardware description language (HDL) such as Verilog or VHDL. These descriptions define the functional logic of the chiplet. Then, use automated tools such as open source tools such as chipyard and opencgra or commercial tools to synthesize the chiplet information to obtain information such as the area and power consumption of the chiplet. In addition, you can also purchase information such as the model parameters of the chiplet.

[0075] 3) Selecting core particles from the core particle library: Selecting core particles from the core particle library based on the wafer-level chip architecture optimization objectives, such as cost, performance, power consumption, area and other factors.

[0076] 4) Construct sequence pairs to represent the layout of the core particles on the wafer-level chip. The sequence pair representation method is as follows. Construct sequence pairs. The horizontal and vertical relative positions between core particles A and B are as follows:

[0077] →A is to the left of B

[0078] →A is on B

[0079] →A is under B

[0080] →A is to the right of B

[0081] According to the property that sequence pairs can represent the horizontal and vertical relationships between all modules, the relationship between any two modules can be easily known from a sequence pair. For example, the layout of the sequence pair (<4 3 1 6 2 5>, <6 3 5 4 1 2>) is as follows: Figure 4 shown.

[0082] 5) Based on the core group concept, routing nodes are used to interconnect the cores on the wafer level chip, such as Figure 5 shown.

[0083] Step S103: application deployment and result evaluation.

[0084] 1) Tasks are mapped one by one on the current architecture, such as Figure 6 shown.

[0085] 2) Use the critical path algorithm to evaluate the running time of the computing application. In the time dimension, if node 4 is the last to complete the execution, the length of the critical path is, Figure 7 shown.

[0086] 3) The layout area of ​​the core particle is calculated from the layout represented by the sequence pair using the longest common subsequence algorithm.

[0087] 4) Calculate the line length between core particles and the data communication cost, etc.

[0088] Step S104: optimal design exploration iteration.

[0089] 1) Use simulated annealing algorithm for iteration.

[0090] 2) In each iteration, the current architecture is fine-tuned and the task deployment mapping is fine-tuned, so that the current architecture evaluation result can be obtained within linear time complexity. The computing application running time and core particle layout information can be accurately evaluated within linear time complexity.

[0091] 3) Compare the new solution generated in each iteration with the saved solution. If it is better than the current solution, save it. Otherwise, save the current solution with a certain probability.

[0092] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0093] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0094] The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

[0095] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits, and accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of software function modules. The present invention is not limited to any specific form of combination of hardware and software.

[0096] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A domain-specific wafer-level chip design optimization method based on heuristics, characterized in that: Include: Conduct application analysis for a certain type of application field, abstract operators from computing applications, and establish an operator library. Operators can form a directed acyclic graph to represent computing applications. In the directed acyclic graph, nodes represent operators, edges represent data dependencies between operators, node weights represent operator execution time, and edge weights represent communication volume between operators. Describe the wafer-level chip architecture design space from the physical design dimension; Map computing applications to wafer-level chip architectures for application deployment, and use the total cost function to evaluate the performance of chip architectures and application deployments in a certain application field. The calculation formula is as follows: ;in, is the execution time cost, which represents the time required for the application to execute on the wafer-level chip architecture; is the resource utilization cost, which indicates the efficiency of resource utilization of wafer-level chip architecture in specific field applications; is the power consumption cost, which represents the total power consumption of each chip when performing tasks; is the area cost, which represents the area occupied by the layout of multiple cores in the wafer-level chip architecture; are weight coefficients, the sum of these coefficients is 1; Through multiple iterative cycles, we change the architectural design space description, fine-tune the application deployment, and evaluate the results, continuously optimizing the wafer-level chip architecture and application deployment solutions to ultimately find the optimal design.

2. The heuristic-based domain-specific wafer-level chip design optimization method according to claim 1, characterized in that: The operator library contains relevant information about each operator, including the execution time on different hardware, the type of operator, and the storage space requirements; multiple operators in the operator library are implemented using codes in multiple languages.

3. The heuristic-based domain-specific wafer-level chip design optimization method according to claim 1, characterized in that: The architecture design space refers to all possible combinations of architecture design parameters, which include wafer chip size, core size, core layout, and core interconnection and wiring.

4. The heuristic-based domain-specific wafer-level chip design optimization method according to claim 1, characterized in that: Through multiple iterations, heuristic methods and greedy strategies, the optimal architecture and application deployment of wafer-level chips are gradually searched. After multiple iterations, when the termination conditions are met, the wafer-level chip architecture and the deployment plan for computing applications in the field are output.

5. The heuristic-based domain-specific wafer-level chip design optimization method according to claim 4, characterized in that: The changes in the architectural design space description include replacing coregrains, adding and deleting coregrains, and perturbing and exchanging coregrain layouts, thereby generating some candidate architectures.

6. The heuristic-based domain-specific wafer-level chip design optimization method according to claim 4, characterized in that: Fine-tuning of application deployment includes randomly mapping an operator to different core particles and mapping operators to new core particles to explore application deployment.

7. A domain-specific wafer-level chip design optimization system based on heuristics, characterized in that: The system is used to implement the heuristic-based field-specific wafer-level chip design optimization method as described in any one of claims 1 to 6, and includes an application analysis and operator library establishment module, an architecture design space description module, an application deployment and result evaluation module, and an optimal design exploration and iteration module, wherein: The application analysis and operator library building module is used to perform application analysis on a certain application field, abstract operators from computing applications, and build an operator library. Operators can form a directed acyclic graph to represent computing applications. The architecture design space description module is used to describe the wafer-level chip architecture design space from the physical design dimension; The application deployment and result evaluation module is used to map computing applications to wafer-level chip architectures for application deployment, and to evaluate the performance of chip architectures and application deployments in certain application fields through a total cost function; The optimal design exploration iteration module is used to modify the architecture design space description, fine-tune the application deployment, and evaluate the results through multiple cycles of iteration, continuously optimizing the wafer-level chip architecture and application deployment solutions, and ultimately finding the optimal design.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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