Storage device, use method, electronic device and storage medium

Abstract

The present application provides a storage device, a method of using, an electronic device and a storage medium, wherein the storage device resides in a baseband chip, and the storage device includes a storage module and a control module; the storage module is used to store a first signal data stream generated in the process of executing a first service based on a first protocol through a first algorithm of the baseband chip; the control module is used to determine a first target signal data from the first signal data stream according to the first control data of the first service, and output the first target signal data to the first service module according to the first control data. The storage device in the present application can reduce the difficulty of algorithm reception and reduce chip costs.

Description

Technical Field

[0001] The present application relates to the technical field of data storage, and in particular to a storage device, a method of using the storage device, an electronic device and a storage medium. Background Art

[0002] In OFDM (Orthogonal Frequency Division Multiplexing) wireless communication baseband chips, due to the complexity of wireless channels and the high interference, the complexity of the physical layer receiver algorithm is often very high, resulting in high difficulty and cost in chip implementation. For cost and performance considerations, the general implementation is achieved through application specific integrated circuits (ASIC). While meeting the physical layer performance, the size of the chip determines the competitiveness of the product.

[0003] The OFDM physical layer receiver algorithm process generally includes downsampling, time domain synchronization, FFT (Fast Fourier Transform) windowing (window sampling) and FFT, channel estimation, frequency domain equalization and demodulation, and decoding. Among them, time domain synchronization uses the training sequence in the frame to complete frame detection and find the beginning of the frame, as well as frequency deviation and DC (direct current) estimation. Time domain synchronization requires memory to store data. As the system rate requirements are getting faster and faster, the physical layer protocol of the OFDM system has been updated, and each time the protocol supports more and more frame formats and more and more features. Existing storage devices cannot adapt to the needs of protocol changes. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a storage device, a method of use, an electronic device and a storage medium to overcome the problems in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a storage device, the storage device resides in a baseband chip, and the storage device includes a storage module and a control module;

[0006] The storage module is used to store a first signal data stream generated in a process in which the baseband chip executes a first service based on a first protocol through a first algorithm;

[0007] The control module is used to determine first target signal data from the first signal data stream according to first control data of the first service, and output the first target signal data to the first service module according to the first control data.

[0008] In some technical solutions of the present application, the storage module is further used to store a second signal data stream generated in the process of the baseband chip executing a second service based on a second protocol through a second algorithm;

[0009] The control module is further configured to determine second target signal data from the second signal data stream according to second control data of the second service, and output the second target signal data to the second service module according to the second control data.

[0010] In some technical solutions of the present application, the control module includes a single-port first-in-first-out queue; the first signal data stream enters the control module through the single-port first-in-first-out queue.

[0011] In some technical solutions of the present application, the control module includes an address control module, and the first control data includes first pointer data;

[0012] The control module, when used to determine first target signal data from the first signal data stream according to the first control data of the first service, includes:

[0013] The address control module is used to jump from the first signal data stream to the first target signal data according to the first pointer data.

[0014] In some technical solutions of the present application, the control module includes a rate control module, and the first control data includes first rate data;

[0015] The control module, when used to output the first target signal data to the first service module according to the first control data, includes:

[0016] The rate control module is used to adjust the rate of outputting the first target signal data according to the first rate data.

[0017] In some technical solutions of the present application, the control module includes a depth control module, and the first control data includes first depth data;

[0018] The control module, when used to output the first target signal data to the first service module according to the first control data, includes:

[0019] The depth control module is used to adjust the depth of the single-port first-in-first-out queue according to the first depth data.

[0020] In a second aspect, an embodiment of the present application provides a method for using a storage device, wherein the storage device resides in a baseband chip, and the storage device includes a storage module and a control module; the method for using the storage device includes:

[0021] The storage module stores a first signal data stream generated in a process in which the baseband chip executes a first service based on a first protocol through a first algorithm;

[0022] The control module determines first target signal data from the first signal data stream according to first control data of the first service, and outputs the first target signal data to the first service module according to the first control data.

[0023] In some technical solutions of the present application, the above method further includes:

[0024] The storage module stores a second signal data stream generated in the process of the baseband chip executing a second service based on a second protocol through a second algorithm;

[0025] The control module determines second target signal data from the second signal data stream according to second control data of the second service, and outputs the second target signal data to the second service module according to the second control data.

[0026] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for using the above-mentioned storage device when executing the computer program.

[0027] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for using the storage device are executed.

[0028] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0029] The storage device in the present application resides in the baseband chip, and the storage device includes a storage module and a control module; the storage module is used to store the first signal data stream generated in the process of the baseband chip executing the first service through the first algorithm based on the first protocol; the control module is used to determine the first target signal data from the first signal data stream according to the first control data of the first service, and output the first target signal data to the first service module according to the first control data. The storage device in the present application can reduce the difficulty of algorithm reception and reduce chip costs.

[0030] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 A schematic diagram of a storage device provided in an embodiment of the present application is shown;

[0033] Figure 2 A schematic diagram of another storage device provided in an embodiment of the present application is shown;

[0034] Figure 3 A schematic diagram of a FIFO with a read jump function provided in an embodiment of the present application is shown;

[0035] Figure 4 A schematic diagram of a FIFO with a read-write and simultaneous jump function provided by an embodiment of the present application is shown;

[0036] Figure 5 A schematic diagram of a FIFO with controllable reading rate provided in an embodiment of the present application is shown;

[0037] Figure 6 A schematic diagram of a frame structure provided in an embodiment of the present application is shown;

[0038] Figure 7 A schematic diagram of another partial frame structure provided in an embodiment of the present application is shown;

[0039] Figure 8 A schematic diagram showing a flow chart of a method for using a storage device provided in an embodiment of the present application;

[0040] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0042] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0043] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0044] In OFDM wireless communication baseband chips, due to the complexity of wireless channels and the high interference, the physical layer receiver algorithm complexity is often very high, resulting in high difficulty and cost in chip implementation. For cost and performance considerations, the general implementation is achieved through application-specific integrated circuits (ASICs). While meeting the physical layer performance, the size of the chip determines the competitiveness of the product.

[0045] The OFDM physical layer receiver algorithm process generally includes downsampling, time domain synchronization, FFT (Fourier transform) windowing (window sampling) and FFT, channel estimation, frequency domain equalization and demodulation, and decoding. Among them, time domain synchronization uses the training sequence in the frame to complete frame detection and find the beginning of the frame, as well as frequency offset and DC estimation. Time domain synchronization requires memory to store data, and the main source is the two time domain algorithms themselves and the frequency domain implementation delay.

[0046] As the system rate requirements are getting faster and faster, the physical layer protocol of the OFDM system has been updated, and each time the protocol supports more and more frame formats and features. Take 802.11 as an example. From WIFI4 to WIFI5, to WIFI6, and then to WIFI7, the physical layer frame format has been increasing, and the subcarrier interval has been shortened. The time domain synchronization memory structure of the OFDM system is determined by its specific functions. Therefore, a universal time domain memory structure is very important for the implementation of the entire receiver baseband system. This ensures that when the protocol is updated or different protocols are used, the time domain memory structure does not need to be modified significantly, and the implementation and verification of the entire system can be efficient and controllable, which can greatly improve the competitiveness of the chip, and avoid the need to cope with more complex frame structures by continuously increasing memory, effectively controlling the chip size and saving costs.

[0047] Based on this, the embodiments of the present application provide a storage device, a method of use, an electronic device and a storage medium, which are described below by way of embodiments. Some implementation methods of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0048] Figure 1 A schematic diagram of a storage device provided in an embodiment of the present application is shown, wherein the storage device resides in a baseband chip, and the storage device includes a storage module and a control module;

[0049] The storage module is used to store a first signal data stream generated in a process in which the baseband chip executes a first service based on a first protocol through a first algorithm;

[0050] The control module is used to determine first target signal data from the first signal data stream according to first control data of the first service, and output the first target signal data to the first service module according to the first control data.

[0051] The present application directly determines the first target signal from the first signal data stream and outputs it to the first service module, thereby reducing the difficulty of algorithm reception and reducing chip costs.

[0052] When the protocol changes, the storage module is further used to store a second signal data stream generated in the process of the baseband chip executing the second service based on the second protocol through the second algorithm;

[0053] The control module is further configured to determine second target signal data from the second signal data stream according to second control data of the second service, and output the second target signal data to the second service module according to the second control data.

[0054] For example, the processing process of the first protocol (wifi4 20M bandwidth) is to downsample the IQ data with a sampling rate of 80M to 20M sampling rate data, and the second protocol is to convert the 80M (wifi4 40M) sampling rate data into 40M sampling rate data.

[0055] The storage device in the embodiment of the present application can be applied to an OFDM wireless communication baseband chip. After the OFDM system digital baseband obtains the time domain IQ (In-Phase Quadrature, in-phase orthogonal signal) stream, the time domain synchronization module needs to complete two major functions: first, the preamble synchronization process, which requires the frame's preamble preamble (guide sequence) to be synchronized in the time domain; second, the data output process, after the synchronization is successful, the time domain data needs to be sent to the FFT (first service module). Among them, the preamble synchronization process is generally implemented by cross-correlating and autocorrelating with a known preamble sequence. The preamble synchronization part often includes a short training sequence and a long training sequence, and each of them needs to perform related synchronization operations. Therefore, the preamble synchronization process itself often includes multiple stages, usually including a short training sequence synchronization process and a long training sequence synchronization process, and even after the real synchronization, short training or long training sequences are used to make some CFO (carry frequency offset) estimates.

[0056] The requirements for memory in the preamble phase are as follows: In the first phase, the input IQ stream is used for synchronization. At the same time, data is directly written into the memory. At the beginning of the second phase, synchronization needs to be performed by backing off a certain number of points.

[0057] The requirements for memory in the data transmission stage are as follows: the data in the LTF (Long Training Field) / HE-LTF (HE, High-efficiency) stage is first used for DC estimation and channel estimation, and then the data is transmitted. The memory needs to store all the data in the LTF / HE-LTF stage. Since there are many HE-LTF points, when the mode check is identified as HE PPDU (PPUD, PHY protocol data unit, physical layer protocol data unit), the memory depth needs to be increased. At this time, the memory in the frequency domain stage can be reused. In the data transmission stage, once the memory is read empty again, the memory depth can be reduced, and the IQ stream can be processed in real time without storage, reducing power consumption and latency.

[0058] The control module in the embodiment of the present application adopts a single-port first-in-first-out queue, and the first signal data stream enters the control module through the single-port first-in-first-out queue. The control module includes an address control module, a rate control module and a depth control module. The address control module is used to jump from the first signal data stream to the first target signal data according to the first pointer data. The rate control module is used to adjust the rate of outputting the first target signal data according to the first rate data. The depth control module is used to adjust the depth of the single-port first-in-first-out queue according to the first depth data.

[0059] When implementing it, you can refer to Figure 2 The structure shown includes three parts: address control module, FIFO read and write rate control (rate control module), and FIFO depth control (depth control module); the address control module is used to latch the read address to realize the function that the read address is discontinuous and can jump. In order to save area, this application uses a single-port FIFO, so reading and writing cannot be done at the same time.

[0060] The rate control module in the present application controls the FIFO. The control process of the rate control module is determined by the processing stage. The processing stage here includes the initial stage of spitting out the number and the final stage of spitting out the number. Different processing stages correspond to different rate control data, and the rate data here (including the first rate data and the second rate data) can be a specific rate value.

[0061] Specifically, the FIFO read / write rate control module implements synchronization of different processing stages and controls the read / write rates. In the initial stage of data output, a large amount of data is stored in the FIFO. At this time, the FIFO read rate needs to be adjusted to the maximum value to output data to the FFT as quickly as possible. Once the FIFO is empty (reaching the end of the data output stage), the FIFO read rate can be set to 0. The IQ stream is directly sent to the subsequent module without passing through the FIFO, which can reduce power consumption and latency.

[0062] The depth control module in the present application controls the FIFO. The control of the depth control module is mainly based on the format of the target signal data frame structure, and different formats correspond to different depth data (including first depth data and second depth data). The depth data here can be a specific depth value.

[0063] Specifically, the FIFO depth control module controls the depth of the FIFO in real time for frame structures of different formats. When the mode is identified as HE, the FIFO depth can be increased due to the large number of HE-LTF points; when it is identified as HT (High throughput) / LEGACY, the FIFO depth can be reduced. When all the accumulated data in the data output phase is read out, the FIFO depth can be reduced to the minimum value.

[0064] The specific control process of the address control module is as follows: Figure 3 and Figure 4 shown. Figure 3 and Figure 4 This is a FIFO with a jump function proposed in this application. By changing the read and write pointers of the FIFO, the read and write jump of the FIFO is realized. It has the following functions: (1) For data that is reused, the starting address of the write is latched, and the read pointer jumps to its starting address when it is used; (2) GI (Guard Interval, protection interval) data is not used, and the read pointer is added with the offset of the number of GIs and directly skipped; skipping invalid data saves time and power consumption; (3) After the FIFO is read empty, the write pointer is changed so that the write pointer starts from zero, so that the memory space of the synchronization module can be released in time; (4) The read and write pointers jump at the same time, and part of the FIFO space is released synchronously.

[0065] Figure 5 This is a timing diagram of FIFO with different read and write rates. For a single-port memory, since the write rate is constant, the fastest read rate is within a cycle. Except for one beat for writing, the read signal fifo_ren is always valid at other times. The fifo_ren signal is generated by the FIFO read and write rate control module. In the initial stage of successful synchronization, the read rate can be adjusted to the maximum. In the later stage of spitting out data, once the FIFO is read empty, the read and write rates can be adjusted to 0, that is, the input data of the synchronization module no longer passes through the FIFO. The FIFO with controllable read and write rates effectively reduces the power consumption and latency of the system.

[0066] Figure 6 and Figure 7 Schematic diagrams of the pre-HE part and the HE part of the frame structure of the HE SU PPDU (SU, singer-user, single user) in 802.11ax are given respectively. Figure 6STF1 (STF, Short Training Field) and STF2 in it are used for frame detection. At this time, FIFO is only written but not read, and data needs to be continuously stored. At this stage, only the memory of the synchronization module is in use in the entire system. The LTF position of the frame is found by cross-correlating and autocorrelating with the known sequence. LTF can be used for channel estimation and DC estimation. The address control module is used to latch the starting address of LTF. The FIFO in this application has a jump function, and the LTF data is output directly according to the latched address. In the data output stage, GI data is not used, and the read pointer is directly changed so that the FIFO does not output this segment of data to the synchronization module. According to different frame types, the FIFO depth control module dynamically adjusts the memory size. When it is identified as HE SU, due to the large amount of HE-LTF data, the FIFO depth can be increased in real time. Figure 7 For the DATA data segment in the time domain, the time domain only needs to give the data to FFT. When there is data accumulation in the FIFO, in order to reduce data accumulation and shorten the delay of the entire system, the FIFO read rate is adjusted to the maximum value. Once all the data stored in the FIFO is input into the FFT module, the newly arrived data no longer passes through the FIFO, and the IQ data stream (referring to a pair of phase-orthogonal modulation signals, that is, the baseband signal) and the synchronization module are directly connected. At this time, the FIFO read and write rate control module sets the read and write rates to 0, and sets the FIFO depth to the minimum value.

[0067] The structure of the present application can support several protocols such as HE / VHT / HT / LEGCY at the same time; (1) the starting addresses of key sequences of different protocols are latched through address control, for example, HT latches the starting address of LTF; HE latches the starting address of LTF and HE-LTF; (2) the FIFO size is adjusted in real time through depth control. For HE with large data volume, the FIFO depth is increased; for other modes with small data volume, the FIFO depth is reduced;

[0068] When more complex protocols emerge in the future, (1) the number of latched addresses in the address control module can be increased; (2) the ratio of the read and write rates of the rate control module can be improved; (3) the FIFO size level of the depth control module can be increased, and different FIFO sizes can be selected according to different protocols; for example, now there are only two levels: HE and non-HE; in the future, there can be three levels: new protocol, HE, and non-HE.

[0069] In an alternative embodiment, Figure 8 A flow chart of a method for using a storage device provided in an embodiment of the present application is shown, wherein the storage device resides in a baseband chip, and the storage device includes a storage module and a control module; the method includes steps S101-S102; specifically:

[0070] S101, the storage module stores a first signal data stream generated in a process in which the baseband chip executes a first service based on a first protocol through a first algorithm;

[0071] S102: The control module determines first target signal data from the first signal data stream according to first control data of the first service, and outputs the first target signal data to a first service module according to the first control data.

[0072] The storage module stores a second signal data stream generated in the process of the baseband chip executing a second service based on a second protocol through a second algorithm;

[0073] The control module determines second target signal data from the second signal data stream according to second control data of the second service, and outputs the second target signal data to the second service module according to the second control data.

[0074] The control module comprises a single-port first-in first-out queue; the first signal data stream enters the control module through the single-port first-in first-out queue.

[0075] The control module includes an address control module, and the first control data includes first pointer data;

[0076] The control module, when used to determine first target signal data from the first signal data stream according to first control data of the first service, includes:

[0077] The address control module is used to jump from the first signal data stream to the first target signal data according to the first pointer data.

[0078] The control module includes a rate control module, and the first control data includes first rate data;

[0079] When the control module is used to output the first target signal data to the first service module according to the first control data, the control module includes:

[0080] The rate control module is used to adjust the rate of outputting the first target signal data according to the first rate data.

[0081] The control module includes a depth control module, and the first control data includes first depth data;

[0082] When the control module is used to output the first target signal data to the first service module according to the first control data, the control module includes:

[0083] The depth control module is used to adjust the depth of the single-port first-in-first-out queue according to the first depth data.

[0084] like Fig. 9 As shown, an embodiment of the present application provides an electronic device for executing the method for using the storage device in the present application, the device includes a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method for using the storage device when executing the computer program.

[0085] Specifically, the above-mentioned memory and processor may be general-purpose memory and processor, which are not specifically limited here. When the processor runs the computer program stored in the memory, the above-mentioned method for using the storage device can be executed.

[0086] Corresponding to the method for using the storage device in the present application, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for using the storage device are executed.

[0087] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is run, the above-mentioned method for using the storage device can be executed.

[0088] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0089] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0090] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0091] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0092] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0093] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A storage device, characterized in that: The storage device resides in the baseband chip, and the storage device includes a storage module and a control module; The storage module is used to store a first signal data stream generated in a process in which the baseband chip executes a first service based on a first protocol through a first algorithm; The control module is used to determine first target signal data from the first signal data stream according to first control data of the first service, and output the first target signal data to the first service module according to the first control data; the first control data includes first pointer data, first rate data and first depth data; The control module includes a single-port first-in first-out queue; the first signal data stream enters the control module through the single-port first-in first-out queue; The control module includes an address control module, a rate control module and a depth control module; The address control module is used to jump from the first signal data stream to the first target signal data according to the first pointer data; The rate control module is used to adjust the rate of outputting the first target signal data according to the first rate data; The depth control module is used to adjust the depth of the single-port first-in-first-out queue according to the first depth data.

2. The storage device according to claim 1, characterized in that When the protocol changes, the storage module is further used to store a second signal data stream generated in the process of the baseband chip executing the second service based on the second protocol through the second algorithm; The control module is also used to determine second target signal data from the second signal data stream according to second control data of the second business, and output the second target signal data to the second business module according to the second control data; the second control data includes second pointer data, second rate data and second depth data.

3. A method for using a storage device, characterized in that: The storage device resides in the baseband chip, and the storage device includes a storage module and a control module; the use method includes: The storage module stores a first signal data stream generated in a process in which the baseband chip executes a first service based on a first protocol through a first algorithm; The control module determines first target signal data from the first signal data stream according to first control data of the first service, and outputs the first target signal data to the first service module according to the first control data; the first control data includes first pointer data, first rate data and first depth data; The control module includes a single-port first-in first-out queue; the first signal data stream enters the control module through the single-port first-in first-out queue; The control module includes an address control module, a rate control module and a depth control module; The address control module jumps from the first signal data stream to the first target signal data according to the first pointer data; The rate control module adjusts the rate of outputting the first target signal data according to the first rate data; The depth control module adjusts the depth of the single-port first-in first-out queue according to the first depth data.

4. The method of use according to claim 3, characterized in that: The method further comprises: When the protocol changes, the storage module stores a second signal data stream generated in the process of the baseband chip executing the second service based on the second protocol through the second algorithm; The control module determines second target signal data from the second signal data stream according to the second control data of the second service, and outputs the second target signal data to the second service module according to the second control data; the second control data includes second pointer data, second rate data and second depth data.

5. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the method for using the storage device as described in any one of claims 3 to 4 are performed.

6. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for using the storage device as claimed in any one of claims 3 to 4 are executed.

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