Display panel and display device

Abstract

The present application discloses a display panel and a display device, wherein the display panel has a display area and a frame area located outside the display area, and the display panel includes a first substrate and a second substrate; the first substrate includes a first underlayer, a thin film transistor layer, a color resist layer, a pixel electrode layer, a dielectric layer and a metal light shielding layer, wherein the thin film transistor layer is arranged on the side of the first substrate facing the second substrate; the color resist layer is arranged on the side of the thin film transistor layer away from the first substrate; the pixel electrode layer is arranged on the side of the color resist layer away from the first substrate; the dielectric layer is arranged between the pixel electrode layer and the thin film transistor layer, and the dielectric layer is provided with a first via hole, and the pixel electrode layer is electrically connected to the thin film transistor layer through the first via hole; the metal light shielding layer includes a first light shielding portion located in the display area; wherein the first light shielding portion is arranged on the side of the pixel electrode layer away from the color resist layer, and the orthographic projection of the first light shielding portion on the first substrate is arranged separately from the orthographic projection of the first via hole on the first substrate.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display panel and a display device. Background Art

[0002] With the development of 5G communication technology, VR (Virtual Reality) technology is experiencing rapid growth. Array substrates formed by combining LTPO (Low Temperature Polycrystalline Oxide) technology with COA (Color Filter on Array) technology are becoming a key R&D focus for various manufacturers. However, in the actual manufacturing process, the LTPO-COA array substrate architecture poses the risk of electrical contact between the metal BM layer and the pixel electrode vias, resulting in a decrease in panel yield. Summary of the Invention

[0003] Embodiments of the present application provide a display panel and a display device, which can prevent a light shielding layer from short-circuiting due to contact with a pixel electrode via.

[0004] In a first aspect, an embodiment of the present application provides a display panel, the display panel having a display area and a frame area located outside the display area, the display panel including a first substrate and a second substrate disposed opposite to each other, the first substrate including:

[0005] a first substrate;

[0006] a thin film transistor layer, disposed on a side of the first substrate facing the second substrate;

[0007] a color resist layer, the color resist layer being disposed on a side of the thin film transistor layer away from the first substrate;

[0008] a pixel electrode layer, the pixel electrode layer being disposed on a side of the color resist layer away from the first substrate;

[0009] a dielectric layer disposed between the pixel electrode layer and the thin film transistor layer, the dielectric layer being provided with a first via hole, the pixel electrode layer being electrically connected to the thin film transistor layer through the first via hole; and

[0010] a metal light-shielding layer, the metal light-shielding layer comprising a first light-shielding portion located in the display area;

[0011] The first light shielding portion is arranged on a side of the pixel electrode layer away from the color resist layer, and an orthographic projection of the first light shielding portion on the first substrate is separated from an orthographic projection of the first via hole on the first substrate.

[0012] In one embodiment, the first substrate further includes a first insulating layer, and the first insulating layer is disposed between the first light shielding portion and the pixel electrode layer.

[0013] In one embodiment, the first light shielding portion includes a plurality of first sub-portions;

[0014] The first insulating layer is patterned, and the second insulating layer includes a plurality of first insulating blocks, each of which is located between one of the first sub-portions and the pixel electrode layer.

[0015] In one embodiment, the first sub-portion forms a first projection on the first substrate;

[0016] The first insulating block forms a second projection on the first substrate, and the second projection has the same shape as the first projection and completely overlaps with the first projection.

[0017] In one embodiment, the first light shielding portion includes a plurality of first sub-portions, and the first sub-portions form a first projection on the first substrate;

[0018] The second substrate includes a second substrate and a black matrix layer, wherein the black matrix layer is provided on a surface of the second substrate facing the first substrate, the black matrix layer includes a plurality of second light shielding portions, and the second light shielding portions form a third projection on the first substrate;

[0019] The first projections formed by the first sub-portions and the third projections formed by the second light-shielding portions are arranged in a crisscross pattern and define a plurality of pixel areas;

[0020] The color resist layer includes a plurality of color resist blocks, and each color resist block is located in a corresponding pixel area;

[0021] The orthographic projection of the first via hole on the first substrate is located within the range of the third projection.

[0022] In one embodiment, the first substrate further includes a spacer layer, wherein the spacer layer is filled in the first via hole and protrudes from the periphery of the first via hole;

[0023] The display panel further includes a support column, wherein the support column is arranged between the second light shielding portion and the spacer layer;

[0024] Wherein, the pixel electrode layer covers the spacer layer.

[0025] In one embodiment, the first substrate further includes a spacer layer, wherein the spacer layer is filled in the first via hole and protrudes from the periphery of the first via hole;

[0026] The first substrate further includes:

[0027] a first electrode layer, the first electrode layer being disposed on the color resist layer, the first electrode layer being electrically connected to the thin film transistor layer through the first via hole; and

[0028] a second electrode layer, the second electrode layer being disposed on the first electrode layer and covering the spacer layer in the first via hole, the second electrode layer being electrically connected to the first electrode layer;

[0029] Wherein, the first electrode layer and the second electrode layer constitute the pixel electrode layer;

[0030] The metal light shielding layer is disposed on a side of the second electrode layer away from the first electrode layer.

[0031] In one embodiment, the first substrate further includes a second insulating layer and a common electrode layer, wherein the second insulating layer is disposed on a side of the dielectric layer away from the thin film transistor, and the common electrode layer is disposed on a side of the second insulating layer away from the dielectric layer, and forms a storage capacitor between the common electrode layer and the pixel electrode layer;

[0032] The metal light shielding layer further includes a third light shielding portion located in the frame area, and the third light shielding portion is arranged on a side of the dielectric layer away from the thin film transistor;

[0033] Wherein, the second insulating layer covers the pixel electrode layer, the first light shielding portion and the third light shielding portion;

[0034] The third light shielding portion is electrically connected to the common electrode layer through the second via hole, and is electrically connected to the thin film transistor layer through the third via hole.

[0035] In one embodiment, the thin film transistor layer includes a plurality of first thin film transistors and a plurality of second thin film transistors, the plurality of first thin film transistors are arranged in the display area, and the first thin film transistors are configured as oxide thin film transistors, the plurality of second thin film transistors are arranged in the border area, and the second thin film transistors are configured as low-temperature polycrystalline silicon thin film transistors;

[0036] The pixel electrode layer is electrically connected to the first drain electrode of the first thin film transistor through the first via hole;

[0037] The metal light shielding layer further includes a third light shielding portion located in the frame area, and the third light shielding portion is electrically connected to the second drain electrode of the second thin film transistor through a third via hole.

[0038] In a second aspect, an embodiment of the present application further provides a display device comprising the above-mentioned display panel.

[0039] Beneficial effect: In the display panel provided by the present application, the first substrate includes a first underlayer, a thin film transistor layer, a color resist layer, a pixel electrode layer, a dielectric layer and a metal shading layer, and the pixel electrode layer is electrically connected to the thin film transistor layer through a first via; the metal shading layer includes a first shading portion located in the display area; the first shading portion is arranged on a side of the pixel electrode layer away from the color resist layer, and the orthographic projection of the first shading portion on the first substrate is separated from the orthographic projection of the first via on the first substrate, thereby eliminating the risk of short circuit caused by contact between the first shading portion and the first via, thereby improving the product yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0041] Figure 1 A diagram of the film layers of a display panel provided in an embodiment of the present application;

[0042] Figure 2 Projection diagram of the light shielding layer and the black matrix layer provided in the embodiment of the present application;

[0043] Figures 3a to 3e for Figure 1 Schematic diagram of the preparation process of the display panel. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0045] In the description of this application, it should be understood that the terms "upper," "lower," "front," "back," "left," "right," "inner," and "outer," etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this application and should not be construed as limiting this application. Furthermore, unless otherwise expressly provided or limited, a first feature being "above" or "below" a second feature merely indicates that the first feature is at a higher or lower level than the second feature, and does not indicate a direct connection.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only, and features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0047] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "install", "connect" and "connect" should be understood in a broad sense without specifically limiting the connection method. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0048] The disclosure below provides many different embodiments for realizing the different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples, and the purpose is not to limit the present application. In addition, the examples of various specific processes and materials provided in the present application, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0049] First, see Figure 1 and Figure 2The display panel 100 has a display area A and a frame area B located outside the display area A. The display panel 100 includes a first substrate 1 and a second substrate 2 that are arranged opposite to each other. The first substrate 1 includes a first substrate 10, a thin film transistor layer 11, a color resist layer 12, a pixel electrode layer 13, a dielectric layer 19, and a metal light shielding layer 16. The thin film transistor layer 11 is arranged on the side of the first substrate 10 facing the second substrate 2. The color resist layer 12 is arranged on the side of the thin film transistor layer 11 away from the first substrate 10. The pixel electrode layer 13 is arranged on the side of the color resist layer 12 away from the first substrate 10. The dielectric layer 19 is arranged between the pixel electrode layer 13 and the thin film transistor layer 11. The dielectric layer 19 is provided with a first via 191. The pixel electrode layer 13 is electrically connected to the thin film transistor layer 11 through the first via 191. The metal light shielding layer 16 includes a first light shielding portion 161 located in the display area A. The first light shielding portion 161 is arranged on the side of the pixel electrode layer 13 away from the color resist layer 12. The orthographic projection of the first light shielding portion 161 on the first substrate 10 is separated from the orthographic projection of the first via 191 on the first substrate 10.

[0050] In an embodiment of the present application, the thin film transistor layer 11 is formed on a surface of the first substrate 10 facing the second substrate 2, the color resist layer 12 is formed on a side of the thin film transistor layer 11 away from the first substrate 10, and the pixel electrode layer 13 is formed on a side of the color resist layer 12 away from the thin film transistor layer 11. The pixel electrode layer 13 is electrically connected to the thin film transistor layer 11 through a first via 191. The metal light shielding layer 16 includes a first light shielding portion 161 located in the display area A; the first light shielding portion 161 is arranged on a side of the pixel electrode layer 13 away from the color resist layer 12, and the orthographic projection of the first light shielding portion 161 on the first substrate 10 is separated from the orthographic projection of the first via 191 on the first substrate 10. In this way, the risk of short circuit caused by contact between the first light shielding portion 161 and the first via 191 is eliminated, thereby improving the product yield of the display panel 100.

[0051] In one embodiment of the present application, please refer to Figure 1 The display panel 100 includes a first substrate 1 and a second substrate 2 disposed opposite each other, a liquid crystal layer (not shown) disposed between the first substrate 1 and the second substrate 2, and support columns 3 disposed between the first substrate 1 and the second substrate 2. The support columns 3 are used to maintain the cell thickness of the liquid crystal layer. The first substrate 1 can be an array substrate, and the second substrate 2 can be an opposing substrate disposed opposite the array substrate.

[0052] See also Figure 1 In one embodiment, the first substrate 1 further includes a first insulating layer 14, which is disposed between the first light-shielding portion 161 and the pixel electrode layer 13. By providing the first insulating layer 14, the first light-shielding portion 161 and the pixel electrode layer 13 are insulated from each other, thereby preventing the first light-shielding portion 161 and the pixel electrode layer 13 from short-circuiting due to electrical contact.

[0053] In addition, the first substrate 1 also includes a second insulating layer 17 and a common electrode layer 15. The second insulating layer 17 is arranged on a side of the dielectric layer 19 away from the thin film transistor layer 11. The common electrode layer 15 is arranged on a side of the second insulating layer 17 away from the dielectric layer 19 and forms a storage capacitor between the common electrode layer 15 and the pixel electrode layer 13.

[0054] In one embodiment, the first light shielding portion 161 includes a plurality of first sub-portions 1611. The first insulating layer 14 can be provided as a whole layer or in a patterned manner. In one embodiment, the first insulating layer 14 is provided in a patterned manner and includes a plurality of first insulating blocks 141. Each first insulating block 141 is located between a first sub-portion 1611 and the pixel electrode layer 13.

[0055] The first sub-portion 1611 forms a first projection on the first substrate 10 ; the first insulating block 141 forms a second projection on the first substrate 10 , and the second projection has the same shape as the first projection and completely overlaps with it.

[0056] At the same time, the orthographic projection of the common electrode layer 15 on the first substrate 10 and the second projection are staggered.

[0057] That is to say, only the first insulating layer 14 below the first sub-portion 1611 is retained, and the rest of the first insulating layer 14 is completely etched; on the one hand, retaining the first insulating layer 14 below the first sub-portion 1611 can insulate the first sub-portion 1611 from the pixel electrode layer 13; on the other hand, completely etching the rest of the first insulating layer 14 can ensure that the thickness uniformity of the storage capacitor layer between the pixel electrode layer 13 and the common electrode layer 15 is better.

[0058] In the examples of this application, please refer to Figure 1 and Figure 2The black matrix layer 22 includes a plurality of second light-shielding portions 221, which are arranged side by side and spaced apart in the first direction F1, and each second light-shielding portion 221 extends along the second direction F2; the first light-shielding portion 161 includes a plurality of first sub-portions 1611, which are arranged side by side and spaced apart in the second direction F2, and each first sub-portion 1611 extends along the first direction F1; that is, the plurality of first projections formed by the plurality of first sub-portions 1611 and the plurality of third projections formed by the plurality of second light-shielding portions 221 are arranged in a criss-cross pattern and define a plurality of pixel areas C; the color resist layer 12 includes a plurality of color resist blocks 121, and each color resist block 121 is located in a corresponding pixel area C.

[0059] The first direction F1 and the second direction F2 are arranged to intersect each other; specifically, in one embodiment, the first direction F1 and the second direction F2 are perpendicular to each other.

[0060] It can be understood that since the first via 191 is provided on the dielectric layer 19, the pixel electrode layer 13 is electrically connected to the thin film transistor layer 11 through the first via 191; therefore, when the patterned metal shading layer 16 is produced on the side of the pixel electrode layer 13 away from the color resist layer 12, the photoresist thickness on the metal shading layer 16 is different inside and outside the first via 191, resulting in a large difference in exposure of the metal shading layer 16 inside and outside the first via 191, which in turn makes the exposure process control of the metal shading layer 16 more difficult.

[0061] In one embodiment of the present application, the orthographic projection of the first via hole 191 on the first substrate 10 is located within the orthographic projection of the second light shielding portion 221 on the first substrate 10. In other words, the orthographic projection of the first via hole 191 on the first substrate 10 is located within the range of the third projection. The first substrate 1 further includes a spacer layer 192, which fills the first via hole 191 and protrudes from the periphery of the first via hole 191; the pixel electrode layer 13 covers the spacer layer 192.

[0062] In this way, when the metal light-shielding layer 16 is produced on the side of the pixel electrode layer 13 away from the color resist layer 12, since the first via hole 191 is filled with the spacer layer 192 and the spacer layer 192 is protruding from the periphery of the first via hole 191 to improve the film morphology, the production surface of the metal light-shielding layer 16 is flat, so that the exposure of the patterned metal light-shielding layer 16 is the same at all places, thereby reducing the difficulty of producing the metal light-shielding layer 16.

[0063] As mentioned above, the orthographic projection of the first via 191 on the first substrate 10 is located within the orthographic projection range of the second light-shielding portion 221 on the first substrate 10. It can be seen that the spacer layer 192 forms a fourth projection on the first substrate 10, and the fourth projection is located within the range of the third projection formed by the second light-shielding portion 221; the display panel 100 also includes a support column 3, which is arranged between the second light-shielding portion 221 and the spacer layer 192; that is, the support column 3 corresponds to the position of the black matrix layer 22, and since the spacer layer 192 is protruding from the periphery of the first via hole 191, the film layer around the spacer layer 192 is further away from the support column 3 in the thickness direction of the first substrate 1, thereby avoiding the support column 3 from scratching the film layer around the spacer layer 192 due to movement, thereby ensuring the yield and display effect of the display panel 100.

[0064] This application does not impose any specific restrictions on the structure of the spacer layer 192. In some embodiments, the spacer layer 192 fills the first via 191 to improve the membrane morphology, and the filled spacer layer 192 simultaneously forms a boss protruding from the surface of the spacer layer 192. In other embodiments, the spacer layer 192 includes a first spacer portion 1921 and a second spacer portion 1922, wherein the first spacer portion 1921 fills the first via 191 and the second spacer portion 1922 is disposed above the first spacer portion 1921 and protrudes from the periphery of the first via 191.

[0065] In one embodiment of the present application, further reference is made to Figure 1 The first substrate 1 also includes a first electrode layer 131 and a second electrode layer 132; the first electrode layer 131 is arranged on the color resist layer 12, and the first electrode layer 131 is electrically connected to the thin film transistor layer 11 through the first via 191; the second electrode layer 132 is arranged on the first electrode layer 131 and covers the spacer layer 192 in the first via 191, and the second electrode layer 132 is electrically connected to the first electrode layer 131; wherein, the first electrode layer 131 and the second electrode layer 132 constitute the pixel electrode layer 13; the metal shading layer 16 is arranged on the side of the second electrode layer 132 away from the first electrode layer 131.

[0066] Continuing from the above, in an embodiment of the present application, the metal light-shielding layer 16 also includes a third light-shielding portion 162 located in the border area B, and the third light-shielding portion 162 is located on the side of the dielectric layer 19 away from the thin-film transistor layer 11; the second insulating layer 17 covers the pixel electrode layer 13, the first light-shielding portion 161 and the third light-shielding portion 162; the third light-shielding portion 162 is electrically connected to the common electrode layer 15 through a second via hole, and is electrically connected to the thin-film transistor layer 11 through a third via hole.

[0067] That is to say, the metal shading layer 16 also includes a third shading portion 162 arranged in the border area B, and by changing the line in the border area B to input an electrical signal to the third shading portion 162, and then loading an electrical signal to the first shading portion 161, not only can the static electricity generated in the first substrate 1 be released, but also a stable electrical signal can be loaded to the first shading portion 161 to avoid the first shading portion 161 interfering with the signal transmission in the first substrate 1 due to large fluctuations in the electrical signal.

[0068] Specifically, the voltage signal loaded in the first light shielding portion 161 is greater than or equal to −500 mA and less than or equal to 500 mA; and the potential of the third light shielding portion 162 is the same as that of the common electrode layer 15 .

[0069] In one embodiment, the first substrate 1 further includes a planar layer 18, which is arranged on the thin film transistor layer 11 and covers the color resist layer 12, and the dielectric layer 19 is arranged on a side of the planar layer 18 away from the thin film transistor layer 11; a first through hole is provided on the planar layer 18 at a position corresponding to the first via hole 191; the third light shielding portion 162 is located on a surface of the dielectric layer 19 away from the planar layer 18; the pixel electrode layer 13 is located on a surface of the dielectric layer 19 away from the planar layer 18, and is electrically connected to the thin film transistor layer 11 through the first via hole 191 and the first through hole; the first light shielding portion 161 is arranged on a side of the pixel electrode layer 13 away from the dielectric layer 19; the third light shielding portion 162 is electrically connected to the common electrode layer 15 through the second via hole, and is electrically connected to the thin film transistor layer 11 through the third via hole.

[0070] Furthermore, the second insulating layer 17 covers the pixel electrode layer 13, the first light shielding portion 161, and the third light shielding portion 162. The first insulating layer 14 is patterned and further includes a plurality of second insulating blocks 142 located in the border region B. Each second insulating block 142 is located between one of the third light shielding portions 162 and the dielectric layer 19.

[0071] Please see further Figure 1 The thin film transistor layer 11 includes a plurality of thin film transistors disposed on a first substrate 10, and a plurality of interlayer insulating layers covering the plurality of thin film transistors. The plurality of thin film transistors include a plurality of first thin film transistors 111 located in the display area A, and a plurality of second thin film transistors 112 located in the border area B. The plurality of interlayer insulating layers include a first interlayer insulating layer 113, a second interlayer insulating layer 114, a third interlayer insulating layer 115, a fourth interlayer insulating layer 116, a fifth interlayer insulating layer 117, and a sixth interlayer insulating layer 118, which are sequentially disposed on the first substrate 10.

[0072] It should be noted that the display panel 100 provided in the embodiment of the present application is suitable for an LTPO (English full name: Low Temperature Poly-Oxide, Chinese abbreviation: low-temperature polycrystalline oxide) display panel 100; the first thin film transistor 111121 is set as an oxide thin film transistor, and the second thin film transistor 112122 is set as a low-temperature polycrystalline silicon thin film transistor.

[0073] In one embodiment of the present application, the first thin film transistor 111 includes a first gate electrode arranged on the second interlayer insulating layer 114 and covered by the third interlayer insulating layer 115, a first active layer arranged on the third interlayer insulating layer 115 and covered by the fourth interlayer insulating layer 116, a second gate electrode arranged on the fourth interlayer insulating layer 116 and covered by the fifth interlayer insulating layer 117, a first source electrode arranged on the fifth interlayer insulating layer 117 and covered by the sixth interlayer insulating layer 118, and a first drain electrode, wherein the first gate electrode and the second gate electrode are respectively located on the upper and lower sides of the first active layer and are arranged corresponding to the channel region of the first active layer, and the first source electrode and the first drain electrode are respectively connected to the two sides of the first active layer, and the connection positions are respectively located on the opposite sides of the channel region.

[0074] Specifically, one end of the first drain electrode of the first thin film transistor 111 passes through the sixth interlayer insulating layer 118, the fifth interlayer insulating layer 117 and the fourth interlayer insulating layer 116, and is connected to the first active layer. The other end of the first drain electrode extends to the side surface of the sixth interlayer insulating layer 118 away from the fifth interlayer insulating layer 117, and is exposed from the first via hole 191. The first electrode layer 131 is electrically connected to the first drain electrode through the first via hole 191, and then the spacer layer 192 is filled in the first via hole 191.

[0075] At the same time, the color resist block 121 is also filled in the contact hole between the first drain electrode and the first active layer to avoid a concave film morphology at the contact hole.

[0076] Based on the structure of the first substrate 1 described above, the present application also provides a method for manufacturing the first substrate 1 .

[0077] See also Figure 3a A first substrate 10 is provided, and the thin film transistor layer 11 is formed on the first substrate 10; a seventh interlayer insulating layer 119 is formed on the thin film transistor layer 11; the color resist layer 12 is formed on the seventh interlayer insulating layer 119, and the color resist layer 12 includes a plurality of color resist blocks 121 distributed in an array; the first planarizing layer 18 is formed on the seventh interlayer insulating layer 119, and the first planarizing layer 18 covers the color resist layer 12; the dielectric layer 19 is formed on the first planarizing layer 18; and the first electrode layer 12 is provided on the dielectric layer 19. 31, the first electrode layer 131 is electrically connected to the thin film transistor layer 11 through the first via hole 191; the first spacer portion 1921 is filled in the first via hole 191, and a second spacer portion 1922 is formed on the first spacer portion 1921, and the second spacer portion 1922 is arranged beyond the periphery of the first via hole 191; the second electrode layer 132 is formed on the first electrode layer 131, and the second electrode layer 132 covers the second spacer portion 1922; the first insulating layer 14 is formed on the seventh interlayer insulating layer 119;

[0078] See also Figure 3b , forming the metal light shielding layer 16 on the first insulating layer 14;

[0079] See also Figure 3c , forming a photoresist layer 4 on the metal light-shielding layer 16, and exposing and developing the photoresist layer 4 to form a patterned photoresist layer 4;

[0080] See also Figure 3d , using the patterned photoresist layer 4 as a mask to etch the metal light shielding layer 16 and the first insulating layer 14 to form the first light shielding portion 161 and the third light shielding portion 162;

[0081] See also Figure 3e A second insulating layer 17 is formed on the seventh interlayer insulating layer 119 , and the second insulating layer 17 covers the first electrode layer 131 , the second electrode layer 132 and the metal light shielding layer 16 .

[0082] Continuing from the above, in the embodiment of the present application, since the first via 191 is filled with the spacer layer 192 to improve the film morphology, the production surfaces of the first insulating layer 14 and the metal light-shielding layer 16 are flat, so that the exposure of the metal light-shielding layer 16 is the same at all locations, thereby reducing the difficulty of producing the metal light-shielding layer 16; and the metal light-shielding layer 16 is produced on the second electrode layer 132, and the orthographic projection of the first light-shielding portion 161 on the first substrate 10 is separated from the orthographic projection of the first via 191 on the first substrate 10; therefore, the risk of short circuit caused by contact between the first light-shielding portion 161 and the first via 191 is eliminated, thereby improving the product yield of the display panel 100.

[0083] In a second aspect, embodiments of the present application further provide a display device. The display device includes a display panel 100. It should be noted that the display panel 100 is configured as the display panel 100 described above. That is, the display panel 100 includes all the technical features of the display panel 100 described above. The display device includes all embodiments of the display panel 100 described above and thus possesses all the technical effects of the above embodiments, which will not be detailed here.

[0084] In one embodiment, the display device may further include a backlight module, and the display panel is disposed on a light-emitting side of the backlight module.

[0085] In one embodiment, the display device may include a mobile phone, a television, a tablet, a computer, or a VR device.

[0086] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area and a frame area located outside the display area. The display panel includes a first substrate and a second substrate arranged opposite to each other. The first substrate includes: a first substrate; a thin film transistor layer, disposed on a side of the first substrate facing the second substrate; a color resist layer, the color resist layer being disposed on a side of the thin film transistor layer away from the first substrate; a pixel electrode layer, the pixel electrode layer being disposed on a side of the color resist layer away from the first substrate; a dielectric layer disposed between the pixel electrode layer and the thin film transistor layer, the dielectric layer being provided with a first via hole, the pixel electrode layer being electrically connected to the thin film transistor layer through the first via hole; and a metal light-shielding layer, the metal light-shielding layer comprising a first light-shielding portion located in the display area, the first light-shielding portion comprising a plurality of first sub-portions; a first insulating layer, the first insulating layer being disposed between the first light-shielding portion and the pixel electrode layer, the first insulating layer being patterned and comprising a plurality of first insulating blocks, each of the first insulating blocks being located between one of the first sub-portions and the pixel electrode layer; The first light shielding portion is arranged on a side of the pixel electrode layer away from the color resist layer, and an orthographic projection of the first light shielding portion on the first substrate is separated from an orthographic projection of the first via hole on the first substrate.

2. The display panel according to claim 1, wherein The first sub-section forms a first projection on the first substrate; The first insulating block forms a second projection on the first substrate, and the second projection has the same shape as the first projection and completely overlaps with the first projection.

3. The display panel according to claim 1, wherein The first light shielding portion includes a plurality of first sub-portions, and the first sub-portions form a first projection on the first substrate; The second substrate includes a second substrate and a black matrix layer, wherein the black matrix layer is provided on a surface of the second substrate facing the first substrate, the black matrix layer includes a plurality of second light shielding portions, and the second light shielding portions form a third projection on the first substrate; The first projections formed by the first sub-portions and the third projections formed by the second light-shielding portions are arranged in a crisscross pattern and define a plurality of pixel areas; The color resist layer includes a plurality of color resist blocks, and each color resist block is located in a corresponding pixel area; The orthographic projection of the first via hole on the first substrate is located within the range of the third projection.

4. The display panel according to claim 3, wherein: The first substrate further includes a spacer layer, which is filled in the first via hole and protrudes from the periphery of the first via hole; The display panel further includes a support column, wherein the support column is arranged between the second light shielding portion and the spacer layer; Wherein, the pixel electrode layer covers the spacer layer.

5. The display panel according to claim 1, wherein The first substrate further includes a spacer layer, which is filled in the first via hole and protrudes from the periphery of the first via hole; The first substrate further includes: a first electrode layer, the first electrode layer being disposed on the color resist layer, the first electrode layer being electrically connected to the thin film transistor layer through the first via hole; and a second electrode layer, the second electrode layer being disposed on the first electrode layer and covering the spacer layer in the first via hole, the second electrode layer being electrically connected to the first electrode layer; Wherein, the first electrode layer and the second electrode layer constitute the pixel electrode layer; The metal light shielding layer is disposed on a side of the second electrode layer away from the first electrode layer.

6. The display panel according to claim 1, wherein: The first substrate further includes a second insulating layer and a common electrode layer, wherein the second insulating layer is disposed on a side of the dielectric layer away from the thin film transistor, and the common electrode layer is disposed on a side of the second insulating layer away from the dielectric layer, and forms a storage capacitor between the common electrode layer and the pixel electrode layer; The metal light shielding layer further includes a third light shielding portion located in the frame area, and the third light shielding portion is arranged on a side of the dielectric layer away from the thin film transistor; Wherein, the second insulating layer covers the pixel electrode layer, the first light shielding portion and the third light shielding portion; The third light shielding portion is electrically connected to the common electrode layer through the second via hole, and is electrically connected to the thin film transistor layer through the third via hole.

7. The display panel according to claim 1, wherein: The thin film transistor layer includes a plurality of first thin film transistors and a plurality of second thin film transistors, wherein the plurality of first thin film transistors are arranged in the display area and are configured as oxide thin film transistors, and the plurality of second thin film transistors are arranged in the frame area and are configured as low-temperature polysilicon thin film transistors; The pixel electrode layer is electrically connected to the first drain electrode of the first thin film transistor through the first via hole; The metal light shielding layer further includes a third light shielding portion located in the frame area, and the third light shielding portion is electrically connected to the second drain electrode of the second thin film transistor through a third via hole.

8. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 7.

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