Driver board, display panel, and display device

Abstract

Embodiments of the present invention provide a driver board, a display panel, and a display device. The driver board includes multiple pixel regions; the pixel regions include pixel circuits, a first power supply structure, and a second power supply structure; the first power supply structure is used to provide a first power supply voltage, and the second power supply structure is used to provide a second power supply voltage; the driver board includes a substrate, and the pixel circuits, the first power supply structure, and the second power supply structure are located on the same side of the substrate; wherein at least one of the first power supply structure and the second power supply structure includes a block structure, and at least one inorganic layer is provided on a side of the block structure away from the substrate; the block structure includes a first block structure, and the first block structure includes at least one first opening. The present invention can reduce the probability of display anomalies.

Description

[0001] This application is a divisional application of the patent application submitted to the China Patent Office on June 30, 2022, with application number 202210767023.X and application name "Drive board, display panel and display device". Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a driving board, a display panel and a display device. Background Art

[0003] LEDs, or light-emitting diodes, efficiently convert electrical energy into light and are widely used in modern lighting, display, and medical devices. In the display field, micro-LEDs and mini-LEDs can be used directly as sub-pixels in displays or as backlights for LCDs (Liquid Crystal Displays). Micro-LEDs are micron-sized LEDs, while mini-LEDs have chip sizes between 50 and 200 μm. However, current LED display products suffer from display anomalies. Summary of the Invention

[0004] Embodiments of the present invention provide a driving board, a display panel, and a display device to solve the problem of abnormal display in prior art products.

[0005] In a first aspect, an embodiment of the present invention provides a driving board, the driving board including a plurality of pixel areas; the pixel areas including pixel circuits, a first power supply structure and a second power supply structure; the first power supply structure is used to provide a first power supply voltage, and the second power supply structure is used to provide a second power supply voltage;

[0006] The driving board includes a substrate, and the pixel circuit, the first power supply structure, and the second power supply structure are located on the same side of the substrate; wherein,

[0007] At least one of the first power structure and the second power structure comprises a block structure, wherein at least one inorganic layer is provided on a side of the block structure away from the substrate;

[0008] The block structure includes a first block structure, and the first block structure includes at least one first opening.

[0009] In a second aspect, based on the same inventive concept, an embodiment of the present invention provides a display panel, including the driving board provided by any embodiment of the present invention.

[0010] In a third aspect, based on the same inventive concept, an embodiment of the present invention provides a display device, including the display panel provided by any embodiment of the present invention.

[0011] The driver board, display panel, and display device provided by the embodiments of the present invention have the following beneficial effects: A first opening is used to partially separate at least one large-area power supply structure to form smaller power supply units that are still electrically connected to each other. The presence of the first opening reduces the cross-sectional area for charge flow within the power supply structure, limiting the flow of charge between the small-area power supply units separated by the first opening. This is equivalent to dispersing the charge on the power supply structure, thereby reducing the amount of charge accumulated in the small-area power supply units, and thus reducing the amount of charge accumulated locally in the large-area power supply structure. During driver board manufacturing, after the large-area power supply structure is processed, the module is placed in a CVD machine to form an inorganic insulating layer. The first opening breaks the large-area power supply structure into multiple small-area power supply units that are still electrically connected to each other, reducing the amount of charge accumulated in the small-area power supply units. The smaller the charge amount, the lower the risk of electrostatic discharge. This reduces the risk of abnormal discharge between each small-area power supply unit and the CVD machine, and thus reduces the risk of abnormal discharge between the large-area power supply structure and the CVD machine, thereby improving process yield and reducing costs. In addition, an inorganic layer is set on the large-area power supply structure, and the excellent water and oxygen barrier ability of the inorganic material is used to effectively protect the large-area power supply structure, prevent the large-area power supply structure from being corroded, improve the performance reliability of the driver board, and reduce the probability of display abnormalities. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0013] Figure 1 A schematic diagram of a pixel circuit in a driver board provided for the implementation of the present invention;

[0014] Figure 2 A schematic diagram of a pixel circuit in another driving board provided by an embodiment of the present invention;

[0015] Figure 3 A partial top view of a driving plate provided by an embodiment of the present invention;

[0016] Figure 4 A schematic cross-sectional view of a driving plate provided by an embodiment of the present invention;

[0017] Figure 5 A partial schematic diagram of another driving board provided by an embodiment of the present invention;

[0018] Figure 6 A schematic diagram of the membrane structure of another driving plate provided in an embodiment of the present invention;

[0019] Figure 7 A schematic diagram of another driving board provided by an embodiment of the present invention;

[0020] Figure 8 for Figure 7 A schematic diagram of a cross section at the mid-tangent line AA';

[0021] Figure 9 for Figure 7 A schematic cross-sectional view at the midline BB';

[0022] Figure 10 A schematic diagram of a film layer of another driving plate provided by an embodiment of the present invention;

[0023] Figure 11 A schematic diagram of a film layer of another driving plate provided by an embodiment of the present invention;

[0024] Figure 12 A schematic diagram of a film layer of another driving plate provided by an embodiment of the present invention;

[0025] Figure 13 A schematic diagram of another driving board provided by an embodiment of the present invention;

[0026] Figure 14 A schematic diagram of a film layer of another driving plate provided by an embodiment of the present invention;

[0027] Figure 15 A schematic diagram of another driving board provided by an embodiment of the present invention;

[0028] Figure 16 for Figure 15 Schematic diagram of disassembly of storage capacitor;

[0029] Figure 17 for Figure 15 A schematic cross-sectional view at the mid-tangent line CC';

[0030] Figure 18 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0031] Figure 19 for Figure 18 An enlarged schematic diagram of the Q9 position in the middle area;

[0032] Figure 20 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0033] Figure 21 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0035] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "an", "the" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0036] The inventors analyzed the causes of display anomalies in existing LED products. LED display products are equipped with a driver board, which is generally a structure with alternating metal layers and insulating layers. The driver board includes pixel circuits that drive the LEDs to emit light. Research has found that the power supply structure in the driver board suffers from electrochemical corrosion. Electrochemical corrosion causes the power supply structure to fail functionally. For example, the positive and negative power supply structures in the driver board short-circuit due to electrochemical corrosion, thereby causing display anomalies. The inventors further analyzed the causes of electrochemical corrosion in the power supply structure and found that the organic layer covering the power supply structure has poor density, making the power supply structure susceptible to corrosion by water and oxygen. In order to improve the corrosion resistance of the power supply structure, the inventors considered forming an inorganic insulating layer on top of the power supply structure, using the high density of the inorganic insulating layer to prevent water and oxygen from corroding the power supply structure. However, during the manufacturing process, it was found that abnormal discharge occurred when the driver board was placed in a CVD (Chemical Vapor Deposition) machine to form the inorganic layer. The abnormal discharge caused problems such as driver board fragmentation, film damage, and equipment damage. The inventors further analyzed the causes of abnormal discharge and found that when the power supply structure is a large-area metal structure, for example, when the combined area of ​​the positive and negative power supply structures accounts for 85% of the total area of ​​the driver board, abnormal discharge can occur in the driver board and the CVD machine during the inorganic layer fabrication process after the power supply structure process. The inventors analyzed that the driver board generates electrostatic charge during the process, and this electrostatic charge accumulates in the metal structure. After the power supply structure process, when the driver board is placed in the CVD machine to fabricate the inorganic layer, due to the electrostatic charge on the power supply structure, when the amount of charge accumulated on the power supply structure is large enough, a potential difference exists between the power supply structure and the electrodes in the CVD machine, resulting in electrostatic discharge. This can cause damage to the electrodes in the CVD machine and the driver board can also break due to electrostatic discharge. The design of a large-area metal structure can reduce the resistance of the power supply structure, reduce voltage drop, and improve the uniformity of the power supply voltage. However, the large-area structure also causes abnormal discharge when entering the CVD machine, thereby limiting the fabrication of the inorganic layer after the power supply structure. Therefore, how to make an inorganic layer behind a large area of ​​metal structure to effectively protect the metal structure to solve display anomalies is an urgent problem to be solved.

[0037] In order to solve the problems existing in the prior art, an embodiment of the present invention provides a driving board, in which openings are made on a large-area metal structure, so as to partially isolate the large-area metal structure by using the openings. For example, the metal structure can be at least one power supply structure, and the openings are used to partially isolate at least one large-area power supply structure to form power supply units with smaller areas that are still electrically connected to each other. Since each power supply unit is smaller in size, the amount of charge accumulated by the smaller power supply unit is also smaller. This can reduce the risk of abnormal discharge between the power supply structure and the CVD machine, and can produce an inorganic insulating layer after the process of the large-area power supply structure, thereby improving the protection performance of the power supply structure, preventing metal corrosion, and solving the problem of display abnormalities.

[0038] The driver board provided in an embodiment of the present invention includes a plurality of pixel areas arranged in an array, wherein the pixel areas include pixel circuits and power supply structures. In some embodiments, a light-emitting device is fixed in the pixel area of ​​the driver board, and the driver board can serve as a backlight module to provide a light source for a liquid crystal display panel. In other embodiments, a light-emitting device is fixed in the pixel area of ​​the driver board, which can serve as a display panel, wherein each pixel area corresponds to a light-emitting pixel in the display panel. The light-emitting device in the embodiment of the present invention can be a Micro-LED or a mini LED.

[0039] Figure 1 A schematic diagram of a pixel circuit in a driver board provided for the implementation of the present invention. Figure 1 As shown, the pixel circuit includes a driver module 0010 and a data writing module 0020. The data writing module 0020 is used to provide a data signal to the pixel circuit, and the driver module 0010 is used to provide a driving current to the light-emitting device P. The driver module 0010 includes a driver transistor Tm, the data writing module 0020 includes a switching transistor T7, and the pixel circuit also includes a storage capacitor Cst. The gate of the switching transistor T7 is coupled to the scan line S, the first electrode of the switching transistor T7 is coupled to the data line Vdata, and the second electrode of the switching transistor T7 is coupled to the gate of the driver transistor Tm. One plate of the storage capacitor Cst is coupled to the positive power supply structure Pvdd, and the other plate of the storage capacitor Cst is coupled to the gate of the driver transistor Tm. The first electrode of the driver transistor Tm is coupled to the positive power supply structure Pvdd, the second electrode of the driver transistor Tm is coupled to the first electrode of the light-emitting device P, and the second electrode of the light-emitting device P is coupled to the negative power supply structure Pvee. The positive power supply structure Pvdd provides a positive power supply voltage, and the negative power supply structure Pvee provides a negative power supply voltage. Figure 1 The driving transistor Tm and the switch transistor T7 are both illustrated as n-type transistors. In another embodiment, each transistor in the pixel circuit is a p-type transistor, which is not illustrated here.

[0040] In another embodiment, Figure 2 A schematic diagram of a pixel circuit in another driving board provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the pixel circuit includes a driver module 0010, a data write module 0020, a threshold compensation module 0030, a light emitting control module 0040, a gate reset module 0050, an electrode reset module 0060, and a storage capacitor Cst. The control terminal of the driver module 0010 is coupled to a first node N1, a first terminal of the driver module 0010 is coupled to a second node N2, and a second terminal of the driver module 0010 is coupled to a third node N3. The data write module 0020 is coupled to the second node N2, and the threshold compensation module 0030 is connected in series between the first node N1 and the third node N3. The light emitting control module 0040 is connected in series with the driver module 0010 and the light emitting device P. The gate reset module 0050 is coupled to the first node N1, and the electrode reset module 0060 is coupled to the first electrode of the light emitting device P and is coupled to a fourth node. The driving module 0010 includes a driving transistor Tm, the gate reset module 0500 includes a gate reset transistor T1, the electrode reset module 0060 includes an electrode reset transistor T2, the data write module 0020 includes a data write transistor T3, the threshold compensation module 0030 includes a threshold compensation transistor T4, and the light control module 0040 includes a first light control transistor T5 and a second light control transistor T6. A first electrode of the gate reset transistor T1 is coupled to the reset line Ref, and a second electrode of the gate reset transistor T1 is coupled to a first node N1. The gate of the driving transistor Tm is coupled to the first node N1, a first electrode of the driving transistor Tm is coupled to a second node N2, and a second electrode of the driving transistor Tm is coupled to a third node N3. The driving transistor Tm is connected in series between the first light control transistor T5 and the second light control transistor T6. A first electrode of the data write transistor T3 is coupled to the data line Vdata, and a second electrode of the data write transistor T3 is coupled to a second node N2. The threshold compensation transistor T4 is connected in series between the first node N1 and the third node N3. The first plate of the storage capacitor Cst and one electrode of the first emission control transistor T5 are both coupled to the positive power supply structure Pvdd. The first electrode of the electrode reset transistor T2 is coupled to the reset line Ref. The second electrode of the electrode reset transistor T2 and the first electrode of the light-emitting device P are coupled to the fourth node N4. The second electrode of the light-emitting device P is coupled to the negative power supply structure Pvee. The gate of the data write transistor T3 and the gate of the threshold compensation transistor T4 are coupled to the first scan line Sc1. The gate of the gate reset transistor T1 and the gate of the electrode reset transistor T2 are coupled to the second scan line Sc2. The gate of the first emission control transistor T5 and the gate of the second emission control transistor T6 are coupled to the emission control line E. Figure 2 The driving transistor Tm and the switch transistor T7 are both illustrated as p-type transistors. In another embodiment, each transistor in the pixel circuit is an n-type transistor, which is not illustrated in the figure here.

[0041] In another embodiment, the pixel circuit includes a driving module 0010, a data writing module 0020, a light emitting control module 0040, a gate reset module 0050, an electrode reset module 0060 and a storage capacitor Cst. However, the pixel circuit does not include Figure 2 In another embodiment, the pixel circuit includes a driving module 0010, a data writing module 0020, a threshold compensation module 0030, a light emitting control module 0040, a gate reset module 0050 and a storage capacitor Cst. However, the pixel circuit does not include Figure 2 The electrode reset module 0060 is shown in FIG.

[0042] The pixel circuit in the above embodiment is only for schematic representation and is not intended to limit the present invention. The pixel circuit in the driver board provided in the embodiment of the present invention can be any one of the prior art. In order to realize the driving of the light emitting device P to emit light, a power supply structure is provided in the driver board, which includes Figure 1 and Figure 2 The positive power supply structure Pvdd and the negative power supply structure Pvee are shown in the figure. In the prior art, the positive power supply structure Pvdd and the negative power supply structure Pvee in the display area are both metal lines, that is, the positive power supply structure Pvdd is a linear metal, and the shape of the positive power supply structure Pvdd is similar to the shape of the data line in the driver board. The width of the positive power supply structure Pvdd in the direction perpendicular to its extension is about 2 to 5 μm, which can also be said to be the line width of the positive power supply structure Pvdd is about 2 to 5 μm; similarly, the structure of the negative power supply structure Pvee is similar to that of the positive power supply structure Pvdd, and the line width of the negative power supply structure Pvee is about 2 to 5 μm. Under normal circumstances, the positive power supply structure Pvdd and the negative power supply structure Pvee both transmit constant voltage signals, that is, the positive power supply structures Pvdd at corresponding positions of different pixel areas on the entire surface of the driver board are electrically connected, and similarly, the negative power supply structures Pvee at corresponding positions of different pixel areas are also electrically connected.

[0043] In order to improve the uniformity of the in-plane power supply voltage in the embodiment of the present invention, at least one of the positive power supply structure Pvdd and the negative power supply structure Pvee is set to a large-area structure. Among them, the large-area structure and the linear metal are two different concepts, and the two can be understood by comparison. Generally, the metal lines in the driving board, such as data lines, scan lines, etc., are all linear metals. A large number of pixel circuits are arranged in the driving board. While meeting the process capabilities and the functions of the metal lines themselves, the line width of the linear metal is generally about 2 to 5 μm. In other words, the width of conventional linear metals in the direction perpendicular to their extension is generally 2 to 5 μm. The large-area structure defined in the embodiment of the present invention is much wider than the line width of the linear metal in the direction perpendicular to its extension. The large-area structure will also be explained in the relevant figures below.

[0044] Figure 3 A schematic partial top view of a driving plate provided in an embodiment of the present invention.

[0045] like Figure 3 As shown, the pixel region Q includes a pixel circuit 10, a first power supply structure 21, and a second power supply structure 22. The first power supply structure 21 is used to provide a first power supply voltage, and the second power supply structure 22 is used to provide a second power supply voltage. One of the first power supply structure 21 and the second power supply structure 22 is a positive power supply structure Pvdd, and the other is a negative power supply structure Pvee. Figure 3 The diagram shows that both the first power structure 21 and the second power structure 22 include a block structure 30. In this embodiment of the present invention, the block structure 30 is a large-area structure (i.e., a block shape) in a top view, rather than a conventional linear metal structure. The first and second power structures 21 and 22 each provide corresponding constant voltage signals. The block shape reduces resistance and thus power consumption.

[0046] It should be clarified that the first power structure 21 and the second power structure 22 defined in the embodiment of the present invention are structures within the pixel area Q, and are definitions of the power structures at their locations from the perspective of a single pixel area Q. Within the pixel area Q, the first power structure 21 and the second power structure 22 both include a block structure 30, which is significantly different from a conventional linear metal structure within the pixel area Q. Conventional linear metal structures are fine metal wires, and their line widths are generally around 2 to 5 μm, while in the embodiment of the present invention, the width of the block structure 30 in any direction within its plane is greater than 5 μm. Moreover, within the pixel area Q, the area of ​​the block structure 30 is much larger than the area of ​​a single linear metal structure.

[0047] In addition, from the perspective of the entire driving board, the first power supply structure 21 in each pixel region Q has the same potential, and the second power supply structure 22 in each pixel region Q also has the same potential. Figure 3Two pixel areas Q arranged in the second direction y are shown in the figure. It can be seen that the two first power supply structures 21 in the two pixel areas Q are interconnected, and there is no obvious boundary between the interconnected first power supply structures 21. The multiple first power supply structures 21 corresponding to the multiple pixel areas Q along the second direction y can be an integrated structure. It can be considered that the multiple first power supply structures 21 corresponding to the multiple pixel areas Q along the second direction y are interconnected to form a first common power supply, and from the perspective of the driving plate as a whole, the shape of the first common power supply is strip-shaped. Compared with the metal wires in the pixel circuit in the driving plate, the area of ​​the first common power supply is much larger than the area of ​​a single metal wire. The first common power supply can also be considered as a large-area block structure. Similarly, Figure 3 The two second power supply structures 22 within the two pixel regions Q are interconnected, and the multiple first power supply structures 21 within the corresponding multiple pixel regions Q along the second direction y are interconnected to form a second common power supply. From the perspective of the entire driver board, the second common power supply is strip-shaped, and the second common power supply can also be considered a large-area block structure. In some embodiments, one of the first power supply structure 21 and the second power supply structure 22 can be configured as a block structure, and the other can be a conventional linear metal structure. This is not illustrated in the figures here. Figure 3 The outline of the block structure 30 is only schematically shown. Figure 3 Deforming only a part of the outline based on the schematic shape, such as forming a block structure 30 with a non-linear outline, also falls within the scope of protection of the present invention.

[0048] Figure 3 In the embodiment, the block structure 30 includes only the first block structure for illustration. In some embodiments described below, the block structure 30 includes the first block structure and the second block structure.

[0049] like Figure 3 As shown, the block structure 30 includes a first block structure 31. In this embodiment, the first block structure 31 is the block structure 30. The first block structure 31 includes at least one first opening K1. The first opening K1 penetrates the film layer where the first block structure 31 is located in a direction perpendicular to the substrate. Figure 3 The first block structure 31 includes a plurality of first openings K1. The embodiment of the present invention does not limit the shape, number, and arrangement of the first openings K1. The first openings K1 can be in any shape such as circular, rectangular, triangular, or irregular. The arrangement of the first openings K1 can be as follows: Figure 3 The arrangement shown can also be any other regular or irregular arrangement.

[0050] Taking the first power structure 21 as the positive power structure Pvdd and the second power structure 22 as the negative power structure Pvee as an example, Figure 1 or Figure 2From the schematic pixel circuit diagram, it can be understood that the first power structure 21 is connected to the transistor in the pixel circuit, and the second power structure 22 is connected to an electrode of the light emitting device. Figure 3 The figure also shows a first connection terminal 021 and a second connection terminal 022. The first connection terminal 021 is used to be electrically connected to the anode of the light-emitting device, and the second connection terminal 022 is used to be electrically connected to the cathode of the light-emitting device. Figure 3 In the embodiment, one light emitting device may be fixed in one pixel region Q.

[0051] Figure 4 Schematic diagram of a cross section of a driving plate provided by an embodiment of the present invention. Figure 4 As shown, the driving board includes a substrate 010 , and the pixel circuit 10 , the first power structure 21 , and the second power structure 22 are located on the same side of the substrate 010 . Figure 4 1 shows the driving transistor Tm, the first emission control transistor T5 and the storage capacitor Cst in the pixel circuit 10. One electrode of the first emission control transistor T5 is coupled to the first power supply structure 21. At least one inorganic layer 40 is provided on the side of the block structure 30 away from the substrate 010.

[0052] like Figure 4 As shown, the driving board includes a first metal layer 011, a second metal layer 012, a capacitor metal layer 013, and a semiconductor layer 014 located on the same side of a substrate 010. The second metal layer 012 is located on the side of the first metal layer 011 away from the substrate 010, the capacitor metal layer 013 is located between the first metal layer 011 and the second metal layer 012, and the semiconductor layer 014 is located between the first metal layer 011 and the substrate 010. An insulating layer is provided between the semiconductor layer 014 and the first metal layer 011, as well as between each adjacent metal layer. Figure 4 Not marked.

[0053] In the driver board provided by the embodiment of the present invention, at least one of the first power supply structure 21 and the second power supply structure 22 in the pixel region Q includes a block structure 30, that is, at least one power supply structure in the pixel region is set to a large-area structure rather than a conventional linear metal. This can reduce the resistance of the power supply structure, reduce the voltage drop on the overall power supply structure in the driver board, improve the uniformity of the power supply voltage signal in each pixel region Q of the driver board, and at the same time reduce power consumption. The block structure 30 is provided to include a first block structure 31, and the first block structure 31 includes at least one first opening K1. The first opening K1 can partially interrupt the large-area first block structure 31. It should be noted that in the embodiment of the present invention, "partial interruption" means that the large-area structure is interrupted at the opening position by using an opening. The large-area structure has a structural defect at the opening position, so that the structures located on the upper and lower sides (or left and right sides) of the opening are interrupted at the opening position, but the large-area structure as a whole still has continuity.

[0054] When a large-area structure enters the CVD system, it overlaps with the electrodes in the CVD system, forming a large capacitor. However, the charge within the large-area structure flows unrestricted throughout the structure, so it tends to accumulate in a large, localized area. Excessive localized charge accumulation within the large-area structure increases the probability of abnormal discharge between the large-area structure and the electrodes in the CVD system.

[0055] In the embodiment of the present invention, the first opening K1 is used to interrupt the large-area first block structure 31 into multiple small-area structures that are still electrically connected to each other. The presence of the first opening K1 reduces the cross-sectional area of ​​charge flow within the first block structure 31, limiting the flow of charge between the small-area structures separated by the first opening K1. This is equivalent to dispersing the charge on the first block structure 31, thereby reducing the amount of charge accumulated within the small-area structures, and thus reducing the amount of charge accumulated locally on the first block structure 31. During the manufacture of the driver board, after the block structure 30 process, the module is placed in a CVD machine to form the inorganic insulating layer. The first opening K1 interrupts the large-area first block structure 31 into multiple small-area structures that are still electrically connected to each other, reducing the amount of charge accumulated within the small-area structures. The lower the charge amount, the lower the risk of electrostatic discharge. This reduces the risk of abnormal discharge between the small-area structures and the CVD machine, and thus reduces the risk of abnormal discharge between the first block structure 31 and the CVD machine. In addition, the small-area structures formed by the interruption of the first opening K1 overlap with the electrodes in the CVD machine to form small capacitors, wherein both small capacitors and large capacitors are viewed in terms of the overlapping area of ​​the two plates. A large capacitor is formed when the overlapping area is large, and a small capacitor is formed when the overlapping area is small. Since the capacitance formed by the small-area structures overlapping with the electrodes in the CVD machine is small, the amount of charge that can be stored in the capacitor is small. Even if abnormal discharge occurs, the energy generated by the discharge of a small amount of charge is also small, and the harm caused is relatively light, and will not cause fragmentation or damage to the electrode, which can improve the process yield and reduce costs. In the embodiment of the present invention, an inorganic layer 40 is provided on the side of the first block structure 31 away from the substrate 010, and the excellent water and oxygen barrier ability of the inorganic material is utilized to effectively protect the first block structure 31 to prevent the first block structure 31 from being corroded, which can meet the requirements of a high-temperature and high-humidity working environment, improve the performance reliability of the drive board, and reduce the probability of display abnormalities.

[0056] The embodiment of the present invention utilizes the first opening K1 to partially isolate the large-area power supply structure to form a plurality of small-area power supply units that are still electrically connected, which can reduce the amount of charge locally accumulated in the large-area power supply structure. The large-area power supply structure is at least one of the first power supply structure 21 and the second power supply structure 22. When the driver board is manufactured, the module is placed on a CVD machine to manufacture an inorganic insulating layer after the large-area power supply structure process. Since the amount of charge locally accumulated in the large-area power supply structure is reduced, the risk of abnormal discharge between the large-area power supply structure and the CVD machine can be reduced, which can improve the process yield and reduce costs. The inorganic layer is manufactured after the large-area power supply structure process, and the excellent water and oxygen barrier ability of the inorganic material is utilized to effectively protect the large-area power supply structure, prevent the large-area power supply structure from being corroded, improve the performance reliability of the driver board, and reduce the probability of display abnormalities.

[0057] In the embodiment of the present invention, the first openings K1 in the first block structure 31 are provided to partially isolate a large area of ​​the first block structure 31. The first openings K1 extend perpendicularly to the substrate plane through the film layer containing the first block structure 31. There are no restrictions on the area of ​​a single first opening K1 or the density of the first openings K1 as a whole. The first openings K1 are openings in the first block structure 31, and no other conductive structures are provided within them.

[0058] Within the pixel region Q, the first openings K1 formed in the first block structure 31 have a certain impact on the resistance of the first block structure 31, causing the resistance of the first block structure 31 to increase. The larger the hole area of ​​the first opening K1, the greater the impact on the resistance of the first block structure 31. The hole area of ​​the first opening K1, the hole density of the overall first opening K1, and the proportion of the total hole area in the area of ​​the first block structure 31 have a complex correlation on the resistance of the first block structure 31. In practice, the hole area of ​​the first opening K1, the hole density of the overall first opening K1, and the total hole area can be set according to specific design requirements.

[0059] like Figure 3As shown, the first block structure 31 includes at least two first openings K1, and the spacing between two adjacent first openings K1 is D1, where D1≤1mm. It should be noted that the spacing between the two first openings K1 is calculated as the shortest distance between the edges of the two holes. In this embodiment, the spacing between two adjacent first openings K1 is limited to no more than 1mm. The first openings K1 can be used to partially isolate at least one large-area power supply structure to form multiple power supply units with smaller areas that are still electrically connected to each other. The presence of the first openings K1 reduces the cross-sectional area of ​​charge flow inside the first block structure 31, limiting the mutual flow of charge between the power supply units separated by the first openings K1, so that the amount of charge accumulated in each power supply unit is also less. The less the charge, the lower the risk of electrostatic discharge. The risk of abnormal discharge between each small-area power supply unit and the CVD machine is reduced, which also reduces the risk of abnormal discharge between the large-area power supply structure and the CVD machine, which can improve the process yield and reduce costs. In addition, after the first block structure 31 process, the inorganic layer is used to protect the first block structure 31, which can meet the requirements of high temperature and high humidity working environment, improve the performance reliability of the driving board, and reduce the probability of display abnormality.

[0060] In some embodiments, D1≤0.6mm can further reduce the size of the small-area power supply unit formed by local partitions, further limit the mutual flow of charge between the small-area power supply units separated by the first opening K1, and further reduce the amount of charge accumulated in a large area. The smaller the amount of charge, the smaller the risk of electrostatic discharge. The risk of abnormal discharge between each small-area power supply unit and the CVD machine is reduced, which also reduces the risk of abnormal discharge between the large-area power supply structure and the CVD machine. In addition, the overlapping area of ​​the electrodes in the small-area power supply unit and the CVD machine is further reduced, so that the capacitance formed between the two is further reduced, and the amount of charge that can be stored in the small capacitor is also reduced. Even if abnormal discharge occurs, the energy generated by the discharge of a smaller amount of charge is also smaller, and the damage caused is lighter. It will not cause fragmentation or electrode damage, which can improve process yield and reduce costs.

[0061] In some embodiments, Figure 5 A partial schematic diagram of another driving board provided in an embodiment of the present invention, Figure 5 Schematically shows two pixel regions Q adjacent to each other in a first direction x. The driving board includes a first signal line 03 extending along the first direction x. The first signal line 03 and the pixel circuit 10 are located on the same side of the substrate 010. Figure 5 The top view of the driving board is parallel to the plane perpendicular to the substrate 010. Figure 5It can be seen that the first signal line 03 overlaps with at least one first opening K1 in a direction perpendicular to the plane of the substrate 010. The first signal line 03 and the first block structure 31 are located in different layers, that is, the first signal line 03 and the large-area power supply structure are located in different layers. When the power supply structure is set to a large-area shape, the power supply structure will overlap with the first signal line 03 to generate parasitic capacitance. Setting the first signal line 03 to overlap with at least one first opening K1 in a direction perpendicular to the plane of the substrate 010 can reduce the overlapping area between the first signal line 03 and the first block structure 31, thereby reducing the parasitic capacitance between the first signal line 03 and the power supply structure, reducing the load on the first signal line 03 and the power supply structure, and correspondingly reducing the voltage drop on the first signal line 03 and the voltage drop on the power supply structure, which is beneficial to improving the brightness uniformity of the light-emitting devices in each pixel area Q on the driver board, and is also beneficial to reducing power consumption.

[0062] In the embodiment of the present invention, there is no limit on the number of first openings K1 that overlap with the same first signal line 03 along a direction perpendicular to the plane of the substrate 010. Figure 5 As shown, at least two first openings K1 arranged in the first direction x overlap with the same first signal line 03 .

[0063] In one embodiment, in combination with the above Figure 2 Schematic diagram of pixel circuit Figure 5 To understand, such as Figure 5 As shown, the driving board also includes a driving signal line, which is coupled to the pixel circuit 10. Figure 5 The pixel circuit 10 is simplified by a graphic box, and the locations where the drive signal lines are coupled to the pixel circuit 10 are not shown. The drive signal lines include a first drive signal line 51 extending along a first direction x and a second drive signal line 52 extending along a second direction y, where the second direction y intersects the first direction x. The first drive signal line 51 includes a first scan line Sc1, a second scan line Sc2, an emission control line E, a data signal line segment Xd, and a reset signal line segment Xr. The second drive signal line 52 includes a data line Vdata and a reset line Ref. The data signal line segment Xd is connected to the data line Vdata via a via extending through the insulating layer, and the reset signal line segment Xr is connected to the reset line Ref via a via extending through the insulating layer. Figure 5 The position circled in the middle area Q1 is the position where the data signal line segment Xd is connected to the data line Vdata via a via hole, and the position where the reset signal line segment Xr is connected to the reset line Ref via a via hole.

[0064] Depending on the structure of the pixel circuit, the type and number of driving signal lines set in the driving board will vary. Figure 5 It is merely an optional embodiment provided by the present invention and is not intended to limit the present invention.

[0065] like Figure 5 As shown, along the first direction x, the first power structure 21 and the second power structure 22 are adjacent to each other in the pixel region Q. Figure 5 Two pixel regions Q are shown, and it can be seen that the first power supply structure 21 and the second power supply structure 22 are arranged alternately in the first direction x. To further reduce the resistance of the power supply structure, the embodiment of the present invention provides a power supply connection line 60. The power supply connection line 60 includes a first power supply connection line 61 and a second power supply connection line 62. The first power supply connection line 61 is used to electrically connect two first power supply structures 21 adjacent to each other along the first direction x, and the second power supply connection line 62 is used to electrically connect two second power supply structures 22 adjacent to each other along the first direction x. The first power supply connection line 61 is connected to the first power supply structure 21 through a first via V1 that penetrates the insulating layer, and the second power supply connection line 62 is connected to the second power supply structure 22 through a second via V2 that penetrates the insulating layer.

[0066] In some embodiments, the first signal line 03 includes a power connection line 60. Figure 5From the top view, it can be seen that, along the direction perpendicular to the plane where the substrate 010 is located, the first block structure 31 included in the first power structure 21 overlaps with the second power connection line 62, and the second power connection line 62 overlaps with at least one first opening K1; along the direction perpendicular to the plane where the substrate 010 is located, the first block structure 31 included in the second power structure 22 overlaps with the first power connection line 61, and the first power connection line 61 overlaps with at least one first opening K1. In this embodiment, both the first power structure 21 and the second power structure 22 include a first block structure 31, that is, both the positive power structure and the negative power structure are set as large-area structures, which can reduce the resistance of the power structure, improve the uniformity of the power voltage signal in multiple pixel areas Q on the entire surface of the driving board, and also reduce power consumption. In addition, the first opening K1 is provided to partially isolate the first block structure 31, which can reduce the amount of charge locally accumulated in the first block structure 31. During driver board fabrication, after the power structure process, the module is placed on a CVD machine to form the inorganic insulating layer. The presence of the first opening K1 reduces the amount of charge accumulated locally within the power structure, thereby reducing the risk of abnormal discharge between the power structure and the CVD machine, improving process yield and reducing costs. Furthermore, the inorganic layer 40 can be positioned on the side of the power structure away from the substrate 010, effectively protecting the power structure from corrosion by leveraging the inorganic material's excellent ability to block water and oxygen. This improves the driver board's performance and reliability, enabling it to meet the requirements of high-temperature and high-humidity operating environments and reducing the likelihood of abnormal displays. In addition, a first power connection line 61 is provided to electrically connect the multiple first power structures 21 alternately arranged in the first direction x in the driving board, which can further reduce the voltage drop on the first common power supply; a second power connection line 62 is provided to electrically connect the multiple second power structures 22 alternately arranged in the first direction x in the driving board, which can further reduce the voltage drop on the second common power supply; and along a direction perpendicular to the plane of the substrate 010, the second power connection line 62 is provided to overlap with at least one first opening K1, and the first power connection line 61 overlaps with at least one first opening K1, which can reduce the parasitic capacitance generated by the overlap of the second power connection line 62 and the first power structure 21, and can also reduce the parasitic capacitance generated by the overlap of the first power connection line 61 and the second power structure 22, which is beneficial to reducing power consumption.

[0067] like Figure 5As shown, the first opening K1 includes a first sub-aperture K11 and a second sub-aperture K12, with the first sub-aperture K11 having a larger aperture area than the second sub-aperture K12. In a direction perpendicular to the plane of the substrate 010, the power connection line 60 overlaps with at least one of the first sub-apertures K11. Taking the first power connection line 61 as an example, to reduce the resistance of the first power connection line 61 itself, the line width of the first power connection line 61 can be made relatively wide, and the first sub-aperture K11 with a larger aperture area can be arranged to overlap the first power connection line 61. This can reduce the parasitic capacitance generated by the overlap between the first power connection line 61 and the second power structure 22, improve the uniformity of the power supply voltage signal within multiple pixel regions Q across the entire surface of the driver board, and also reduce power consumption.

[0068] In some embodiments, as Figure 5 As shown, the power connection line 60 overlaps with at least one first sub-hole K11, and at the same time, the power connection line 60 overlaps with at least one second sub-hole K12. Still taking the first power connection line 61 as an example, the first power connection line 61 overlaps with the first block structure 31 included in the second power structure 22. A first opening K1 is made on the first block structure 31 to partially isolate the first block structure 31, and the first opening K1 will also have a certain impact on the overall resistance of the first block structure 31. Setting the first power connection line 61 to overlap with both the first sub-hole K11 and the second sub-hole K12 is beneficial for achieving a balance between the overall resistance of the first block structure 31 and reducing the parasitic capacitance generated by the overlap of the first power connection line and the first block structure 31.

[0069] In some embodiments, as Figure 5 As shown in the diagram at the locations of regions Q2 and Q3, the first power connection line 61 has an opening that penetrates the film layer in which it is located. At the location of region Q2, the first power connection line 61 overlaps with the first block structure 31, and an opening is made in the first power connection line 61 to reduce the parasitic capacitance generated by the overlap between the first power connection line 61 and the first block structure 31. At the location of region Q3, the first power connection line 61 overlaps with the second drive signal line 52, and an opening is made in the first power connection line 61 to reduce the parasitic capacitance generated by the overlap between the first power connection line 61 and the second drive signal line 52, thereby reducing the load on the second drive signal line 52.

[0070] In some embodiments, as Figure 5As shown, the first signal line 03 includes a first drive signal line 51, that is, the first signal line 03 includes at least one of the first scan line Sc1, the second scan line Sc2, the light control line E, the data signal line segment Xd, and the reset signal line segment Xr. Arranging the first drive signal line 51 to overlap with at least one first opening K1 can reduce the parasitic capacitance generated by the overlap between the first drive signal line 51 and the first block structure 31 in a direction perpendicular to the plane of the substrate 010, thereby reducing the load on the first drive signal line 51 and improving the brightness uniformity of the light-emitting devices in each pixel area Q on the driver board. Furthermore, the load on the first block structure 31 can be reduced, thereby reducing power consumption.

[0071] like Figure 5 As shown, the first drive signal line 51 overlaps with at least one second sub-aperture K12 in a direction perpendicular to the plane of the substrate 010. To accommodate the size of the transistors in the pixel circuit 10 and minimize the space occupied by the pixel circuit 10, the line width of the first drive signal line 51 is generally set relatively narrow. A second sub-aperture K12 with a smaller aperture area is arranged to overlap the first drive signal line 51 based on the line width of the first drive signal line 51. This can reduce the capacitance generated by the overlap between the first drive signal line 51 and the first block structure 31 in a direction perpendicular to the plane of the substrate 010, lowering the load on the first drive signal line 51 and facilitating improved brightness uniformity of the light-emitting devices within each pixel region Q on the driver board. Furthermore, the smaller second sub-aperture K12 has a smaller impact on the overall resistance of the first block structure 31.

[0072] In one embodiment, if Figure 5 As shown, the second drive signal line 52 is located between two pixel areas Q adjacent to each other along the first direction x; the second drive signal line 52 and the first drive signal line 51 are located in different layers, and part of the first drive signal line 51 is coupled to the second drive signal line 52. The second drive signal line 52 includes a data line Vdata and a reset line Ref, the data signal line segment Xd is coupled to the data line Vdata, and the reset signal line segment Xr is coupled to the reset line Ref. The second drive signal line 52 extending along the second direction y is arranged on the periphery of the first power structure 21 and the second power structure 22, so that the second drive signal line 52 does not need to overlap with the first power structure 21 or the second power structure 22. The second drive signal line 52 is coupled to the pixel circuit 10 through the corresponding first drive signal line 51, which can reduce the overlapping area with the first block structure 31 and the signal line, and reduce the influence of parasitic capacitance on the load of the signal line.

[0073] In one embodiment, Figure 6 A schematic diagram of the film structure of another driving plate provided in an embodiment of the present invention is shown in FIG. Figure 6As shown, the driving board includes a first metal layer 011 and a second metal layer 012 located on the same side of the substrate 010, and the second metal layer 012 is located on the side of the first metal layer 011 away from the substrate 010; wherein, the first driving signal line 51 is located in the first metal layer 011, and the first block structure 31 is located in the second metal layer 012. The driving board also includes a capacitor metal layer 013 and a semiconductor layer 014, the capacitor metal layer 013 is located between the first metal layer 011 and the second metal layer 012, and the semiconductor layer 014 is located between the first metal layer 011 and the substrate 010. One plate of the storage capacitor Cst is located in the capacitor metal layer 013, and the other plate is located in the first metal layer 011. wherein, an insulating layer is provided between the semiconductor layer 014 and the first metal layer 011, as well as between each adjacent metal layer, Figure 6 The first drive signal line 51 is disposed on the first metal layer 011, and the first block structure 31 is disposed on the second metal layer 012, with at least two insulating layers between them. In a direction e perpendicular to the plane of the substrate 010, the first drive signal line 51 and the first block structure 31 are spaced relatively far apart, which helps reduce parasitic capacitance between them.

[0074] In one embodiment, the first metal layer 011 and the capacitor metal layer 013 are made of molybdenum, and the second metal layer 012 is made of titanium and aluminum. Optionally, the second metal layer 012 is a three-layer structure of titanium / aluminum / titanium.

[0075] In some embodiments, the second drive signal line 52 is located on the same layer as the first block structure 31. In this way, the second drive signal line 52 can be set on the periphery of the first power structure 21 and the second power structure 22, which can reduce the overlapping area with the first block structure 31 and the signal line, and can also reduce the impact of parasitic capacitance on the load of the second drive signal line 52, which is beneficial to improving the brightness uniformity of the light-emitting devices in each pixel area Q on the driving board.

[0076] In addition, if Figure 6 As shown, the driving board also includes a light-shielding metal layer 015, which is located on the side of the semiconductor layer 014 close to the substrate 010. In the direction e perpendicular to the plane where the substrate 010 is located, the light-shielding metal layer 015 overlaps with the channel of the transistor. The active layer of the transistor is located in the semiconductor layer 014, and the channel of the transistor is the part of the active layer that overlaps with the gate of the transistor in the direction e perpendicular to the plane where the substrate 010 is located. The light-shielding metal layer 015 is used to block the channel of the transistor to prevent light from entering the channel from the side of the substrate 010, thereby ensuring the stability of the transistor characteristics. Figure 6 The light shielding metal layer 015 is connected to the electrode 040 located in the first metal layer 011 through the via hole of the insulating layer, so that a dual-gate transistor structure can be formed, which can improve the characteristics and performance of the transistor. Figure 6 FIG. 1 schematically shows that one plate of the storage capacitor Cst is located in the capacitor metal layer 013, and the other plate is located in the first metal layer 011. In an embodiment of the present invention, a light-shielding metal layer 015 is further provided so that the plate located in the capacitor metal layer 013 overlaps in a direction perpendicular to the plane of the substrate 010, thereby increasing the capacitance of the storage capacitor Cst.

[0077] In some embodiments, Figure 7 A schematic diagram of another driving board provided in an embodiment of the present invention, Figure 8 for Figure 7 A schematic cross-section diagram at the midline AA'. Figure 7 FIG. 1 shows a pixel region Q, but does not show structures such as driving signal lines and power supply connection lines. Figure 7 and Figure 8 From the perspective of FIG. 1 , the driver board further includes an auxiliary power supply structure 70. The auxiliary power supply structure 70 is located on a side of the first block structure 31 away from the substrate 010. A first insulating layer 71 is provided between the auxiliary power supply structure 70 and the first block structure 31. The auxiliary power supply structure 70 and the first block structure 31 are connected via at least two vias V3 that penetrate the first insulating layer 71. In other words, the auxiliary power supply structure 70 is connected in parallel with the first block structure 31. Figure 7 In the figure, the first power structure 21 includes a first block structure 31 , and the second power structure 22 includes a first block structure 31 for illustration.

[0078] Figure 7 Only the structure at the location of one pixel region Q is schematically shown. Two auxiliary power supply structures 70 are provided in the pixel region Q, one of which is connected in parallel with the first block structure 31 of the first power supply structure 21, and the other is connected in parallel with the first block structure 31 of the second power supply structure 22. Viewed from the entire surface of the drive board, in the second direction y, the auxiliary power supply structures 70 connected to the first power supply structure 21 in adjacent pixel regions Q are connected to each other, and the auxiliary power supply structures 70 connected to the second power supply structure 22 in adjacent pixel regions Q are connected to each other. In other words, the drive board as a whole includes two auxiliary power supply structures, one of which is connected in parallel with the first common power supply, and the other is connected in parallel with the second common power supply.

[0079] In the embodiment of the present invention, a first opening K1 is formed on the first block structure 31. The first opening K1 is used to partially isolate the first block structure 31. The first opening K1 reduces the cross-sectional area of ​​charge flow within the first block structure 31, limiting the flow of charge between the small-area structures separated by the first opening K1. This is equivalent to dispersing the charge on the first block structure 31, which can reduce the amount of charge locally accumulated in the first block structure 31. When manufacturing the driver board, after the block structure process, the module is placed on a CVD machine to form an inorganic insulating layer. Due to the presence of the first opening K1, the amount of charge accumulated in each small-area structure is reduced, thereby reducing the risk of abnormal discharge between each small-area structure and the CVD machine, thereby reducing the risk of abnormal discharge between the first block structure 31 and the CVD machine. The setting of the first opening K1 will have a certain impact on the overall resistance of the first block structure 31. By setting the auxiliary power supply structure 70 in parallel with the first block structure 31, the resistance of the power supply structure can be reduced, the voltage drop of the power supply structure can be reduced, the uniformity of the power supply voltage signal in multiple pixel areas Q on the entire surface of the driving board can be improved, and the power consumption can also be reduced.

[0080] In other embodiments, only one auxiliary power structure 70 is provided in the pixel region Q, and the auxiliary power structure 70 is connected in parallel to the first block structure 31 of one of the first power structure 21 and the second power structure 22. This is not illustrated in the figure.

[0081] In some embodiments, the first insulating layer 71 includes an inorganic insulating layer.

[0082] In another embodiment, the first insulating layer 71 includes an organic insulating layer.

[0083] like Figure 7 and Figure 8As shown, the block structure 30 also includes a second block structure 32, which is located on a side of the first block structure 31 away from the substrate 010. The second block structure 32 includes at least one second opening K2. The auxiliary power structure 70 includes the second block structure 32. In other words, the auxiliary power structure 70 is configured as a large-area structure, which can reduce the resistance of the auxiliary power structure 70. By connecting the auxiliary power structure 70 in parallel with the first block structure 31, the resistance of the power structure is further reduced, thereby further improving the uniformity of the power supply voltage signal within multiple pixel regions Q across the entire surface of the driver board. At the same time, a second opening K2 is provided on the second block structure 32, which partially isolates the large-area second block structure 32 using the second opening K2, limiting the flow of charge between the smaller-area structures separated by the second opening K2. This is equivalent to dispersing the charge on the second block structure 32, reducing the amount of charge accumulated within the smaller-area structures, and thus reducing the amount of charge locally accumulated in the second block structure 32. During driver board production, after the second block structure 32 process, the module is placed on a CVD machine to form an inorganic insulating layer. Because the second openings K2 interrupt the large-area second block structure 32 into multiple smaller structures that remain electrically connected, the amount of charge accumulated within the smaller structures is reduced. The lower the charge, the lower the risk of electrostatic discharge. This reduces the risk of abnormal discharge between the smaller structures and the CVD machine, and thus also between the second block structure 32 and the CVD machine. An inorganic layer can be provided on the side of the second block structure 32 away from the substrate 010, leveraging the inorganic material's excellent ability to block water and oxygen to effectively protect the second block structure 32 from corrosion. This improves the driver board's performance and reliability, enabling it to meet the requirements of high-temperature and high-humidity operating environments and reducing the likelihood of display anomalies.

[0084] like Figure 7 As shown, the second block structure 32 includes at least two second openings K2, and the spacing between two adjacent second openings K2 is D2, wherein D2≤1mm. The spacing between the two second openings K2 is calculated as the shortest distance between the edges of the two holes. In this embodiment, the spacing between two adjacent second openings K2 is limited to no more than 1mm, and the second openings K2 can be used to partially isolate the large-area second block structure 32, which can reduce the amount of charge locally accumulated in the second block structure 32. When the inorganic layer is produced after the process of the second block structure 32, the risk of abnormal discharge between the large-area second block structure 32 and the CVD machine can be reduced, which can improve the process yield and reduce costs.

[0085] In a pixel region Q, the total area of ​​the second openings K2 is S1, and the area of ​​the second block structure 32 is S0, where S1 / S0>0.1. By making the second openings K2 on the second block structure 32, the second block structure 32 with a large area can be partially isolated to reduce the amount of charge accumulated locally in the second block structure 32. In some embodiments, the insulating layer between the second block structure 32 and the first block structure 31 includes an organic insulating layer. During the process, the organic insulating layer releases gas when heated. The proportion of the total area of ​​the second openings K2 to the area of ​​the second block structure 32 is limited so that there can be a sufficiently large opening area at the location of the second block structure 32 to facilitate the discharge of gas and avoid the gas released by the organic insulating layer from being unable to be discharged, resulting in film peeling.

[0086] In some embodiments, S1 / S0>0.2.

[0087] like Figure 8 As shown, the second opening K2 includes a third sub-hole K23; the orthographic projection of the third sub-hole K23 on the substrate 010 is located within the orthographic projection of the first opening K1 on the substrate 010. That is, in a direction e perpendicular to the plane of the substrate 010, the third sub-hole K23 overlaps with the first opening K1, and the hole area of ​​the third sub-hole K23 is smaller than that of the first opening K1. This facilitates the gradual ramping of the subsequently fabricated film layer at the opening location, ensuring the continuity of the film layer.

[0088] In some embodiments, the auxiliary power structure 70 is made of the same material as the first block structure 31. Figure 6 From the schematic diagram of the driving plate membrane layer shown in the embodiment, the first block structure 31 is located in the second metal layer 012. In some embodiments, a third metal layer is further provided on the side of the second metal layer 012 away from the substrate 010, and the auxiliary power supply structure 70 is located in the third metal layer, and the third metal layer and the second metal layer 012 are made of the same material. The materials used to make the third metal layer and the second metal layer 012 include titanium and aluminum. The resistance of the metal structure made of the third metal layer and the second metal layer 012 is relatively small. The auxiliary power supply structure 70 is made of the same material as the first block structure 31, the auxiliary power supply structure 70 is located in the third metal layer, the first block structure 31 is located in the second metal layer 012, and the first block structure 31 and the auxiliary power supply structure 70 are connected in parallel, which can reduce the impedance of the power supply structure, thereby reducing the voltage drop and improving the uniformity of the power supply voltage signal within the driving plate surface.

[0089] In some embodiments, Figure 9 for Figure 7 A cross-sectional diagram at the midline BB'. Figure 9As shown, the second opening K2 includes a fourth sub-aperture K24; along a direction e perpendicular to the plane of the substrate 010, the fourth sub-aperture K24 does not overlap with the first opening K1. In other words, the fourth sub-aperture K24 overlaps with the non-aperture area of ​​the first block structure 31. The first insulating layer 71 between the second block structure 32 and the first block structure 31 comprises an organic insulating layer. During the manufacturing process, the organic insulating layer releases gas when heated. The gas can be discharged through the fourth sub-aperture K24, preventing the gas released from the organic insulating layer from being unable to be discharged, which may cause the film to peel.

[0090] Figure 9 The figure also illustrates a second opening K2 that overlaps with the first opening K1 in a direction perpendicular to the plane of the substrate 010. When the first insulating layer 71 comprises an organic insulating layer, the first insulating layer 71 can provide a certain degree of planarization. In this embodiment, the size relationship between the second opening K2 and the first opening K1 is not limited.

[0091] In another embodiment, an organic insulating layer is included between the second block structure 32 and the first block structure 31 . Figure 10 A schematic diagram of another film layer of a driving plate provided in an embodiment of the present invention, such as Figure 10As shown, the first insulating layer 71 between the second block structure 32 and the first block structure 31 includes a first sub-inorganic layer 41 and a first sub-organic layer 42. The first sub-organic layer 42 is an organic insulating layer, and the first sub-inorganic layer 41 is an inorganic insulating layer. The first sub-organic layer 42 is located on a side of the first sub-inorganic layer 41 away from the first block structure 31. Optionally, the first block structure 31 is made of metal titanium and metal aluminum. In one embodiment, the first block structure 31 is a three-layer metal structure of titanium / aluminum / titanium, and the thickness of the first block structure 31 is relatively thick, and the thickness of the first sub-inorganic layer 41 made on the first block structure 31 is relatively thin, which may not be able to completely cover the first block structure 31 and cause defects. For example, a slope will be formed at the edge of the first block structure 31, and the thinner first sub-inorganic layer 41 may not be able to completely cover the slope position, resulting in the edge of the first block structure 31 being exposed to the outside and easily corroded. However, the first sub-inorganic layer 41 has good density and excellent ability to block water and oxygen, and can play a good barrier role against the erosion of water and oxygen on the first block structure 31. In this embodiment of the present invention, a thicker first sub-organic layer 42 is formed after the first sub-inorganic layer 41 is formed. The organic layer and the inorganic layer are formed using different processes. The first sub-organic layer 42 has a certain degree of fluidity during the initial manufacturing process, enabling it to effectively cover the sloped areas. The first sub-organic layer 42 is used to cover portions of the first block structure 31 that may not be covered by the first sub-inorganic layer 41, thereby improving protection for the first block structure 31. In this embodiment, the second block structure 32 includes a fourth sub-hole K24. During the manufacturing process, the first sub-organic layer 42 releases gas when heated. The gas can be discharged through the fourth sub-hole K24, preventing the gas released from the first sub-organic layer 42 from being unable to be discharged, resulting in film delamination, thereby improving the stability of the film structure.

[0092] like Figure 10 As shown, a second insulating layer 72 is provided on the side of the second block structure 32 away from the substrate 010, and the second insulating layer 72 is used to protect the second block structure 32 on the side of the second block structure 32 away from the substrate 010. Optionally, the second insulating layer 72 includes at least one inorganic layer. The excellent water and oxygen barrier ability of inorganic materials is utilized to effectively protect the second block structure 32, which can improve the performance reliability of the drive board. At the same time, the second opening K2 is used to partially isolate the second block structure 32. When the second insulating layer 72 is manufactured after the process of the second block structure 32, the risk of abnormal discharge between the second block structure 32 and the CVD machine can be reduced, which can improve the process yield and reduce costs.

[0093] In some embodiments, as Figure 7As shown, the pixel region Q further includes a connecting electrode 80, one end of the connecting electrode 80 corresponds to the output end of the pixel circuit 10, and the other end of the connecting electrode 80 corresponds to the second power supply structure 22. Figure 1 or Figure 2 The schematic diagram of the pixel circuit 10 is used for understanding. The output end of the pixel circuit 10 is the output port for outputting driving current to the light-emitting device when the pixel circuit 10 is working. The light-emitting device needs to be bound in the pixel area Q. The "corresponding" defined in this embodiment is understood to mean that there is a certain correlation between the two and they are set one to one. In an embodiment of the present invention, the connecting electrode 80 is "Z"-shaped, and the connecting electrode 80 is located between the first power supply structure 21 and the second power supply structure 22. The connecting electrode 80 includes a first protrusion 80-1 and a second protrusion 80-2. The connecting electrode 80 can play the role of connecting the wires, such as Figure 7 The regions Q5 and Q6 are shown in FIG. The first protrusion 80-1 of the connecting electrode 80 at the position of region Q6 corresponds to the output terminal of the pixel circuit 10, and the second protrusion 80-2 of the connecting electrode 80 at the position of region Q5 corresponds to the second power supply structure 22. A light-emitting device is fixed at the position of region Q6, the anode of which is coupled to the output terminal of the pixel circuit 10, and the cathode of which is coupled to the first protrusion 80-1 of the connecting electrode 80; another light-emitting device is fixed at the position of Q5, the anode of which is coupled to the second protrusion 80-2 of the connecting electrode 80, and the cathode of which is coupled to the second power supply structure 22. The present invention sets the connecting electrode 80 between the first power supply structure 21 and the second power supply structure 22, and there is no need to adjust the position of the pixel circuit and the signal line in the pixel region Q. In this way, two light-emitting devices can be set in series in one pixel region Q. In conventional settings, the greater the brightness required by the pixel region Q, the greater the driving current required to be provided to the light-emitting device, resulting in greater power consumption. In the embodiment of the present invention, two light-emitting devices are connected in series within a pixel region Q, enabling the pixel region to achieve a high brightness even at a low drive current, thereby reducing power consumption. Furthermore, the reduced drive current also reduces the requirements for the pixel circuit, and thus the performance requirements for the display driver chip.

[0094] in addition, Figure 10 The output terminal 10 - c of the pixel circuit 10 is schematically shown in FIG. 1 . It can be seen that the opening on the second insulating layer 72 exposes the output terminal 10 - c , so that the electrode of the light-emitting device can be coupled to the output terminal 10 - c through a bonding process.

[0095] In some embodiments, Figure 11 A schematic diagram of another film layer of a driving plate provided in an embodiment of the present invention, such as Figure 11As shown, the pixel region Q further includes a metal oxide layer 91. The metal oxide layer 91 is located on a side of the block structure 30 away from the substrate 010. The metal oxide layer 91 is coupled to the block structure 30. The block structure 30 includes a first block structure 31, which has a first opening K1. The features of the first block structure 31 can be understood with reference to the above-mentioned related embodiments. Figure 11 The first block structure 31 in the figure belongs to the first power structure 21, which is the positive power structure Pvdd. Specifically, a metal oxide layer 91 is provided on the side of the first power structure 21 away from the substrate 010, and the metal oxide layer 91 is coupled to the first power structure 21. In this embodiment, the block structure 30 is a positive power structure. During application, electrochemical corrosion preferentially occurs on the metal oxide layer 91. Therefore, the metal oxide layer 91 can be used to enhance the electrochemical corrosion resistance of the block structure 30, thereby improving the performance and stability of the driver board.

[0096] In some embodiments, the metal oxide layer 91 includes at least one of indium tin oxide, indium zinc oxide, zinc oxide, or indium oxide.

[0097] In other embodiments, Figure 11 The middle block structure 30 belongs to the second power structure 22, that is, a metal oxide layer 91 is provided on the side of the second power structure 22 away from the substrate 010, and the metal oxide layer 91 is coupled to the second power structure 22. This is not illustrated in the figure.

[0098] Figure 11 In the figure, only the block structure 30 includes the first block structure 31. In some embodiments, the block structure 30 also includes a second block structure 32, which is located on the side of the first block structure 31 away from the substrate 010. The second block structure 32 can be understood with reference to the above-mentioned related embodiments. The metal oxide layer 91 is located on the side of the second block structure 32 away from the substrate 010. The metal oxide layer 91 is coupled to the second block structure 32 and is not shown in the figure here.

[0099] like Figure 11 As shown, a third insulating layer 73 is further provided on the side of the metal oxide layer 91 away from the substrate 010 . Optionally, the third insulating layer 73 includes an organic material. The third insulating layer 73 can play a planarization role behind the metal oxide layer 91 . Figure 11 The output terminal 10-c of the pixel circuit 10 is also illustrated. It can be seen that the opening on the third insulating layer 73 and the opening on the inorganic layer 40 overlap and jointly expose the output terminal 10-c, so that the electrode of the light-emitting device can be coupled to the output terminal 10-c through a binding process.

[0100] like Figure 11As shown, an inorganic layer 40 is provided between the metal oxide layer 91 and the block structure 30. That is, the insulating layer between the metal oxide layer 91 and the block structure 30 is an inorganic material, wherein the metal oxide layer 91 and the block structure 30 are coupled via vias penetrating the inorganic layer 40. When manufacturing the driver board, the inorganic layer 40 is first fabricated after the process of the block structure 30, and then the metal oxide layer 91 is fabricated after the process of the inorganic layer 40. The fabrication of the metal oxide layer 91 includes an etching process. The inorganic layer 40 fabricated before the fabrication of the metal oxide layer 91 can protect the underlying metal structure, preventing the etching solution in the etching process of the metal oxide layer 91 from over-etching the underlying metal structure.

[0101] In another embodiment, Figure 12 A schematic diagram of another film layer of a driving plate provided in an embodiment of the present invention, such as Figure 12 As shown, the metal oxide layer 91 is in direct contact with the surface of the block structure 30 away from the substrate 010. The metal oxide layer 91 covers the surface of the block structure 30 and couples with the block structure 30. This embodiment can utilize the metal oxide layer 91 to enhance the block structure 30's resistance to electrochemical corrosion and improve the performance and stability of the driver board. The patterning process of the metal oxide layer 91 and the patterning process of the block structure 30 can be performed using the same mask plate, thereby reducing process costs.

[0102] In addition, if Figure 12 As shown, a fourth insulating layer 74 is provided on the side of the metal oxide layer 91 away from the substrate 010. Optionally, the fourth insulating layer 74 includes at least one inorganic layer, which utilizes the excellent water and oxygen barrier capability of inorganic materials to improve the performance reliability of the driver board in high temperature and high humidity working environments.

[0103] In some embodiments, Figure 13 A schematic diagram of another driving board provided in an embodiment of the present invention, Figure 14 Schematic diagram of another film layer of a driving plate provided by an embodiment of the present invention. Figure 13 As shown, the driving board includes a plurality of pads 92, which are located at the periphery of the plurality of pixel regions Q; the pads 92 are used to bind and connect with the driving structure, which may be, for example, a display driver chip or a flexible circuit board.

[0104] like Figure 14As shown, pad 92 and pixel circuit 10 are located on the same side of substrate 010. Pad 92 includes a metal portion 921 and a metal oxide portion 922. Metal oxide portion 922 is located on the side of metal portion 921 away from substrate 010. Metal oxide portion 922 and metal oxide layer 91 are located on the same layer. Metal oxide portion 922 protects metal portion 921 from corrosion. Metal oxide portion 922 and metal oxide layer 91 can be manufactured in the same process, which can simplify the process.

[0105] Combine Figure 6 For the purpose of understanding the film layer structure of the driving board illustrated in the embodiment, in one embodiment, the metal portion 921 is located in the second metal layer 012, and the metal portion 921 includes a three-layer metal structure of titanium / aluminum / titanium, then the hardness of the metal portion 921 is relatively small. In the binding process, for example, when the driving board and the flexible circuit board are bound, the conductive particles in the anisotropic conductive adhesive between the pad and the flexible circuit board need to be crushed by applying a large pressure. In the embodiment of the present invention, a metal oxide portion 922 is provided on the metal portion 921. Since the hardness of the metal oxide portion 922 is relatively large, a small pressure is used in the binding process to crush the conductive particles in the anisotropic conductive adhesive, thereby reducing the difficulty of the process.

[0106] In addition, if Figure 14 As shown, the insulating layer between the metal oxide layer 91 and the first block structure 31 is the inorganic layer 40. A fifth insulating layer 75 is further provided on the side of the metal oxide layer 91 away from the substrate 010. Figure 14 Schematically, the fifth insulating layer 75 includes two inorganic layers.

[0107] In some embodiments, the inorganic layer located on the side of the block structure 30 away from the substrate 010 includes a first inorganic layer, and the first inorganic layer is in contact with the block structure 30. In other words, when the driving board is manufactured, an inorganic layer is directly manufactured after the block structure 30 process, so as to protect the block structure 30 with the inorganic layer.

[0108] by Figure 4 Taking the embodiment as an example, the block structure 30 includes a first block structure 31, the inorganic layer 40 is a first inorganic layer, and the inorganic layer 40 is in direct contact with the first block structure 31 on the side of the first block structure 31 away from the substrate 010. Figure 10 Taking the embodiment as an example, the block structure 30 includes a first block structure 31 and a second block structure 32 , wherein the second insulating layer 72 includes a first inorganic layer, and the first inorganic layer contacts the second block structure 32 on a side of the second block structure 32 away from the substrate 010 .

[0109] In some embodiments, the driving board includes a first organic layer, which is located on the side of the block structure 30 away from the substrate 010, and the first organic layer is located on the side of at least one inorganic layer away from the block structure 30. When the thickness of the film layer where the block structure 30 is located is relatively thick, the relatively thin inorganic layer made on the block structure 30 may not be able to completely cover the edge slope position of the block structure 30 and there will be defects. In the embodiment of the present invention, a thicker first organic layer is made after the inorganic layer process. The first organic layer is thick and has a certain fluidity in the initial stage of production, which can cover the slope position well. Such a setting can ensure that the block structure 30 is completely covered and avoid the existence of exposed parts of the block structure 30. The good water and oxygen barrier ability of the inorganic layer is used to protect the block structure 30 and prevent the block structure 30 from corrosion. The organic layer on the inorganic layer can further improve the corrosion resistance and also play a flattening role.

[0110] In embodiments where the block structure 30 includes a first block structure 31, at least one inorganic layer is disposed on the side of the first block structure 31 facing away from the substrate 010. In some embodiments, the inorganic layer is in direct contact with the first block structure 31 on the side facing away from the substrate 010. In other embodiments, all insulating layers on the side of the first block structure 31 facing away from the substrate 010 are inorganic insulating layers. In still other embodiments, an organic insulating layer is further disposed on the side of the first block structure 31 facing away from the substrate 010, with at least one inorganic layer disposed between the organic insulating layer and the first block structure 31.

[0111] In embodiments where the block structure 30 includes a first block structure 31 and a second block structure 32, the first block structure 31 is located on the side of the second block structure 32 that is closer to the substrate 010, and at least one inorganic layer is provided on the side of the second block structure 32 that is farther from the substrate 010. In some embodiments, the at least one inorganic layer is in direct contact with the second block structure 32 on the side farther from the substrate 010. In other embodiments, all insulating layers on the side of the second block structure 32 that is farther from the substrate 010 are inorganic insulating layers. In other embodiments, an organic insulating layer is further provided on the side of the second block structure 32 that is farther from the substrate 010, with at least one inorganic layer provided between the organic insulating layer and the second block structure 32. In other embodiments, the insulating layer between the first block structure 31 and the second block structure 32 includes at least one inorganic layer. In still other embodiments, an organic insulating layer and an inorganic insulating layer are provided between the first block structure 31 and the second block structure 32, wherein the inorganic insulating layer is located on the side of the organic insulating layer that is closer to the substrate 010.

[0112] In some embodiments, as Figure 3 and Figure 4As shown, the first power supply structure 21 and the second power supply structure 22 both include a first block structure 31, and the first block structure 31 of the first power supply structure 21 and the first block structure 31 of the second power supply structure 22 are located on the same layer. This embodiment configures both the positive power supply structure and the negative power supply structure as large-area structures, which can reduce the resistance of the power supply structure, reduce the voltage drop across the power supply structure, improve the uniformity of the power supply voltage signal within each pixel area Q of the driver board, and also reduce power consumption. Furthermore, the large-area power supply structure is partially separated by the first opening K1 to form small-area power supply units. The presence of the first opening K1 reduces the cross-sectional area of ​​charge flow within the large-area power supply structure, limiting the flow of charge between the small-area power supply units separated by the first opening K1. This is equivalent to dispersing the charge existing on the large-area power supply structure, which can reduce the amount of charge accumulated in the small-area power supply units, that is, reduce the amount of charge accumulated locally in the large-area power supply structure. Placing the module in a CVD machine to form the inorganic insulating layer after the bulk power structure is processed can reduce the risk of abnormal discharge between the bulk power structure and the CVD machine, improving process yield and reducing costs. Furthermore, placing the first block structure 31 of the two power structures on the same layer can simplify the manufacturing process.

[0113] In one embodiment, Figure 15 A schematic diagram of another driving board provided in an embodiment of the present invention, Figure 16 for Figure 15 Schematic diagram of disassembly of storage capacitor. Figure 17 for Figure 15 A schematic cross-sectional view at the midline CC'. Figure 15 The storage capacitor Cst is shown in FIG. Figure 16 As shown, the storage capacitor includes a first plate C1 and a second plate C2. In a direction perpendicular to the plane of the substrate 010, the first plate C1 and the second plate C2 overlap to form a capacitor. The first plate C1 has a third opening K3, and the second plate C2 has a fourth opening K4. In a direction e perpendicular to the plane of the substrate 010, the third opening K3 and the fourth opening K4 overlap. Figure 15 FIG shows a schematic diagram of the via V4 connecting the first electrode plate C1 to the first power structure 21. Figure 1 or Figure 2 The first electrode C1 is coupled to the positive power supply structure Pvdd, and the second electrode C2 is coupled to the gate of the driving transistor Tm. Figure 15 The pixel circuit 10 is only simplified and the specific position of the driving transistor Tm is not shown. Figure 15 The connecting wire 050 is shown schematically in FIG. 1 , and the connecting wire 050 led out from the second electrode plate C2 is connected to the gate of the driving transistor Tm. Figure 17As shown, the second electrode plate C2 is located in the first metal layer 011, the first electrode plate C1 is located in the capacitor metal layer 013, and the first power supply structure 21 is located in the second metal layer 012. In the embodiment of the present invention, the first metal layer 011, the capacitor metal layer 013, and the second metal layer 012 are arranged in sequence away from the substrate 010. The first metal layer 011 and the capacitor metal layer 013 are two adjacent metal layers. The two electrodes of the storage capacitor Cst are respectively located in the first metal layer 011 and the capacitor metal layer 013. Therefore, the thickness of the insulating layer between the first electrode plate C1 and the second electrode plate C2 is relatively thin. When the capacitance value requirement of the storage capacitor Cst is met, the size of the first electrode plate C1 and the second electrode plate C2 does not need to be set too large. In addition, some signal lines in the driver board are arranged on the first metal layer 011, and the first power supply structure 21 and the second power supply structure 22 are arranged on the second metal layer 012. Therefore, there are at least two insulating layers between the signal lines and the power supply structure. The two insulating layers are respectively an insulating layer between the first metal layer 011 and the capacitor metal layer 013, and an insulating layer between the capacitor metal layer 013 and the second metal layer 012. This arrangement makes it possible to increase the spacing between the signal lines and the power supply structure in a direction perpendicular to the plane of the substrate 010. Therefore, the capacitance formed when the two overlap is relatively small, which can reduce the load on the signal lines and the power supply structure.

[0114] In this embodiment of the present invention, openings are formed in the first and second plates C1, C2, of the storage capacitor Cst. A third opening K3 is used to partially isolate a large area of ​​the first plate C1, and a fourth opening K4 is used to partially isolate a large area of ​​the second plate C2. These openings are arranged in a direction e perpendicular to the plane of the substrate 010, with the third and fourth openings K3 and K4 overlapping. While ensuring that the capacitance of the storage capacitor Cst formed by the overlap of the first and second plates C1 and C2 meets the required capacitance, this also prevents excessive localized charge accumulation on the first or second plates C1 and C2, which could cause abnormal discharge when the module is loaded into a CVD machine. Figure 16 In the embodiment, only the first plate C1 has two third openings K3 and the second plate C2 has two fourth openings K4 for illustration. In the embodiment of the present invention, there is no limitation on the number and area of ​​openings provided on the two plates of the storage capacitor Cst. In some embodiments, the spacing between two adjacent third openings K3 is not greater than 1 mm, and the spacing between two adjacent fourth openings K4 is not greater than 1 mm. The calculation method for the spacing between two adjacent openings can refer to the above Figure 3 Please understand the relevant instructions in the embodiments.

[0115] In some embodiments, Figure 18 A partial schematic diagram of another driving board provided in an embodiment of the present invention, Figure 19 for Figure 18The enlarged diagram of the Q9 position in the middle area. Figure 18 As shown, the driver board includes a display area AA and a non-display area NA, and the non-display area NA is provided with a plurality of fan-out lines S. One end of the fan-out line S is connected to the drive signal line in the display area AA, and the other end is connected to the pad of the non-display area BA, and the pad is used to bind the driver chip or the flexible circuit board. The fan-out line S includes a first fan-out lead S-1 and a second fan-out lead S-2. The first fan-out lead S-1 is coupled to the first drive signal line 51 extending in the first direction x in the display area AA, and the second fan-out lead S-2 is coupled to the second drive signal line 52 extending in the second direction y in the display area AA. In one embodiment, the first fan-out lead S-1 includes at least a scan fan-out line and a light-emitting control fan-out line. The scan fan-out line is coupled to the scan line in the display area AA, and the light-emitting control fan-out line is coupled to the light-emitting control line in the display area AA. The second fan-out lead S-2 includes at least a data fan-out line, which is coupled to the data line in the display area AA. Optionally, the second fan-out lead S-2 also includes a reset fan-out line, which is coupled to the reset line in the display area AA.

[0116] Figure 18 The first power supply structure 21 and the second power supply structure 22 in the display area AA are schematically shown, but the pixel areas Q in the display area AA are not marked. According to the relevant description in the above embodiment, it can be known that the first power supply structures 21 in the pixel areas Q arranged along the second direction y in the display area AA are interconnected to form a first common power supply 21-G, and the second power supply structures 22 in the pixel areas Q arranged along the second direction y are interconnected to form a second common power supply 22-G. From the entire surface of the driving board, the shape of the first common power supply 21-G in the display area AA is a strip, and the shape of the second common power supply 22-G in the display area AA is a strip. Moreover, in the display area AA, along the first direction x, the first common power supply 21-G and the second common power supply 22-G are arranged alternately. It should be noted that, Figure 18 The shapes of the first common power source 21 -G and the second common power source 22 -G in the display area AA are merely shown, and the openings provided on the first power source structure 21 and the second power source structure 22 are not shown.

[0117] The non-display area NA includes a first power supply structure 051 and a second power supply structure 052. A power supply voltage terminal ( Figure 18 (not shown), the power supply voltage terminals include a first power supply voltage terminal and a second power supply voltage terminal. The first power supply structure 051 is connected to the first power supply voltage terminal, and the second power supply structure 052 is connected to the second power supply voltage terminal. The first power supply structure 051 and the second power supply structure 052 in the non-display area NA are both large-area structures.

[0118] Depend on Figure 18It can be seen that the first power supply structure 051 is connected to the first common power supply 21-G within the display area AA. In other words, the first common power supply 21-G is connected to the first power supply voltage terminal through the first power supply structure 051 within the non-display area NA. The first power supply structure 051 and the first common power supply 21-G are an integrated structure, that is, the first power supply structure 051 and the first common power supply 21-G are made of the same layer and material. Furthermore, the first power supply structure 051 within the non-display area NA is insulated and overlapped with the multiple fan-out lines S. In one embodiment, the fan-out lines S are located on the first metal layer 011, and the first power supply structure 051 is located on the second metal layer 012.

[0119] like Figure 19 As shown, in an embodiment of the present invention, the first power supply structure 051 is provided with a fifth opening K5. The fifth opening K5 is used to partially partition the large-area first power supply structure 051 into multiple smaller structures that remain electrically connected. The presence of the fifth opening K5 reduces the cross-sectional area for charge flow within the first power supply structure 051, limiting the flow of charge between the smaller structures separated by the fifth opening K5. This effectively disperses the charge on the first power supply structure 051, reducing the amount of charge accumulated within the smaller structures and, consequently, the amount of charge accumulated locally on the first power supply structure 051. During driver board fabrication, the amount of charge accumulated within each smaller structure on the first power supply structure 051 is reduced. Lower charge levels reduce the risk of electrostatic discharge, thus reducing the risk of abnormal discharge between each smaller structure and the CVD machine, thereby reducing the risk of abnormal discharge between the first power supply structure 051 and the CVD machine. This embodiment of the present invention allows for the fabrication of an inorganic layer after the processing of the first power supply structure 051 to effectively protect the first power supply structure 051. In the direction perpendicular to the plane of the substrate 010, the first power supply structure 051 overlaps with multiple fan-out lines S. Setting the fifth opening K5 to overlap with the fan-out line can reduce the capacitance formed by the overlap of the first power supply structure 051 and the fan-out line S, thereby reducing the load on the fan-out line S.

[0120] Similarly, the second power supply structure 052 is connected to the second common power supply 22-G in the display area AA, and the second common power supply 22-G is connected to the second power supply voltage terminal through the second power supply structure 052 in the non-display area NA. The second power supply structure 052 and the first common power supply 21-G are an integrated structure, and the second power supply structure 052 and the second common power supply 22-G are located on the same layer. The second power supply structure 052 is located on the second metal layer 012. Figure 19As shown, in an embodiment of the present invention, the second power supply structure 052 is provided with a sixth opening K6. The sixth opening K6 is used to partially partition the large-area second power supply structure 052 into multiple smaller structures that remain electrically connected. The presence of the sixth opening K6 reduces the cross-sectional area for charge flow within the second power supply structure 052, limiting the flow of charge between the smaller structures separated by the sixth opening K6. This effectively disperses the charge on the second power supply structure 052, reducing the amount of charge accumulated within the smaller structures and, consequently, the amount of charge locally accumulated on the second power supply structure 052. During driver board fabrication, the amount of charge accumulated within each smaller structure on the second power supply structure 052 is reduced. Lower charge levels reduce the risk of electrostatic discharge, thus reducing the risk of abnormal discharge between each smaller structure and the CVD machine. This reduces the risk of abnormal discharge between the second power supply structure 052 and the CVD machine. This embodiment of the present invention allows for the fabrication of an inorganic layer after the processing of the second power supply structure 052 to effectively protect the second power supply structure 052. In the direction perpendicular to the plane of the substrate 010, the second power supply structure 052 overlaps with multiple fan-out lines S in the fan-out area SQ. Setting the sixth opening K6 to overlap with the fan-out line can reduce the capacitance formed by the overlap of the second power supply structure 052 and the fan-out line S, thereby further reducing the load on the fan-out line S.

[0121] In the embodiment of the present invention, the number and area of ​​the fifth opening K5 and the sixth opening K6 are not limited. In some embodiments, the spacing between two adjacent fifth openings K5 is not greater than 1 mm, and the spacing between two adjacent sixth openings K6 is not greater than 1 mm. The calculation method for the spacing between two adjacent openings can refer to the above Figure 3 Please understand the relevant instructions in the embodiments.

[0122] In some embodiments, in combination with the above Figure 6 For purposes of this embodiment, the display panel includes a first metal layer 011, a second metal layer 012, and a capacitor metal layer 013 located on one side of a substrate 010. The capacitor metal layer 013 is located between the first metal layer 011 and the second metal layer 012. A first power supply structure 051 and a second power supply structure 052 are located on the second metal layer 012, and a fan-out line S is located on the first metal layer 011.

[0123] It should be noted that the above Figure 18 The shape and extension direction of the fan-out line S are for schematic purposes only and are not intended to limit the present invention. Some segments of the fan-out line S may be straight lines or broken lines. In some embodiments, the first direction x and the second direction y are perpendicular to each other, and the extension direction of at least some segments of the fan-out line S forms a non-zero angle with the first direction x and also forms a non-zero angle with the second direction y.

[0124] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, Figure 20 A schematic diagram of a display panel provided by an embodiment of the present invention is shown in FIG. Figure 20 As shown, the display panel includes a driving board 001 provided by any embodiment of the present invention; the driving board 001 includes multiple pixel areas Q, and the display panel also includes multiple light-emitting devices P; in a direction perpendicular to the plane of the substrate, one pixel area Q overlaps with at least one light-emitting device p. Figure 20 As shown in FIG, one light emitting device P is provided in one pixel region Q. In some embodiments, two or more light emitting devices P connected in series are provided in one pixel region Q, which is not shown in the figure here.

[0125] Based on the same inventive concept, an embodiment of the present invention provides a display device, Figure 21 A schematic diagram of a display device provided by an embodiment of the present invention is shown in FIG. Figure 21 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiment and will not be repeated here. The display device provided by the embodiment of the present invention can be any device with a display function, such as a mobile phone, tablet computer, laptop computer, television, etc.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A driving plate, characterized in that: The driving board includes a plurality of pixel areas; the pixel areas include pixel circuits, a first power supply structure and a second power supply structure; the first power supply structure is used to provide a first power supply voltage, and the second power supply structure is used to provide a second power supply voltage; The first power structure and the second power structure both include a block structure, the block structure includes a first block structure, the first block structure includes at least one first opening; the first power structure and the second power structure both include the first block structure; The driving board further includes a first signal line extending along a first direction. In a direction perpendicular to the plane where the substrate is located, the first signal line overlaps with at least one of the first openings.

2. The driving plate according to claim 1, wherein: The first block structure includes at least two first openings, and a distance between two adjacent first openings is D1, wherein D1≤1 mm.

3. The driving plate according to claim 2, characterized in that: D1≤0.6mm.

4. The driving plate according to claim 1, wherein: The first signal line and the first block structure are located in different layers.

5. The driving plate according to claim 4, characterized in that: Also includes: substrate; The pixel circuit, the first power supply structure, and the second power supply structure are located on the same side of the substrate; The first signal line includes a first driving signal line, and the first driving signal line is coupled to the pixel circuit; a first metal layer and a second metal layer located on the same side of the substrate, wherein the second metal layer is located on a side of the first metal layer away from the substrate; The first signal line is located in the first metal layer, and the first block structure is located in the second metal layer.

6. The driving plate according to claim 5, characterized in that: The first opening includes a first sub-hole and a second sub-hole, and the hole area of ​​the first sub-hole is larger than the hole area of ​​the second sub-hole.

7. The driving plate according to claim 6, characterized in that: Along a direction perpendicular to the plane of the substrate, the first driving signal line overlaps with at least one of the second sub-holes.

8. The driving plate according to claim 5, characterized in that: The driving board further includes a second driving signal line extending along a second direction, the second direction intersecting the first direction; The second driving signal line and the first driving signal line are located in different layers.

9. The driving plate according to claim 8, characterized in that: The first driving signal line includes at least one of a first scanning line, a second scanning line and a light emitting control line; The second driving signal line includes a data line.

10. The driving plate according to claim 1, wherein: At least one inorganic layer is provided on a side of the block structure away from the substrate.

11. The driving plate according to claim 10, characterized in that: The inorganic layer includes a first inorganic layer in contact with the bulk structure.

12. The driving plate according to claim 10, characterized in that: The driving plate includes a first organic layer, wherein the first organic layer is located on a side of the bulk structure away from the substrate, and the first organic layer is located on a side of at least one of the inorganic layers away from the bulk structure.

13. The driving plate according to claim 1, wherein: The driving board further includes a substrate; The block structure further includes a second block structure, wherein the second block structure is located on a side of the first block structure away from the substrate; The second block structure includes at least one second opening K2.

14. The driving plate according to claim 1, wherein: The width of the block structure in any direction within the plane where the block structure is located is greater than 5 μm.

15. A driving plate, characterized in that: The driving board includes a plurality of pixel areas; the pixel areas include pixel circuits, a first power supply structure and a second power supply structure; the first power supply structure is used to provide a first power supply voltage, and the second power supply structure is used to provide a second power supply voltage; At least one of the first power structure and the second power structure comprises a block structure, the block structure comprises a first block structure, the first block structure comprises at least one first opening; At least one inorganic layer is provided on a side of the block structure away from the substrate; The driving board further includes a first signal line extending along a first direction. In a direction perpendicular to the plane where the substrate is located, the first signal line overlaps with at least one of the first openings.

16. The driving plate according to claim 15, characterized in that: The first block structure includes at least two first openings, and a distance between two adjacent first openings is D1, wherein D1≤1 mm.

17. The driving plate according to claim 16, wherein: D1≤0.6mm.

18. The driving plate according to claim 15, wherein: The first signal line and the first block structure are located in different layers.

19. The driving plate according to claim 18, wherein: Also includes: substrate; the pixel circuit, the first power supply structure, and the second power supply structure are located on the same side of the substrate; The first signal line includes a first driving signal line, and the first driving signal line is coupled to the pixel circuit; a first metal layer and a second metal layer located on the same side of the substrate, wherein the second metal layer is located on a side of the first metal layer away from the substrate; The first signal line is located in the first metal layer, and the first block structure is located in the second metal layer.

20. The driving plate according to claim 19, wherein: The first opening includes a first sub-hole and a second sub-hole, and the hole area of ​​the first sub-hole is larger than the hole area of ​​the second sub-hole.

21. The driving plate according to claim 20, characterized in that: Along a direction perpendicular to the plane of the substrate, the first driving signal line overlaps with at least one of the second sub-holes.

22. The driving plate according to claim 19, wherein: The driving board further includes a second driving signal line extending along a second direction, the second direction intersecting the first direction; The second driving signal line and the first driving signal line are located in different layers.

23. The driving plate according to claim 22, characterized in that The first driving signal line includes at least one of a first scanning line, a second scanning line and a light emitting control line; The second driving signal line includes a data line.

24. The driving plate according to claim 15, wherein: The inorganic layer includes a first inorganic layer in contact with the bulk structure.

25. The driving plate according to claim 15, characterized in that The driving plate includes a first organic layer, wherein the first organic layer is located on a side of the bulk structure away from the substrate, and the first organic layer is located on a side of at least one of the inorganic layers away from the bulk structure.

26. The driving plate according to claim 15, characterized in that The driving board further includes a substrate; The block structure further includes a second block structure, wherein the second block structure is located on a side of the first block structure away from the substrate; The second block structure includes at least one second opening K2.

27. The driving plate according to claim 15, characterized in that The width of the block structure in any direction within the plane where the block structure is located is greater than 5 μm.

28. A display panel, characterized in that: The display panel comprises a driving board as claimed in any one of claims 1 to 27; the display panel further comprises a plurality of light-emitting devices; in a direction perpendicular to the plane of the substrate, one pixel region overlaps with at least one light-emitting device.

29. The display panel according to claim 28, wherein: The light-emitting device is a micro-LED or a mini-LED.

30. A display device, characterized in that: A display panel comprising any one of claims 28 to 29.

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