Light emitting diode chip, preparation method thereof and display device

Abstract

The embodiment of the present disclosure provides a light emitting diode chip, a preparation method thereof and a display device, and belongs to the technical field of semiconductors. The preparation method comprises the following steps: forming a connection electrode layer on each light emitting unit, and the first connection electrode on each light emitting unit points to the second connection electrode along a first direction, the included angle between the first direction and the flat side is 30-60 degrees, and the first direction is the length direction of the rectangular projection; or the first connection electrode on a part of the light emitting units points to the second connection electrode along a second direction, the second direction is the length direction of the rectangular projection, and the first connection electrode on another part of the light emitting units points to the second connection electrode along a third direction, and the third direction is opposite to the second direction; and the sapphire wafer is cracked along the cutting path to obtain a plurality of light emitting diode chips. The embodiment of the present disclosure can make the light emitting pattern of the LED chip or the light pattern of the display device using the LED chip more symmetrical.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode chip, a preparation method thereof, and a display device. Background Art

[0002] Light emitting diodes (LEDs) have been widely used in display devices due to their small size, long service life, rich colors, and low energy consumption.

[0003] In the related art, the preparation method of LED chips includes: forming a plurality of light-emitting units on a sapphire wafer, the sapphire wafer having connected flat edges and arc edges, the orthographic projection of the light-emitting units on the sapphire wafer being a rectangular projection, the plurality of light-emitting units being distributed at intervals, and a cutting path being formed between adjacent light-emitting units; forming a connecting electrode layer on each light-emitting unit, the connecting electrode layer including a first connecting electrode and a second connecting electrode, the first connecting electrode and the second connecting electrode on the same light-emitting unit being arranged along a first direction, the first direction being parallel to or perpendicular to the flat edge, and the first direction being the length direction of the rectangular projection; splitting the sapphire wafer along the cutting path to obtain a plurality of LED chips.

[0004] However, affected by the sapphire lattice, scratching the sapphire wafer along the cutting path will produce oblique cracks on the side walls of the sapphire substrate, that is, the side walls of the sapphire substrate are not completely perpendicular to the bottom surface of the sapphire substrate, and the first direction is parallel or perpendicular to the flat edge, which will make the oblique crack angles of the side walls of the sapphire substrate in the multiple LED chips obtained by scratching (that is, the angle of the side wall deviating from the vertical plane of the bottom surface) larger, and the oblique crack directions are the same relative to the direction from the first connecting electrode to the second connecting electrode, which will cause asymmetric light patterns of the LED chips or asymmetric light patterns of display devices using LED chips. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode chip, a method for manufacturing the same, and a display device, which can make the light pattern of the LED chip or the light pattern of the display device using the LED chip more symmetrical. The technical solution is as follows:

[0006] On the one hand, a method for preparing a light-emitting diode chip is provided, comprising: forming a plurality of light-emitting units on a sapphire wafer, the sapphire wafer having a connected flat edge and an arc edge, the orthographic projection of the light-emitting unit on the sapphire wafer being a rectangular projection, the plurality of light-emitting units being distributed at intervals, and a cutting path being formed between adjacent light-emitting units; forming a connecting electrode layer on each of the light-emitting units, the connecting electrode layer comprising a first connecting electrode and a second connecting electrode, the first connecting electrode on each of the light-emitting units pointing to the second connecting electrode along a first direction, the angle between the first direction and the flat edge being 30° to 60°, the first direction being the length direction of the rectangular projection; or, the first connecting electrode on a portion of the light-emitting units pointing to the second connecting electrode along a second direction, the second direction being the length direction of the rectangular projection, and the first connecting electrode on another portion of the light-emitting units pointing to the second connecting electrode along a third direction, the third direction being opposite to the second direction; and splitting the sapphire wafer along the cutting path to obtain a plurality of light-emitting diode chips.

[0007] Optionally, the first connecting electrode on each of the light-emitting units points to the second connecting electrode along the first direction; the forming of a connecting electrode layer on each of the light-emitting units includes: coating a layer of photoresist material on the sapphire wafer and the light-emitting unit; exposing the photoresist material under the shielding of a first photoresist plate, the first photoresist plate having a plurality of first photoresist patterns arranged in an array, the first photoresist pattern including a first connecting electrode pattern and a second connecting electrode pattern, the first connecting electrode pattern in the first photoresist pattern pointing to the second connecting electrode pattern along the first direction; developing the photoresist material to obtain a first photoresist layer; forming an electrode material layer on the light-emitting unit and the first photoresist layer; removing the first photoresist layer and the electrode material layer on the first photoresist layer to obtain the connecting electrode layer.

[0008] Optionally, the first connecting electrode on a portion of the light-emitting units points to the second connecting electrode along the second direction, and the first connecting electrode on another portion of the light-emitting units points to the second connecting electrode along the third direction, and the two portions of the light-emitting units are respectively located on both sides of the perpendicular midline of the flat edge.

[0009] Optionally, forming a connecting electrode layer on each of the light-emitting units includes: coating a layer of photoresist material on the sapphire wafer and the light-emitting unit; exposing the photoresist material under the shielding of a second photoresist plate, the second photoresist plate having a plurality of second photoresist patterns arranged in an array and a plurality of third photoresist patterns arranged in an array, the plurality of second photoresist patterns and the plurality of third photoresist patterns being respectively located on both sides of a center line of the second photoresist plate, the second photoresist pattern including a first connecting electrode pattern and a second connecting electrode pattern, the first connecting electrode pattern in the second photoresist pattern pointing to the second connecting electrode pattern along the second direction, the third photoresist pattern including the first connecting electrode pattern and the second connecting electrode pattern, the first connecting electrode pattern in the third photoresist pattern pointing to the second connecting electrode pattern along the third direction; developing the photoresist material to obtain a second photoresist layer; forming an electrode material layer on the light-emitting unit and the second photoresist layer; removing the second photoresist layer and the electrode material layer on the second photoresist layer to obtain the connecting electrode layer.

[0010] On the other hand, a method for preparing a light-emitting diode chip is provided, comprising: forming a plurality of light-emitting units on a first sapphire wafer and a second sapphire wafer, respectively, the first sapphire wafer having a connected flat edge and an arc edge, the second sapphire wafer having a connected flat edge and the arc edge, the orthographic projection of the light-emitting unit on the first sapphire wafer on the first sapphire wafer and the orthographic projection of the light-emitting unit on the second sapphire wafer on the second sapphire wafer both being rectangular projections, the plurality of light-emitting units being distributed at intervals, and a cutting path being formed between adjacent light-emitting units; forming a connecting electrode layer on each of the light-emitting units, the connecting electrode layer comprising a first connecting electrode and a second connecting electrode, the first connecting electrode on each light-emitting unit on the first sapphire wafer pointing to the second connecting electrode along a second direction, which is the length direction of the rectangular projection, and the first connecting electrode on each light-emitting unit on the second sapphire wafer pointing to the second connecting electrode along a third direction, which is opposite to the second direction; and splitting the first sapphire wafer and the second sapphire wafer along the cutting path to obtain a plurality of light-emitting diode chips.

[0011] Optionally, the forming the connection electrode layer on each of the light emitting units respectively comprises: coating a layer of photoresist material on the first sapphire wafer, on the light emitting units on the first sapphire wafer, on the second sapphire wafer and on the light emitting units on the second sapphire wafer respectively; exposing the photoresist material on the first sapphire wafer and on the light emitting units on the first sapphire wafer under the shielding of a third photoetching plate, and exposing the photoresist material on the second sapphire wafer and on the light emitting units on the second sapphire wafer under the shielding of a fourth photoetching plate, the third photoetching plate has a plurality of second photoetching patterns arranged in an array, the second photoetching patterns comprise first connection electrode patterns and second connection electrode patterns, the first connection electrode patterns in the second photoetching patterns point to the second connection electrode patterns along the second direction, the fourth photoetching plate has a plurality of third photoetching patterns arranged in an array, the third photoetching patterns comprise the first connection electrode patterns and the second connection electrode patterns, the first connection electrode patterns in the third photoetching patterns point to the second connection electrode patterns along the third direction; developing the photoresist material to obtain a third photoresist layer and a fourth photoresist layer respectively; forming an electrode material layer on the third photoresist layer and the fourth photoresist layer; removing the electrode material layer on the third photoresist layer and the fourth photoresist layer to obtain the connection electrode layer.

[0012] Optionally, the second direction is parallel or perpendicular to the flat side.

[0013] Optionally, the light emitting unit comprises a light emitting structure and a transparent conductive layer which are sequentially stacked, the light emitting structure comprises a first semiconductor layer, a light emitting layer and a second semiconductor layer which are sequentially stacked, the light emitting structure has a mesa extending from a surface of the second semiconductor layer away from the light emitting layer to the first semiconductor layer; the transparent conductive layer is located on the second semiconductor layer and connected with the second semiconductor layer; the first connection electrode is located on the mesa and connected with the first semiconductor layer; the second connection electrode is located on a side of the transparent conductive layer away from the second semiconductor layer and connected with the transparent conductive layer; after the connection electrode layer is formed, the method further comprises: forming a passivation layer on the connection electrode layer, the passivation layer covers the connection electrode layer, the passivation layer has a first through hole exposing the first semiconductor layer and a second through hole exposing the transparent conductive layer; forming a pad electrode layer on the passivation layer, the pad electrode layer comprises a first pad electrode and a second pad electrode, the first pad electrode is connected with the first connection electrode through the first through hole, and the second pad electrode is connected with the second connection electrode through the second through hole.

[0014] In another aspect, a light emitting diode chip is provided, wherein the light emitting diode chip is prepared by any of the aforementioned preparation methods.

[0015] On the other hand, a display device is provided, comprising a substrate and a plurality of light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array on the substrate, and at least one light-emitting diode chip among the plurality of light-emitting diode chips is prepared by any of the aforementioned preparation methods.

[0016] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects:

[0017] In the embodiment of the present disclosure, the first connecting electrode points to the second connecting electrode along a first direction, and the angle between the first direction and the flat edge is 30° to 60°. The first direction is the length direction of the rectangular projection. Since the oblique crack angle of the sapphire substrate is affected by the sapphire lattice and the scratching direction, the oblique crack angle of the side wall of the sapphire substrate in the LED chip obtained by scratching along the cutting path is smaller, the light pattern of the LED chip is more symmetrical, and the light pattern of the display device using the LED chip is more symmetrical. Alternatively, the first connecting electrode on a part of the light-emitting units points to the second connecting electrode along the second direction, and the first connecting electrode on another part of the light-emitting units points to the second connecting electrode along the third direction; or, the first connecting electrode on each light-emitting unit on the first sapphire wafer points to the second connecting electrode along the second direction, and the first connecting electrode on each light-emitting unit on the second sapphire wafer points to the second connecting electrode along the third direction, the second direction is the length direction of the rectangular projection, and the third direction is opposite to the second direction. In this way, among the multiple LED chips obtained by splitting along the cutting path, there are two types of LED chips with opposite oblique crack directions on the side walls of the sapphire substrate relative to the direction from the first connecting electrode to the second connecting electrode. Applying the two LED chips with opposite oblique crack directions to the same display device can make the light pattern of the display device more symmetrical. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 This is a flow chart of a method for preparing an LED chip provided by an embodiment of the present disclosure;

[0020] Figure 2 This is a flow chart of another method for preparing an LED chip provided by an embodiment of the present disclosure;

[0021] Figure 3is a structural schematic diagram in an LED chip preparation process provided by an embodiment of the present disclosure;

[0022] Figure 4 is a structural schematic diagram of a first photolithography plate provided by an embodiment of the present disclosure;

[0023] Figure 5 is a structural schematic diagram of an LED chip provided by an embodiment of the present disclosure;

[0024] Figure 6 is a top view of an LED chip provided by an embodiment of the present disclosure;

[0025] Figure 7 is a structural schematic diagram in another LED chip preparation process provided by an embodiment of the present disclosure;

[0026] Figure 8 is a structural schematic diagram in another LED chip preparation process provided by an embodiment of the present disclosure;

[0027] Figure 9 is a structural schematic diagram in another LED chip preparation process provided by an embodiment of the present disclosure;

[0028] Figure 10 is a light pattern schematic diagram of an LED chip provided by an embodiment of the present disclosure;

[0029] Figure 11 is a flow chart of another LED chip preparation method provided by an embodiment of the present disclosure;

[0030] Figure 12 is a structural schematic diagram in another LED chip preparation process provided by an embodiment of the present disclosure;

[0031] Figure 13 is a structural schematic diagram of a second photolithography plate provided by an embodiment of the present disclosure;

[0032] Figure 14 is a structural schematic diagram in another LED chip preparation process provided by an embodiment of the present disclosure;

[0033] Figure 15 is a structural schematic diagram of another LED chip provided by an embodiment of the present disclosure;

[0034] Figure 16 is a light pattern schematic diagram of another LED chip and display device provided by an embodiment of the present disclosure;

[0035] Figure 17 is a flow chart of another LED chip preparation method provided by an embodiment of the present disclosure;

[0036] Figure 18is a flow chart of another method for manufacturing an LED chip provided by an embodiment of the present disclosure.

[0037] Figure 19 is a structural schematic diagram in a manufacturing process of an LED chip provided by an embodiment of the present disclosure.

[0038] Figure 20 is a structural schematic diagram of a third photolithography plate and a fourth photolithography plate provided by an embodiment of the present disclosure.

[0039] Figure 21 is a structural schematic diagram in a manufacturing process of an LED chip provided by an embodiment of the present disclosure.

[0040] Reference signs:

[0041] 10: sapphire wafer; 101: first sapphire wafer; 102: second sapphire wafer; 11: flat edge; 12: circular arc edge; 13: sapphire substrate; 20: light emitting unit; 21: light emitting structure; 211: first semiconductor layer; 212: light emitting layer; 213: second semiconductor layer; 214: mesa; 22: cutting path; 23: transparent conductive layer; 30: first photolithography plate; 301: first photolithography pattern; 3011: first connecting electrode pattern; 3012: second connecting electrode pattern; 31: second photolithography plate; 311: second photolithography pattern; 312: third photolithography pattern; 32: third photolithography plate; 33: fourth photolithography plate; 40: connecting electrode layer; 41: first connecting electrode; 42: second connecting electrode; 50: passivation layer; 60: pad electrode layer; 61: first pad electrode; 62: second pad electrode; 70: first via hole; 71: second via hole. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in further detail below with reference to the drawings.

[0043] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "one" or "a" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" and similar words mean that the elements or objects preceding "include" encompass the elements or objects listed following "include" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. Furthermore, "A and / or B" indicates that there are three situations: A, B, and A and B.

[0044] Figure 1 This is a flow chart of a method for preparing an LED chip provided by an embodiment of the present disclosure. This method is applicable to LED chips of various sizes or types, such as mini-LED chips and micro-LED chips. Figure 1 As shown, the preparation method comprises:

[0045] In step S1001 , a plurality of light-emitting units are formed on a sapphire wafer.

[0046] The sapphire wafer has connected flat edges and arc edges, the orthographic projection of the light-emitting unit on the sapphire wafer is a rectangular projection, multiple light-emitting units are distributed at intervals, and cutting paths are formed between adjacent light-emitting units.

[0047] Here, the rectangular projection not only refers to a projection with a rectangular outer contour, but also refers to a projection with an outer contour that is approximately rectangular, for example, a rounded rectangular projection.

[0048] In step S1002 , a connection electrode layer is formed on each light emitting unit.

[0049] The connection electrode layer comprises a first connection electrode and a second connection electrode, the first connection electrode on each light emitting unit points to the second connection electrode along a first direction, an included angle between the first direction and the flat side is 30° to 60°, and the first direction is a length direction of the rectangular projection; or, the first connection electrode on a part of the light emitting units points to the second connection electrode along a second direction, the second direction is a length direction of the rectangular projection, and the first connection electrode on another part of the light emitting units points to the second connection electrode along a third direction, the third direction is opposite to the second direction.

[0050] It should be noted that when the first direction intersects with the flat side and is not perpendicular to each other, there are acute angles and obtuse angles, and the acute angle is used to represent the included angle between the first direction and the flat side in the embodiment of the present disclosure.

[0051] In step S1003, the sapphire wafer is cracked along the cutting path to obtain a plurality of light emitting diode chips.

[0052] In the embodiment of the present disclosure, the first connection electrode points to the second connection electrode along the first direction, the included angle between the first direction and the flat side is 30° to 60°, and the first direction is the length direction of the rectangular projection. Since the beveling angle of the sapphire substrate is affected by the sapphire lattice and the cracking direction, the cracking along the cutting path can reduce the probability that the lattice plane prone to beveling of the sapphire is concentrated on the long side or the short side of the sapphire substrate, and the beveling is distributed to each side wall of the sapphire substrate, so that the beveling angle of the side wall of the sapphire substrate in the obtained LED chip is smaller, the light pattern of the LED chip is more symmetrical, and the light pattern of the display device using the LED chip is more symmetrical. Alternatively, the first connection electrode on a part of the light emitting units points to the second connection electrode along the second direction, the second direction is the length direction of the rectangular projection, and the first connection electrode on another part of the light emitting units points to the second connection electrode along the third direction, the third direction is opposite to the second direction. In the plurality of LED chips obtained by cracking along the cutting path, there are two kinds of LED chips with opposite beveling directions of the side wall of the sapphire substrate relative to the direction from the first connection electrode to the second connection electrode. The two kinds of LED chips with opposite beveling directions are applied to the same display device, so that the light pattern of the display device is more symmetrical.

[0053] Figure 2 is another flow chart of a preparation method of an LED chip provided by the embodiment of the present disclosure. As shown in the figure, the preparation method comprises: Figure 2

[0054] In step S2001, a plurality of light emitting units are formed on the sapphire wafer.

[0055] Figure 3 is a structural schematic diagram in the preparation process of an LED chip provided by the embodiment of the present disclosure. As shown in the figure, Figure 3 ​As shown, the sapphire wafer 10 has a connected flat edge 11 and an arc edge 12. The orthographic projection of the light-emitting unit 20 on the sapphire wafer 10 is a rectangular projection. The plurality of light-emitting units 20 are spaced apart, and a cutting path 22 is formed between adjacent light-emitting units 20. The first direction x1 is the length direction of the rectangular projection.

[0056] In step S2002, a layer of photoresist material is coated on the sapphire wafer and the light-emitting unit.

[0057] Illustratively, the photoresist material may be a positive photoresist or a negative photoresist.

[0058] In step S2003, the photoresist material is exposed under the shielding of the first photoresist plate.

[0059] Figure 4 Schematic diagram of the structure of a first photoresist provided by an embodiment of the present disclosure. Figure 4 As shown, the first photolithography plate 30 has a plurality of first photolithography patterns 301 arranged in an array. The first photolithography pattern 301 includes a first connection electrode pattern 3011 and a second connection electrode pattern 3012. In the first photolithography pattern 301, the first connection electrode pattern 3011 points to the second connection electrode pattern 3012 along the first direction x1.

[0060] like Figure 3 As shown, the angle α between the first direction x1 and the flat edge 11 is 30° to 60°.

[0061] For example, the angle α between the first direction x1 and the flat edge 11 may be 30°, 45°, or 60°.

[0062] For example, the first photoresist plate 30 and / or the sapphire wafer 10 may be rotated so that α is within this range.

[0063] In step S2004 , the photoresist material is developed to obtain a first photoresist layer.

[0064] The pattern of the photoresist material removed region in the first photoresist layer is completely identical to the first photoresist pattern 301 .

[0065] In step S2005 , an electrode material layer is formed on the light emitting unit and the first photoresist layer.

[0066] For example, the electrode material layer may be formed by deposition under the cover of the first photoresist layer. The electrode material layer may be deposited on the first photoresist layer and on the light emitting units 20 exposed by the photoresist pattern of the first photoresist layer.

[0067] In step S2006 , the first photoresist layer and the electrode material layer on the first photoresist layer are removed to obtain a connecting electrode layer.

[0068] Through the above steps S2002 to S2006 , the connection electrode layer 40 can be formed on each light emitting unit 20 .

[0069] Figure 5 This is a schematic structural diagram of an LED chip provided by an embodiment of the present disclosure. Figure 6 FIG. 1 is a top view of an LED chip provided by an embodiment of the present disclosure. Figure 5 and Figure 6 As shown, the light emitting unit 20 includes a light emitting structure 21 and a transparent conductive layer 23 stacked in sequence. The light emitting structure 21 includes a first semiconductor layer 211, a light emitting layer 212, and a second semiconductor layer 213 stacked in sequence. The light emitting structure 21 has a mesa (MESA) 214 extending from a surface of the second semiconductor layer 213 away from the light emitting layer 212 toward the first semiconductor layer 211.

[0070] Optionally, the first semiconductor layer 211 may be an N-type GaN layer, and the second semiconductor layer 213 may be a P-type GaN layer.

[0071] Exemplarily, the first semiconductor layer 211 is a Si-doped GaN layer, and the second semiconductor layer 213 is a Mg-doped GaN layer.

[0072] Optionally, the light-emitting layer 212 includes multiple pairs of alternately stacked InGaN layers and GaN layers. Depending on the wavelength range of the LED chip, the light-emitting layer 212 can be made of different materials. For example, the light-emitting layer 212 of a blue-green LED chip can be made of alternately stacked InGaN layers and GaN layers, while the light-emitting layer 212 of a red LED chip can be made of alternately stacked InGaAs layers and GaAs layers.

[0073] Exemplarily, the light emitting layer 212 includes 3 to 8 pairs of alternately stacked InGaN layers and GaN layers, for example, 5 pairs of alternately stacked InGaN layers and GaN layers, and other numbers of pairs are also possible, which is not limited in the present disclosure.

[0074] Exemplarily, the transparent conductive layer 23 is located on the second semiconductor layer 213 and connected to the second semiconductor layer 213 .

[0075] The transparent conductive layer 23 may also be called a current spreading layer. The transparent conductive layer 23 can make the current spread laterally to various regions of the second semiconductor layer 213 to ensure the luminous efficiency of the LED chip.

[0076] Optionally, the transparent conductive layer 23 may be an indium tin oxide (ITO) layer. ITO has good transmittance and low resistivity, thus ensuring the light output effect of the LED chip, and also facilitates carrier conduction and improves carrier injection efficiency.

[0077] like Figure 3 、 Figure 5 and Figure 6 As shown, the connecting electrode layer 40 includes a first connecting electrode 41 and a second connecting electrode 42. The first connecting electrode 41 on each light-emitting unit 20 points to the second connecting electrode 42 along the first direction x1. The first connecting electrode 41 is located on the mesa 214 and connected to the first semiconductor layer 211. The second connecting electrode 42 is located on a side of the transparent conductive layer 23 away from the second semiconductor layer 213 and connected to the transparent conductive layer 23.

[0078] Figure 7 This is a structural schematic diagram of another LED chip preparation process provided by an embodiment of the present disclosure. Figure 7 and Figure 3 The difference is that Figure 7 The first direction x1 in Figure 3 The first direction x1 in is opposite.

[0079] Figure 8 This is a structural schematic diagram of another LED chip preparation process provided by an embodiment of the present disclosure. Figure 8 and Figure 3 The difference is that Figure 8 The first direction x1 in Figure 3 The first direction x1 in the figure is symmetrical about the perpendicular bisector of the flat side 11 .

[0080] Figure 9 This is a structural schematic diagram of another LED chip preparation process provided by an embodiment of the present disclosure. Figure 9 and Figure 8 The difference is that Figure 9 The first direction x1 in Figure 8 The first direction x1 in is opposite.

[0081] In step S2007 , a passivation layer is formed on the connection electrode layer.

[0082] like Figure 3 、 Figure 5 and Figure 6As shown, the passivation layer 50 covers the connecting electrode layer 40. The passivation layer 50 has a first through hole 70 that exposes the first semiconductor layer 211 and a second through hole 71 that exposes the transparent conductive layer 23. Here, covering means covering both the surface of the film layer and the sidewalls of the film layer. The passivation layer 50 covers both the surface of the connecting electrode layer 40 away from the light-emitting unit 20 and the sidewalls of the connecting electrode layer 40. In other words, the passivation layer 50 covers the underlying connecting electrode layer 40. In this way, the passivation layer 50 can protect the potentially exposed surfaces of the LED chip, reduce the impact of mechanical damage or chemical corrosion on the LED chip, and ensure the reliability of the LED chip.

[0083] Optionally, the passivation layer 50 is a distributed Bragg reflector (DBR) layer, which not only performs a passivation function but also reflects light emitted from the light-emitting layer 212 toward the passivation layer 50 to the substrate, thereby improving the light extraction effect of the LED chip.

[0084] Exemplarily, the DBR layer includes a plurality of periodically alternately stacked SiO2 layers and TiO2 layers, and the number of periods of the DBR layer may be 20 to 50. For example, the DBR layer may include 30 periods of alternately stacked SiO2 layers and TiO2 layers.

[0085] In other embodiments, the passivation layer 50 may be at least one of a SiO2 layer, an Al2O3 layer, a SiN layer, or a SiON layer. These materials have good protective properties and can better protect the LED chip. In addition, these materials have good light transmittance and can reduce the light absorption effect of the passivation layer 50, thereby improving the light extraction efficiency of the LED chip.

[0086] In step S2008 , a pad electrode layer is formed on the passivation layer.

[0087] Illustratively, the pad electrode layer 60 includes a first pad electrode 61 and a second pad electrode 62. The first pad electrode 61 is connected to the first connection electrode 41 via a first through-hole 70, and the second pad electrode 62 is connected to the second connection electrode 42 via a second through-hole 71. The pad electrode layer 60 facilitates connection of the LED chip to external electrical signals.

[0088] In step S2009, a laser is used to cleave the sapphire wafer along the dicing lines from the surface of the sapphire wafer away from the light emitting unit.

[0089] For example, a stealth scribing technique can be used to scribble from the surface of the sapphire wafer 10 away from the light-emitting unit 20. This technique focuses a laser into the interior of the sapphire wafer 10, instantly heating the material at the laser focus to a high temperature and vaporizing it. The material then rapidly cools, leaving cavities within the sapphire wafer 10. Multiple cavities are spaced apart along the extension direction of the same scribe line 22. This facilitates the formation of multiple LED chips by scribing, and the oblique crack angles on the sidewalls of the sapphire substrate 13 of the LED chips are relatively small.

[0090] For example, in the stealth cutting and scribing technology, the laser can be focused at different depths inside the sapphire wafer 10, that is, the scribing can be performed using a multi-focus cutting technology.

[0091] For example, the sapphire substrate 13 may be a patterned sapphire substrate having a plurality of protrusions arranged in an array on its surface.

[0092] Through the above steps S2001 to S2009, multiple Figure 5 and Figure 6 The LED chip shown.

[0093] Figure 5 In the figure, the solid line of the side wall of the sapphire substrate 13 indicates that the Figure 2 The side wall state of the LED chip prepared by the preparation method shown in FIG. The dotted line represents the side wall state of the LED chip obtained by the preparation method in the related art. Figure 2 The difference between the manufacturing method shown is that in the related art, when manufacturing LED chips, the arrangement direction of the first connecting electrode and the second connecting electrode on each light-emitting unit is perpendicular to the flat edge of the sapphire wafer. Figure 5 As shown by the dotted line in FIG, in the related art, the angle at which the side wall deviates from the vertical plane of the bottom surface is β1; Figure 5 As shown by the solid line in Figure 2 In the LED chip prepared by the preparation method shown, the angle at which the side wall of the sapphire substrate 13 deviates from the vertical plane of the bottom surface of the sapphire substrate 13 is β2, and β2 is significantly smaller than β1. That is, in the LED chip obtained by using this preparation method, the oblique crack angle of the side wall of the sapphire substrate 13 is smaller.

[0094] Figure 10 This is a schematic diagram of the light pattern of an LED chip provided in an embodiment of the present disclosure. Figure 10 The solid curve in the figure represents the Figure 2 The light type of the LED chip prepared by the preparation method shown is Figure 10 The dotted curve in FIG represents the light type of the LED chip prepared by the preparation method in the related art. Figure 10As shown in the middle dashed curve, in the related art, the radiance of the LED chip at a 90° azimuth angle measured at a positive pitch angle position is almost always higher than the radiance at a 90° azimuth angle measured at a negative pitch angle position of the same degree, and the dashed curve is obviously lower on the left and higher on the right; Figure 10 As shown by the solid line curve, Figure 2 The LED chips prepared by the preparation method shown have roughly the same radiance at a 90° azimuth angle measured at the same positive and negative pitch angle positions, and the solid line curve is roughly symmetrical about the 0° pitch angle position, which means that the light pattern of the LED chips obtained by this preparation method is more symmetrical.

[0095] Figure 11 This is a flow chart of another method for preparing an LED chip provided by the embodiment of the present disclosure. Figure 11 As shown, the preparation method comprises:

[0096] In step S3001, a plurality of light-emitting units are formed on a sapphire wafer.

[0097] Figure 12 This is a structural diagram of another LED chip manufacturing process provided by the embodiment of the present disclosure. Figure 12 As shown, the sapphire wafer 10 has a connected flat edge 11 and an arc edge 12. The orthographic projection of the light-emitting unit 20 on the sapphire wafer 10 is a rectangular projection. The plurality of light-emitting units 20 are spaced apart, and a cutting path 22 is formed between adjacent light-emitting units 20. The second direction x2 is the length direction of the rectangular projection.

[0098] Exemplarily, the second direction x2 is perpendicular to the flat edge 11. This facilitates alignment of the photomask and the sapphire wafer 10 during the photolithography step, which is beneficial to production.

[0099] In step S3002, a layer of photoresist material is coated on the sapphire wafer and the light-emitting unit.

[0100] In step S3003, the photoresist material is exposed under the shielding of the second photoresist.

[0101] Figure 13 Schematic diagram of the structure of a second photoresist provided by an embodiment of the present disclosure. Figure 13As shown, the second photoresist plate 31 has a plurality of second photoresist patterns 311 arranged in an array and a plurality of third photoresist patterns 312 arranged in an array. The plurality of second photoresist patterns 311 and the plurality of third photoresist patterns 312 are respectively located on either side of a center line of the second photoresist plate 31. The second photoresist pattern 311 includes a first connection electrode pattern 3011 and a second connection electrode pattern 3012. In the second photoresist pattern 311, the first connection electrode pattern 3011 points toward the second connection electrode pattern 3012 along a second direction x2. The third photoresist pattern 312 includes a first connection electrode pattern 3011 and a second connection electrode pattern 3012. In the third photoresist pattern 312, the first connection electrode pattern 3011 points toward the second connection electrode pattern 3012 along a third direction x3. The third direction x3 is opposite to the second direction x2.

[0102] In step S3004, the photoresist material is developed to obtain a second photoresist layer.

[0103] The pattern of the photoresist material removal area in the second photoresist layer is the same as the second photoresist pattern or the third photoresist pattern.

[0104] In step S3005 , an electrode material layer is formed on the light emitting unit and the second photoresist layer.

[0105] Illustratively, the electrode material layer may be formed by deposition under the cover of the second photoresist layer.

[0106] In step S3006 , the second photoresist layer and the electrode material layer on the second photoresist layer are removed to obtain a connecting electrode layer.

[0107] Through the above steps S3002 to S3006 , the connection electrode layer 40 can be formed on each light emitting unit 20 .

[0108] Figure 14 This is a structural diagram of another LED chip manufacturing process provided by the embodiment of the present disclosure. Figure 14 As shown, the second direction x2 is parallel to the flat edge 11. This also facilitates alignment of the photoresist plate and the sapphire wafer 10 during the photolithography step, which is beneficial to production.

[0109] In other embodiments, the angle between the second direction x2 and the flat edge 11 may be 30° to 60°.

[0110] like Figure 12 and Figure 14As shown, the first connection electrodes 41 on a portion of the light-emitting units 20 point toward the second connection electrodes 42 along the second direction x2, while the first connection electrodes 41 on another portion of the light-emitting units 20 point toward the second connection electrodes 42 along the third direction x3. The two portions of light-emitting units 20 are located on either side of the perpendicular midline of the flat edge 11. This facilitates the production of the second photoresist plate and facilitates subsequent differentiation of LED chips with oppositely directed oblique cracks on the sidewalls of the two sapphire substrates.

[0111] Exemplarily, the two light emitting units 20 are symmetrical about the perpendicular midline of the flat side 11 .

[0112] In other embodiments, the two parts of light-emitting units 20 can be arranged in an array and alternately arranged in the row direction; or the two parts of light-emitting units 20 can be arranged in an array and alternately arranged in the column direction; or the two parts of light-emitting units 20 can be arranged in an array and randomly distributed, etc., and the present disclosure does not limit this.

[0113] For example, the two parts have the same number of light-emitting units 20. In other embodiments, the two parts may have different numbers of light-emitting units 20, which is not limited in the present disclosure.

[0114] In step S3007 , a passivation layer is formed on the connection electrode layer.

[0115] In step S3008 , a pad electrode layer is formed on the passivation layer.

[0116] In step S3009, a laser is used to cleave the sapphire wafer along the dicing lines from the surface of the sapphire wafer away from the light emitting unit.

[0117] It should be noted that, among the above steps S3001 to S3009, only steps S3001 to S3006 are significantly different from steps S2001 to S2006. Figure 2 Detailed description of the related embodiments is omitted here.

[0118] Figure 15 This is a schematic diagram of the structure of another LED chip provided by the embodiment of the present disclosure. Figure 11 Prepared by the preparation method shown, Figure 15 (a) shows an LED chip in which the first connecting electrode 41 points toward the second connecting electrode 42 along the second direction, and the oblique crack direction of the side wall of the sapphire substrate 13 in the LED chip is to the left. Figure 15 (b) is an LED chip in which the first connecting electrode 41 points to the second connecting electrode 43 along the third direction, and the oblique crack direction of the side wall of the sapphire substrate 13 in the LED chip is rightward. Figure 15In the figure, relative to the direction from the first connection electrode 41 to the second connection electrode 42, the oblique crack directions of the sidewalls of the sapphire substrate 13 in (a) and (b) are opposite.

[0119] Through the above steps S3001 to S3009, multiple Figure 15 The LED chip shown.

[0120] Figure 16 This is a schematic diagram of the light pattern of another LED chip provided in an embodiment of the present disclosure. Figure 16 (a) is Figure 15 The light pattern of the LED chip shown in (a) is Figure 16 (b) is Figure 15 The light pattern of the LED chip shown in (b) is that the oblique crack directions of the side walls of the sapphire substrate of the two parts of the LED chip are opposite relative to the direction from the first connecting electrode to the second connecting electrode. Figure 16 The radiance curves of the LED chips at 90° azimuth measured at different pitch angles of (a) and (b) are roughly symmetrical about the 0° pitch angle position. The curve in (a) is low on the left and high on the right, while the curve in (b) is high on the left and low on the right, which is Figure 16 The light patterns of the LED chips in (a) and (b) are roughly opposite. Figure 16 (c) is the superimposed light pattern of (a) and (b). The radiance at a 90° azimuth angle measured at the same positive and negative pitch angles is roughly the same, which means that the superimposed light pattern is relatively symmetrical. Therefore, applying these two LED chips with opposite oblique crack directions to the same display device can make the light pattern of the display device more symmetrical.

[0121] Figure 17 This is a flow chart of another method for preparing an LED chip provided by an embodiment of the present disclosure. This preparation method is applicable to LED chips of various sizes or types, such as Mini-LED chips and Micro-LED chips. Figure 17 As shown, the preparation method comprises:

[0122] In step S4001, a plurality of light-emitting units are formed on a first sapphire wafer and a second sapphire wafer, respectively.

[0123] Among them, the first sapphire wafer has a connected flat edge and an arc edge, the second sapphire wafer has a connected flat edge and an arc edge, the orthographic projection of the light-emitting unit on the first sapphire wafer on the first sapphire wafer and the orthographic projection of the light-emitting unit on the second sapphire wafer on the second sapphire wafer are both rectangular projections, multiple light-emitting units are distributed at intervals, and cutting roads are formed between adjacent light-emitting units.

[0124] In step S4002 , a connection electrode layer is formed on each light emitting unit.

[0125] The connecting electrode layer includes a first connecting electrode and a second connecting electrode. The first connecting electrode on each light-emitting unit on the first sapphire wafer points to the second connecting electrode along a second direction, which is the length direction of the rectangular projection. The first connecting electrode on each light-emitting unit on the second sapphire wafer points to the second connecting electrode along a third direction, which is opposite to the second direction.

[0126] In step S4003, the first sapphire wafer and the second sapphire wafer are cleaved along the dicing lines to obtain a plurality of light emitting diode chips.

[0127] In the embodiment of the present disclosure, the first connecting electrode on each light-emitting unit on the first sapphire wafer points to the second connecting electrode along the second direction, which is the length direction of the rectangular projection. The first connecting electrode on each light-emitting unit on the second sapphire wafer points to the second connecting electrode along the third direction, which is opposite to the second direction. In this way, among the multiple LED chips obtained by splitting along the cutting path, there are two types of LED chips with opposite oblique crack directions on the side walls of the sapphire substrate relative to the direction from the first connecting electrode to the second connecting electrode. Applying the two LED chips with opposite oblique crack directions to the same display device can make the light pattern of the display device more symmetrical. In addition, the same photolithography plate can be used for different sapphire wafers in the photolithography step. Rotating the photolithography plate and / or rotating the sapphire wafer so that the first connecting electrode points to the second connecting electrode along the second direction or the third direction can make the light pattern of the display device more symmetrical without changing the photolithography plate structure or the LED chip structure.

[0128] Figure 18 This is a flow chart of another method for preparing an LED chip provided by the embodiment of the present disclosure. Figure 18 As shown, the preparation method comprises:

[0129] In step S5001, a plurality of light-emitting units are formed on a first sapphire wafer and a second sapphire wafer, respectively.

[0130] Figure 19 This is a structural diagram of another LED chip manufacturing process provided by the embodiment of the present disclosure. Figure 19As shown in (a) and (b) of FIG. 1 , a first sapphire wafer 101 has a connected flat edge 11 and a circular edge 12, and a second sapphire wafer 102 has a connected flat edge 11 and a circular edge 12. The orthographic projection of the light-emitting units 20 on the first sapphire wafer 101 and the orthographic projection of the light-emitting units 20 on the second sapphire wafer 102 are both rectangular projections. The multiple light-emitting units 20 are spaced apart, and cutting streets 22 are formed between adjacent light-emitting units 20. The second direction x2 is the length direction of the rectangular projections.

[0131] Exemplarily, the second direction x2 is perpendicular to the flat edge 11 .

[0132] In step S5002, a layer of photoresist material is coated on the first sapphire wafer, the light emitting unit on the first sapphire wafer, the second sapphire wafer, and the light emitting unit on the second sapphire wafer respectively.

[0133] In step S5003, the photoresist material on the first sapphire wafer and the light-emitting unit on the first sapphire wafer is exposed under the shielding of the third photoresist plate, and the photoresist material on the second sapphire wafer and the light-emitting unit on the second sapphire wafer is exposed under the shielding of the fourth photoresist plate.

[0134] Figure 20 Schematic diagram of the structure of a third photoresist and a fourth photoresist provided by the embodiment of the present disclosure. Figure 20 As shown in (a), the third photoresist plate 32 has a plurality of second photoresist patterns 311 arranged in an array. The second photoresist patterns 311 include a first connection electrode pattern 3011 and a second connection electrode pattern 3012. In the second photoresist patterns 311, the first connection electrode pattern 3011 points to the second connection electrode pattern 3012 along the second direction x2. Figure 20 As shown in (b) of FIG. 3 , the fourth photoresist plate 33 has a plurality of third photoresist patterns 312 arranged in an array. The third photoresist patterns 312 include a first connection electrode pattern 3011 and a second connection electrode pattern 3012. In the third photoresist patterns 312, the first connection electrode pattern 3011 points to the second connection electrode pattern 3012 along a third direction x3. The third direction x3 is opposite to the second direction x2.

[0135] In step S5004 , the photoresist material is developed to obtain a third photoresist layer and a fourth photoresist layer.

[0136] The pattern of the photoresist material removed area in the third photoresist layer is the same as the second photoresist pattern, and the pattern of the photoresist material removed area in the fourth photoresist layer is the same as the third photoresist pattern.

[0137] In step S5005 , an electrode material layer is formed on the light emitting unit, the third photoresist layer, and the fourth photoresist layer.

[0138] Illustratively, the electrode material layer may be formed by deposition under the cover of the third photoresist layer and the fourth photoresist layer.

[0139] In step S5006 , the third photoresist layer and the electrode material layer on the third photoresist layer and the fourth photoresist layer and the electrode material layer on the fourth photoresist layer are removed to obtain a connecting electrode layer.

[0140] Through the above steps S5002 to S5006 , the connection electrode layer 40 can be formed on each light emitting unit 20 .

[0141] Figure 21 This is a structural diagram of another LED chip manufacturing process provided by the embodiment of the present disclosure. Figure 21 As shown, the second direction x2 is parallel to the flat edge 11 .

[0142] In other embodiments, the angle between the second direction x2 and the flat edge 11 may be 30° to 60°.

[0143] like Figure 19 and Figure 21 As shown, the first connecting electrode 41 on each light-emitting unit 20 on the first sapphire wafer 101 points to the second connecting electrode 42 along the second direction x2, and the first connecting electrode 41 on each light-emitting unit 20 on the second sapphire wafer 102 points to the second connecting electrode 42 along the third direction x3.

[0144] In step S5007 , a passivation layer is formed on the connection electrode layer.

[0145] In step S5008 , a pad electrode layer is formed on the passivation layer.

[0146] In step S5009 , a laser is used to cleave the first sapphire wafer and the second sapphire wafer along the dicing lines from the surfaces of the first sapphire wafer and the second sapphire wafer away from the light emitting units.

[0147] It should be noted that, among the above steps S5001 to S5009, only steps S5001 to S5006 are significantly different from steps S2001 to S2006. Figure 2 Detailed description of the related embodiments is omitted here.

[0148] Through the above steps S5001 to S5009, multiple Figure 15 The LED chip shown.

[0149] The present disclosure also provides an LED chip. The LED chip adopts Figure 1 、 Figure 2 、 Figure 11 、 Figure 17 or Figure 18 Prepared by the preparation method shown in the figure. Figure 5 and Figure 6 As shown, the LED chip includes a sapphire substrate 13, a light-emitting unit 20 and a connection electrode layer stacked in sequence. The connection electrode layer includes a first connection electrode 41 and a second connection electrode 42.

[0150] Optionally, the light emitting unit 20 includes a light emitting structure 21 and a transparent conductive layer 23 stacked in sequence.

[0151] The light emitting structure 21 includes a first semiconductor layer 211 , a light emitting layer 212 , and a second semiconductor layer 213 stacked in sequence. The light emitting structure 211 has a mesa 214 extending from a surface of the second semiconductor layer 213 away from the light emitting layer 212 toward the first semiconductor layer 211 .

[0152] The transparent conductive layer 23 is located on the second semiconductor layer 213 and connected to the second semiconductor layer 213 .

[0153] The first connection electrode 41 is located on the mesa 214 and connected to the first semiconductor layer 211 .

[0154] The second connection electrode 42 is located on a side of the transparent conductive layer 23 away from the second semiconductor layer 213 and is connected to the transparent conductive layer 23 .

[0155] Optionally, the LED chip further includes a passivation layer 50 , which is located on the connection electrode layer and covers the connection electrode layer. The passivation layer 50 has a first through hole 70 exposing the first semiconductor layer 211 and a second through hole 71 exposing the transparent conductive layer 23 .

[0156] Optionally, the LED chip also includes a pad electrode layer 60, which is located on the passivation layer 50. The pad electrode layer 60 includes a first pad electrode 61 and a second pad electrode 62. The first pad electrode 61 is connected to the first connecting electrode 41 through a first through hole 70, and the second pad electrode 62 is connected to the second connecting electrode 42 through a second through hole 71.

[0157] Optionally, the structure, shape and material of the LED can be found in Figures 1 to 21 The detailed description of the preparation method is omitted here.

[0158] The embodiment of the present disclosure further provides a display device, which includes a substrate and a plurality of LED chips, wherein the plurality of LED chips are arranged in an array on the substrate, and at least one of the plurality of LED chips adopts the following method:Figure 1 、 Figure 2 、 Figure 11 、 Figure 17 or Figure 18 Prepared according to the preparation method shown.

[0159] Illustratively, the substrate may be a circuit board.

[0160] For example, when two LED chips with oppositely slanted split directions are used in the same display device, the two LED chips with oppositely slanted split directions can be arranged in an array and alternately arranged. This allows the two LED chips with oppositely slanted split directions to be evenly distributed on the light-emitting surface of the display device, improving the symmetry of the light pattern of the light-emitting surface of the display device. In other embodiments, the two LED chips with oppositely slanted split directions can be arranged in an array on either side of the centerline of the light-emitting surface of the display device, and the present disclosure is not limited thereto.

[0161] Optionally, the display device may be a backlight module or a display panel, etc. The display device may be used in products or components with display functions, such as AR / VR (augmented reality technology / virtual reality technology) devices, wearable display devices, mobile phones, and televisions.

[0162] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not intended to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments with equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure are still within the scope of the technical solution of the present disclosure.

Claims

1. A method for preparing a light-emitting diode chip, characterized in that: include: A plurality of light-emitting units (20) are formed on a sapphire wafer (10), wherein the sapphire wafer (10) has a connected flat edge (11) and an arc edge (12), and the orthographic projection of the light-emitting unit (20) on the sapphire wafer (10) is a rectangular projection. The plurality of light-emitting units (20) are distributed at intervals, and a cutting path (22) is formed between adjacent light-emitting units (20); A connecting electrode layer (40) is formed on each of the light-emitting units (20), the connecting electrode layer (40) comprising a first connecting electrode (41) and a second connecting electrode (42), the first connecting electrode (41) on each of the light-emitting units (20) pointing toward the second connecting electrode (42) along a first direction, the angle between the first direction and the flat edge (11) being 30° to 60°, the first direction being the length direction of the rectangular projection; or the first connecting electrode (41) on a portion of the light-emitting units (20) pointing toward the second connecting electrode (42) along a second direction, the second direction being the length direction of the rectangular projection, and the first connecting electrode (41) on another portion of the light-emitting units (20) pointing toward the second connecting electrode (42) along a third direction, the third direction being opposite to the second direction; The sapphire wafer (10) is split along the cutting path (22) to obtain a plurality of light-emitting diode chips.

2. The preparation method according to claim 1, characterized in that The first connecting electrode (41) on each of the light-emitting units (20) points toward the second connecting electrode (42) along the first direction; The forming of a connecting electrode layer (40) on each of the light-emitting units (20) comprises: coating a layer of photoresist material on the sapphire wafer (10) and the light-emitting unit (20); The photoresist material is exposed under the shielding of a first photoresist plate (30), wherein the first photoresist plate (30) has a plurality of first photoresist patterns (301) arranged in an array, wherein the first photoresist patterns (301) include a first connection electrode pattern (3011) and a second connection electrode pattern (3012), and wherein the first connection electrode pattern (3011) in the first photoresist pattern (301) points toward the second connection electrode pattern (3012) along the first direction; developing the photoresist material to obtain a first photoresist layer; forming an electrode material layer on the light-emitting unit (20) and the first photoresist layer; The first photoresist layer and the electrode material layer on the first photoresist layer are removed to obtain the connecting electrode layer (40).

3. The preparation method according to claim 1, characterized in that The first connecting electrode (41) on a portion of the light-emitting units (20) points toward the second connecting electrode (42) along the second direction, and the first connecting electrode (41) on another portion of the light-emitting units (20) points toward the second connecting electrode (42) along the third direction, and the two portions of the light-emitting units (20) are respectively located on both sides of the perpendicular midline of the flat edge (11).

4. The preparation method according to claim 3, characterized in that The forming of a connecting electrode layer (40) on each of the light-emitting units (20) comprises: coating a layer of photoresist material on the sapphire wafer (10) and the light-emitting unit (20); The photoresist material is exposed under the shielding of a second photoresist plate (31), wherein the second photoresist plate (31) has a plurality of second photoresist patterns (311) arranged in an array and a plurality of third photoresist patterns (312) arranged in an array, wherein the plurality of second photoresist patterns (311) and the plurality of third photoresist patterns (312) are respectively located on both sides of a center line of the second photoresist plate (31), wherein the second photoresist pattern (311) includes a first connection electrode pattern (3011) and a second connection electrode pattern (3012), wherein the first connection electrode pattern (3011) in the second photoresist pattern (311) points toward the second connection electrode pattern (3012) along the second direction, and wherein the third photoresist pattern (312) includes the first connection electrode pattern (3011) and the second connection electrode pattern (3012), wherein the first connection electrode pattern (3011) in the third photoresist pattern (312) points toward the second connection electrode pattern (3012) along the third direction; developing the photoresist material to obtain a second photoresist layer; forming an electrode material layer on the light-emitting unit (20) and the second photoresist layer; The second photoresist layer and the electrode material layer on the second photoresist layer are removed to obtain the connecting electrode layer (40).

5. A method for preparing a light-emitting diode chip, characterized in that: include: A plurality of light-emitting units (20) are formed on a first sapphire wafer (101) and a second sapphire wafer (102), respectively; the first sapphire wafer (101) has a flat edge (11) and an arc edge (12) connected to each other; the second sapphire wafer (102) has the flat edge (11) and the arc edge (12) connected to each other; the orthographic projection of the light-emitting unit (20) on the first sapphire wafer (101) on the first sapphire wafer (101) and the orthographic projection of the light-emitting unit (20) on the second sapphire wafer (102) on the second sapphire wafer (102) are both rectangular projections; the plurality of light-emitting units (20) are distributed at intervals, and a cutting path (22) is formed between adjacent light-emitting units (20); A connection electrode layer (40) is formed on each of the light-emitting units (20), the connection electrode layer (40) comprising a first connection electrode (41) and a second connection electrode (42), the first connection electrode (41) on each light-emitting unit (20) on the first sapphire wafer (101) points to the second connection electrode (42) along a second direction, the second direction being the length direction of the rectangular projection, and the first connection electrode (41) on each light-emitting unit (20) on the second sapphire wafer (102) points to the second connection electrode (42) along a third direction, the third direction being opposite to the second direction; The first sapphire wafer (101) and the second sapphire wafer (102) are split along the cutting path (22) to obtain a plurality of light-emitting diode chips.

6. The preparation method according to claim 5, characterized in that The forming of a connecting electrode layer (40) on each of the light-emitting units (20) comprises: Coating a layer of photoresist material on the first sapphire wafer (101), the light-emitting unit (20) on the first sapphire wafer (101), the second sapphire wafer (102), and the light-emitting unit (20) on the second sapphire wafer (102), respectively; The photoresist material on the first sapphire wafer (101) and the light-emitting unit (20) on the first sapphire wafer (101) is exposed under the shielding of a third photoresist plate, and the photoresist material on the second sapphire wafer (102) and the light-emitting unit (20) on the second sapphire wafer (102) is exposed under the shielding of a fourth photoresist plate (33), wherein the third photoresist plate (32) has a plurality of second photoresist patterns (311) arranged in an array, and the second photoresist patterns (311) include a first connection electrode pattern (3011) and a second connection electrode pattern (3011). shape (3012), the first connection electrode pattern (3011) in the second photolithography pattern (311) points toward the second connection electrode pattern (3012) along the second direction, the fourth photolithography plate (33) has a plurality of third photolithography patterns (312) arranged in an array, the third photolithography pattern (312) includes the first connection electrode pattern (3011) and the second connection electrode pattern (3012), and the first connection electrode pattern (3011) in the third photolithography pattern (312) points toward the second connection electrode pattern (3012) along the third direction; developing the photoresist material to obtain a third photoresist layer and a fourth photoresist layer respectively; forming an electrode material layer on the light-emitting unit (20), the third photoresist layer, and the fourth photoresist layer; The third photoresist layer and the electrode material layer on the third photoresist layer and the fourth photoresist layer and the electrode material layer on the fourth photoresist layer are removed to obtain the connecting electrode layer (40).

7. The preparation method according to any one of claims 1 to 6, characterized in that The second direction is parallel or perpendicular to the flat edge (11).

8. The preparation method according to any one of claims 1 to 6, characterized in that The light-emitting unit (20) includes a light-emitting structure (21) and a transparent conductive layer (23) stacked in sequence. The light emitting structure (21) comprises a first semiconductor layer (211), a light emitting layer (212), and a second semiconductor layer (213) stacked in sequence, and the light emitting structure (21) has a mesa (214) extending from a surface of the second semiconductor layer (213) away from the light emitting layer (212) toward the first semiconductor layer (211); The transparent conductive layer (23) is located on the second semiconductor layer (213) and is connected to the second semiconductor layer (213); The first connecting electrode (41) is located on the mesa (214) and connected to the first semiconductor layer (211); The second connecting electrode (42) is located on a side of the transparent conductive layer (23) away from the second semiconductor layer (213) and is connected to the transparent conductive layer (23); After forming the connecting electrode layer (40), the method further comprises: forming a passivation layer (50) on the connecting electrode layer (40), the passivation layer (50) covering the connecting electrode layer (40), the passivation layer (50) having a first through hole (70) exposing the first semiconductor layer (211) and a second through hole (71) exposing the transparent conductive layer (23); A pad electrode layer (60) is formed on the passivation layer (50), the pad electrode layer (60) comprising a first pad electrode (61) and a second pad electrode (62), the first pad electrode (61) being connected to the first connection electrode (41) via the first through hole (70), and the second pad electrode (62) being connected to the second connection electrode (42) via the second through hole (71).

9. A light-emitting diode chip, characterized in that: The light-emitting diode chip is prepared by the preparation method according to any one of claims 1 to 8.

10. A display device, characterized in that: The device comprises a substrate and a plurality of light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array on the substrate, and at least one light-emitting diode chip among the plurality of light-emitting diode chips is prepared by the preparation method according to any one of claims 1 to 8.

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