A high input impedance control circuit and method for analog input

Abstract

The present invention discloses a high input impedance control circuit and method for analog quantity input, wherein the circuit comprises: the input end of the first high input impedance circuit is connected to the first output end of the sampling circuit; the output end of the first high input impedance circuit is connected to the first input end of the analog-to-digital conversion circuit; the input end of the second high input impedance circuit is connected to the second output end of the sampling circuit; the output end of the second high input impedance circuit is connected to the second input end of the analog-to-digital conversion circuit; the output end of the analog-to-digital conversion circuit is connected to the input end of the control unit; the control end of the first high input impedance circuit is connected to the first control switch; the control end of the second high input impedance circuit is connected to the second control switch; the control end of the first control switch and the control end of the second control switch are respectively connected to the output end of the control unit. The technical content disclosed by the present invention provides high impedance for the analog quantity input channel during the power-on process; and the circuit device cost is low and requires a lower power supply.

Description

Technical Field

[0001] The present invention relates to the field of industrial automation technology, and more specifically, to a high input impedance control circuit and method for analog input. Background Art

[0002] In the use of industrial automation control systems, in order to improve the availability of equipment operation, it is generally necessary to make redundant configuration of modules, especially analog input modules, so that when a backup module needs to be inserted, the acquisition accuracy of the main module cannot be affected, so as to achieve true disturbance-free switching. One point is often overlooked: during the module startup and power-on process, the devices on the analog input channel will have a low input impedance path due to the uncertainty of the state during the power-on process, thereby lowering the impedance value of the input end and causing abnormal acquisition values ​​of the main module. Therefore, the analog input module needs to have a higher input impedance both during the power-on process and during normal operation.

[0003] In order to solve the problem of low impedance path during power-on when inserting a spare analog input module, it was previously necessary to add an operational amplifier or instrumentation amplifier to the input end of each channel.

[0004] In a multi-channel analog input system, it is required to add an operational amplifier or instrumentation amplifier at the input end of each channel, which is not only expensive but also occupies a large printed circuit board area and also places high demands on the power supply of the system.

[0005] Therefore, how to provide a high input impedance control circuit and method for analog input has become a technical problem that needs to be solved urgently in this field. Summary of the invention

[0006] The object of the present invention is to provide a high input impedance control circuit and method for analog input.

[0007] According to a first aspect of the present invention, there is provided a high input impedance control circuit for analog quantity input, comprising a first high input impedance circuit, a first control switch, a second high input impedance circuit and a second control switch;

[0008] The input end of the first high input impedance circuit is connected to the first output end of the sampling circuit; the output end of the first high input impedance circuit is connected to the first input end of the analog-to-digital conversion circuit; the input end of the second high input impedance circuit is connected to the second output end of the sampling circuit; the output end of the second high input impedance circuit is connected to the second input end of the analog-to-digital conversion circuit; the output end of the analog-to-digital conversion circuit is connected to the input end of the control unit; the control end of the first high input impedance circuit is connected to the first control switch; the control end of the second high input impedance circuit is connected to the second control switch; the control end of the first control switch and the control end of the second control switch are respectively connected to the output end of the control unit;

[0009] The analog-to-digital conversion circuit includes: a first multiplexer, a second multiplexer, a first operational amplifier, a second operational amplifier, a third multiplexer and an analog-to-digital converter;

[0010] The input end of the first multiplexer is the first input end of the analog-to-digital conversion circuit; the input end of the second multiplexer is the second input end of the analog-to-digital conversion circuit; the output end of the first multiplexer is connected to the input end of the first operational amplifier; the output end of the second multiplexer is connected to the input end of the second operational amplifier; the output end of the first operational amplifier and the output end of the second operational amplifier are respectively connected to the input end of the third multiplexer; the output end of the third multiplexer is connected to the input end of the analog-to-digital converter; and the output end of the analog-to-digital converter is the output end of the analog-to-digital conversion circuit.

[0011] Optionally, the first high input impedance circuit includes: a first N-channel field effect transistor, a third resistor, a fourth resistor and a fifth resistor;

[0012] The drain and input end of the first N-channel field effect transistor are connected to the first output end of the sampling circuit; the source of the first N-channel field effect transistor is connected to the first input end of the analog-to-digital conversion circuit; one end of the third resistor is connected to the gate of the first N-channel field effect transistor; the other end of the third resistor is connected to the first control switch; one end of the fifth resistor is connected to the source of the first N-channel field effect transistor; the other end of the fifth resistor is connected to the ground; one end of the fourth resistor is connected to the gate of the first N-channel field effect transistor; the other end of the fourth resistor is connected to the ground.

[0013] Optionally, the sampling circuit comprises: a first resistor and a second resistor;

[0014] One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground;

[0015] In order to enable the first output terminal signal of the sampling circuit to pass through the first N-channel field effect transistor, the gate voltage of the first N-channel field effect transistor needs to satisfy the following formula:

[0016]

[0017] Wherein, Vg1 is the driving gate voltage of the first N-channel field effect transistor; R3 is the third resistor; R4 is the fourth resistor; V 1GS(th) is the threshold turn-on voltage of the first N-channel field effect transistor; I input It is the analog input current.

[0018] Optionally, the second high input impedance circuit includes: a second N-channel field effect transistor, a sixth resistor, a seventh resistor and an eighth resistor;

[0019] The drain and input end of the second N-channel field effect transistor are connected to the second output end of the sampling circuit; the source of the second N-channel field effect transistor is connected to the second input end of the analog-to-digital conversion circuit; one end of the sixth resistor is connected to the gate of the second N-channel field effect transistor; the other end of the sixth resistor is connected to the second control switch; one end of the eighth resistor is connected to the source of the second N-channel field effect transistor; the other end of the eighth resistor is connected to ground; one end of the seventh resistor is connected to the gate of the second N-channel field effect transistor; and the other end of the seventh resistor is connected to ground.

[0020] Optionally, the sampling circuit comprises: a first resistor and a second resistor;

[0021] One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground;

[0022] In order to enable the second output terminal signal of the sampling circuit to pass through the second N-channel field effect transistor, the gate voltage of the second N-channel field effect transistor needs to satisfy the following formula:

[0023]

[0024] Wherein, R6 is the sixth resistor; R7 is the seventh resistor; V 2GS(th) is the threshold turn-on voltage of the second N-channel field effect transistor; Iinput It is the analog input current.

[0025] According to a second aspect of the present invention, a high input impedance control method for analog input is provided, comprising the high input impedance control circuit for analog input according to the first aspect of the present invention, the method comprising:

[0026] During the power-on process, the first control switch is disconnected, and the first high input impedance circuit is in a high impedance state;

[0027] When power-on is completed, the control unit controls the first control switch to close, and the first high input impedance circuit is turned on;

[0028] During the power-on process, the second control switch is disconnected, and the second high input impedance circuit is in a high impedance state;

[0029] When power-on is completed, the control unit controls the second control switch to close, and the second high input impedance circuit is turned on.

[0030] Optionally, the first high input impedance circuit includes: a first N-channel field effect transistor, a third resistor R3, a fourth resistor and a fifth resistor;

[0031] The drain and input end of the first N-channel field effect transistor are connected to the first output end of the sampling circuit; the source of the first N-channel field effect transistor is connected to the first input end of the analog-to-digital conversion circuit; one end of the third resistor is connected to the gate of the first N-channel field effect transistor; the other end of the third resistor is connected to the first control switch; one end of the fifth resistor is connected to the source of the first N-channel field effect transistor; the other end of the fifth resistor is connected to the ground; one end of the fourth resistor is connected to the gate of the first N-channel field effect transistor; the other end of the fourth resistor is connected to the ground;

[0032] During the power-on process, the first control switch is disconnected and pulled down by the fourth resistor, so that the gate voltage of the first N-channel field effect transistor is zero, the first N-channel field effect transistor is turned off, and the first high input impedance circuit is in a high impedance state;

[0033] When power-on is completed, the control unit controls the first control switch to close, and the gate drive voltage Vg1 of the first N-channel field effect transistor passes through the voltage divider circuit of the third resistor and the fourth resistor, so that the gate voltage of the first N-channel field effect transistor is: The fifth resistor is pulled down by default, that is, the source of the first N-channel field effect transistor is 0V, and the first high input impedance circuit is turned on.

[0034] Optionally, the sampling circuit comprises: a first resistor and a second resistor;

[0035] One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground;

[0036] In order to enable the first output terminal signal of the sampling circuit to pass through the first N-channel field effect transistor, the gate voltage of the first N-channel field effect transistor needs to satisfy the following formula:

[0037]

[0038] Wherein, Vg1 is the gate drive voltage of the first N-channel field effect transistor Q1; R3 is the third resistor; R4 is the fourth resistor; V 1GS(th) is the threshold turn-on voltage of the first N-channel field effect transistor Q1; I input It is the analog input current.

[0039] Optionally, the second high input impedance circuit includes: a second N-channel field effect transistor, a sixth resistor, a seventh resistor and an eighth resistor;

[0040] The drain and input end of the second N-channel field effect transistor are connected to the second output end of the sampling circuit; the source of the second N-channel field effect transistor is connected to the second input end of the analog-to-digital conversion circuit; one end of the sixth resistor is connected to the gate of the second N-channel field effect transistor; the other end of the sixth resistor is connected to the second control switch; one end of the eighth resistor is connected to the source of the second N-channel field effect transistor; the other end of the eighth resistor is connected to the ground; one end of the seventh resistor is connected to the gate of the second N-channel field effect transistor; the other end of the seventh resistor is connected to the ground;

[0041] During the power-on process, the second control switch is disconnected and pulled down by the fourth resistor, so that the gate voltage of the second N-channel field effect transistor is zero, the second N-channel field effect transistor is turned off, and the second high input impedance circuit is in a high impedance state;

[0042] When the power-on is completed, the control unit controls the second control switch to close, and the gate drive voltage Vg2 of the second N-channel field effect transistor passes through the voltage divider circuit of the sixth resistor and the seventh resistor, so that the gate voltage of the second N-channel field effect transistor is: The eighth resistor is pulled down by default, that is, the source of the second N-channel field effect transistor is 0V, and the second high input impedance circuit is turned on.

[0043] Optionally, the sampling circuit includes: a first resistor R1 and a second resistor R2;

[0044] One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground;

[0045] In order to enable the second output terminal signal of the sampling circuit to pass through the second N-channel field effect transistor, the gate voltage of the second N-channel field effect transistor needs to satisfy the following formula:

[0046]

[0047] Wherein, R6 is the sixth resistor; R7 is the seventh resistor; V 2GS(th) is the threshold turn-on voltage of the second N-channel field effect transistor; I input It is the analog input current.

[0048] According to the technical content disclosed in the present invention, the following beneficial effects are achieved: high impedance is provided for the analog input channel during the power-on process; and the circuit device cost is low, the layout area is small, and a lower power supply is required.

[0049] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0051] Figure 1 The present invention is a schematic diagram of a high input impedance control circuit for analog input provided according to an embodiment.

[0052] Explanation of the accompanying drawings: R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; Q1, first N-channel field effect transistor; Q2, second N-channel field effect transistor; SW1, first control switch; SW2, second control switch; MUX1, first multiplexer; MUX2, second multiplexer; OPA1, first operational amplifier; OPA2, second operational amplifier; MUX1, third multiplexer; ADC, analog-to-digital converter; T, external AI instrument. DETAILED DESCRIPTION

[0053] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0054] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0055] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0056] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0057] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0058] According to a first aspect of the present invention, Figure 1 As shown, a high input impedance control circuit for analog input is provided, comprising a first high input impedance circuit, a first control switch SW1, a second high input impedance circuit and a second control switch SW2;

[0059] The input end of the first high input impedance circuit is connected to the first output end of the sampling circuit; the output end of the first high input impedance circuit is connected to the first input end of the analog-to-digital conversion circuit; the input end of the second high input impedance circuit is connected to the second output end of the sampling circuit; the output end of the second high input impedance circuit is connected to the second input end of the analog-to-digital conversion circuit; the output end of the analog-to-digital conversion circuit is connected to the input end of the control unit; the control end of the first high input impedance circuit is connected to the first control switch SW1; the control end of the second high input impedance circuit is connected to the second control switch SW2; the control end of the first control switch SW1 and the control end of the second control switch SW2 are respectively connected to the output end of the control unit;

[0060] The analog-to-digital conversion circuit includes: a first multiplexer MUX1, a second multiplexer MUX2, a first operational amplifier OPA1, a second operational amplifier OPA2, a third multiplexer MUX3 and an analog-to-digital converter ADC;

[0061] The input end of the first multiplexer MUX1 is the first input end of the analog-to-digital conversion circuit; the input end of the second multiplexer MUX2 is the second input end of the analog-to-digital conversion circuit; the output end of the first multiplexer MUX1 is connected to the input end of the first operational amplifier OPA1; the output end of the second multiplexer MUX2 is connected to the input end of the second operational amplifier OPA2; the output end of the first operational amplifier OPA1 and the output end of the second operational amplifier OPA2 are respectively connected to the input end of the third multiplexer MUX3; the output end of the third multiplexer MUX3 is connected to the input end of the analog-to-digital converter ADC; the output end of the analog-to-digital converter ADC is the output end of the analog-to-digital conversion circuit.

[0062] The first operational amplifier OPA1 and the second operational amplifier OPA2 have the characteristics of high input impedance, and therefore also have high input impedance during normal operation.

[0063] In some embodiments, the first high input impedance circuit includes: a first N-channel field effect transistor Q1, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

[0064] The drain and input end of the first N-channel field effect transistor Q1 are connected to the first output end of the sampling circuit; the source of the first N-channel field effect transistor Q1 is connected to the first input end of the analog-to-digital conversion circuit; one end of the third resistor R3 is connected to the gate of the first N-channel field effect transistor Q1; the other end of the third resistor R3 is connected to the first control switch SW1; one end of the fifth resistor R5 is connected to the source of the first N-channel field effect transistor Q1; the other end of the fifth resistor R5 is connected to the ground; one end of the fourth resistor R4 is connected to the gate of the first N-channel field effect transistor Q1; the other end of the fourth resistor R4 is connected to the ground.

[0065] The third resistor R3 and the fourth resistor R4 are used to provide a certain level to the gate of the first N-channel field effect transistor Q1 when powered on, so that the first N-channel field effect transistor Q1 is in a turned-off state.

[0066] The fifth resistor R5 provides a certain level to the source of the first N-channel field effect transistor Q1 when powered on, so as to ensure that the first N-channel field effect transistor Q1 is reliably turned on.

[0067] Convert the input current signal into a voltage signal; in the safety instrument system, two sampling resistors are generally used in series, mainly to be able to diagnose random faults of the sampling resistors, so the voltage across the first resistor R1 and the voltage across the first resistor R1 and the second resistor R2 need to be collected.

[0068] The sampling circuit comprises: a first resistor R1 and a second resistor R2;

[0069] One end of the first resistor R1 is connected to one end of the external AI meter T, and one end of the first resistor R1 is the first output end of the sampling circuit; the other end of the first resistor R1 is connected to one end of the second resistor R2; one end of the second resistor R2 is the second output end of the sampling circuit; the other end of the second resistor R2 is connected to the ground;

[0070] The external AI instrument T provides analog output current (such as 4mA ~ 20mA);

[0071] In order to enable the first output terminal signal of the sampling circuit to pass through the first N-channel field effect transistor Q1, the gate voltage of the first N-channel field effect transistor Q1 needs to satisfy the following formula:

[0072]

[0073] Wherein, Vg1 is the driving gate voltage of the first N-channel field effect transistor Q1; R3 is the third resistor; R4 is the fourth resistor; V 1GS(th) is the threshold turn-on voltage of the first N-channel field effect transistor Q1; I input It is the analog input current.

[0074] In some embodiments, the second high input impedance circuit includes: a second N-channel field effect transistor Q2, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8;

[0075] The drain and input end of the second N-channel field effect transistor Q2 are connected to the second output end of the sampling circuit; the source of the second N-channel field effect transistor Q2 is connected to the second input end of the analog-to-digital conversion circuit; one end of the sixth resistor R6 is connected to the gate of the second N-channel field effect transistor Q2; the other end of the sixth resistor R6 is connected to the second control switch SW2; one end of the eighth resistor R8 is connected to the source of the second N-channel field effect transistor Q2; the other end of the eighth resistor R8 is connected to the ground; one end of the seventh resistor R7 is connected to the gate of the second N-channel field effect transistor Q2; the other end of the seventh resistor R7 is connected to the ground.

[0076] The functions of the sixth resistor R6 and the seventh resistor R7 are consistent with those of the third resistor R3 and the fourth resistor R4.

[0077] The sampling circuit comprises: a first resistor R1 and a second resistor R2;

[0078] One end of the first resistor R1 is connected to one end of the external AI meter T, and one end of the first resistor R1 is the first output end of the sampling circuit; the other end of the first resistor R1 is connected to one end of the second resistor R2; one end of the second resistor R2 is the second output end of the sampling circuit; the other end of the second resistor R2 is connected to the ground

[0079] In order to enable the second output terminal signal of the sampling circuit to pass through the second N-channel field effect transistor Q2, the gate voltage of the second N-channel field effect transistor Q2 needs to satisfy the following formula:

[0080]

[0081] Wherein, R6 is the sixth resistor; R7 is the seventh resistor; V 2GS(th) is the threshold turn-on voltage of the second N-channel field effect transistor; I input It is the analog input current.

[0082] According to a second aspect of the present invention, a high input impedance control method for analog input is provided, comprising the high input impedance control circuit for analog input described in the first item of Embodiment 1, the method comprising:

[0083] During the power-on process, the first control switch SW1 is disconnected, and the first high input impedance circuit is in a high impedance state;

[0084] When power-on is completed, the control unit controls the first control switch SW1 to close, and the first high input impedance circuit is turned on;

[0085] During the power-on process, the second control switch SW2 is disconnected, and the second high input impedance circuit is in a high impedance state;

[0086] After power-on is completed, the control unit controls the second control switch SW2 to close, and the second high input impedance circuit is turned on.

[0087] The first high input impedance circuit includes: a first N-channel field effect transistor Q1, a third resistor R3, a fourth resistor R4 and a fifth resistor R5;

[0088] The drain and input end of the first N-channel field effect transistor Q1 are connected to the first output end of the sampling circuit; the source of the first N-channel field effect transistor Q1 is connected to the first input end of the analog-to-digital conversion circuit; one end of the third resistor R3 is connected to the gate of the first N-channel field effect transistor Q1; the other end of the third resistor R3 is connected to the first control switch SW1; one end of the fifth resistor R5 is connected to the source of the first N-channel field effect transistor Q1; the other end of the fifth resistor R5 is connected to the ground; one end of the fourth resistor R4 is connected to the gate of the first N-channel field effect transistor Q1; the other end of the fourth resistor R4 is connected to the ground;

[0089] During the power-on process, the first control switch SW1 is disconnected and pulled down by the fourth resistor R4, so that the gate voltage of the first N-channel field effect transistor Q1 is zero, the first N-channel field effect transistor Q1 is turned off, and the first high input impedance circuit is in a high impedance state;

[0090] When power-on is completed, the control unit controls the first control switch SW1 to close, and the gate drive voltage Vg1 of the first N-channel field effect transistor Q1 passes through the voltage divider circuit of the third resistor R3 and the fourth resistor R4, so that the gate voltage of the first N-channel field effect transistor Q1 is: The fifth resistor R5 is pulled down by default, that is, the source of the first N-channel field effect transistor Q1 is 0V, and the first high input impedance circuit is turned on.

[0091] The sampling circuit comprises: a first resistor R1 and a second resistor R2;

[0092] One end of the first resistor R1 is connected to one end of the external AI meter T, and one end of the first resistor R1 is the first output end of the sampling circuit; the other end of the first resistor R1 is connected to one end of the second resistor R2; one end of the second resistor R2 is the second output end of the sampling circuit; the other end of the second resistor R2 is connected to the ground;

[0093] In order to enable the first output terminal signal of the sampling circuit to pass through the first N-channel field effect transistor Q1, the gate voltage of the first N-channel field effect transistor Q1 needs to satisfy the following formula:

[0094]

[0095] Wherein, Vg1 is the gate drive voltage of the first N-channel field effect transistor Q1; R3 is the third resistor; R4 is the fourth resistor; V 1GS(th) is the threshold turn-on voltage of the first N-channel field effect transistor Q1; I input It is the analog input current.

[0096] The second high input impedance circuit includes: a second N-channel field effect transistor Q2, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8;

[0097] The drain and input end of the second N-channel field effect transistor Q2 are connected to the second output end of the sampling circuit; the source of the second N-channel field effect transistor Q2 is connected to the second input end of the analog-to-digital conversion circuit; one end of the sixth resistor R6 is connected to the gate of the second N-channel field effect transistor Q2; the other end of the sixth resistor R6 is connected to the second control switch SW2; one end of the eighth resistor R8 is connected to the source of the second N-channel field effect transistor Q2; the other end of the eighth resistor R8 is connected to the ground; one end of the seventh resistor R7 is connected to the gate of the second N-channel field effect transistor Q2; the other end of the seventh resistor R7 is connected to the ground;

[0098] During the power-on process, the second control switch SW2 is disconnected and pulled down by the fourth resistor R7, so that the gate voltage of the second N-channel field effect transistor Q2 is zero, the second N-channel field effect transistor Q2 is turned off, and the second high input impedance circuit is in a high impedance state;

[0099] When the power-on is completed, the control unit controls the second control switch SW2 to close, and the gate drive voltage Vg2 of the second N-channel field effect transistor Q2 passes through the voltage divider circuit of the sixth resistor R6 and the seventh resistor R7, so that the gate voltage of the second N-channel field effect transistor Q2 is: The eighth resistor R8 is pulled down by default, that is, the source of the second N-channel field effect transistor Q2 is 0V, and the second high input impedance circuit is turned on.

[0100] The sampling circuit comprises: a first resistor R1 and a second resistor R2;

[0101] One end of the first resistor R1 is connected to one end of the external AI meter T, and one end of the first resistor R1 is the first output end of the sampling circuit; the other end of the first resistor R1 is connected to one end of the second resistor R2; one end of the second resistor R2 is the second output end of the sampling circuit; the other end of the second resistor R2 is connected to the ground;

[0102] In order to enable the second output terminal signal of the sampling circuit to pass through the second N-channel field effect transistor Q2, the gate voltage of the second N-channel field effect transistor Q2 needs to satisfy the following formula:

[0103]

[0104] In summary, if an operational amplifier is used as a high impedance at power-on on the analog input module channel, the input end of the channel requires at least one high-voltage operational amplifier, and the general withstand voltage value needs to be 36V, mainly due to the 24V power supply used in industrial sites. The solution of using NMOS tube as the high impedance of the input end has a very large cost advantage.

[0105] The cost of a single high-voltage operational amplifier is about 5 RMB, while the cost of a small SOT23 packaged NMOS tube is about 0.5 RMB. The cost difference between the two is about 10 times. Taking the analog acquisition module with 32 channels as an example, if a high-voltage operational amplifier is used as a high-impedance solution at the input end, the calculated cost is 320 RMB; while the solution using NMOS tube as a high-impedance solution at the input end is 32 RMB. If an NMOS tube is used as a high-impedance solution at the input end on a single analog input module, at least 288 RMB can be saved. In actual industrial sites, a large number of analog input modules will be used, and the cost savings can at least reach a certain objective figure.

[0106] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A high input impedance control circuit for analog input, characterized in that: include: a first high input impedance circuit, a first control switch, a second high input impedance circuit, and a second control switch; The input end of the first high input impedance circuit is connected to the first output end of the sampling circuit; the output end of the first high input impedance circuit is connected to the first input end of the analog-to-digital conversion circuit; the input end of the second high input impedance circuit is connected to the second output end of the sampling circuit; the output end of the second high input impedance circuit is connected to the second input end of the analog-to-digital conversion circuit; the output end of the analog-to-digital conversion circuit is connected to the input end of the control unit; the control end of the first high input impedance circuit is connected to the first control switch; the control end of the second high input impedance circuit is connected to the second control switch; The control end of the first control switch and the control end of the second control switch are respectively connected to the output end of the control unit; The analog-to-digital conversion circuit includes: a first multiplexer, a second multiplexer, a first operational amplifier, a second operational amplifier, a third multiplexer and an analog-to-digital converter; The input end of the first multiplexer is the first input end of the analog-to-digital conversion circuit; the input end of the second multiplexer is the second input end of the analog-to-digital conversion circuit; the output end of the first multiplexer is connected to the input end of the first operational amplifier; the output end of the second multiplexer is connected to the input end of the second operational amplifier; the output end of the first operational amplifier and the output end of the second operational amplifier are respectively connected to the input end of the third multiplexer; the output end of the third multiplexer is connected to the input end of the analog-to-digital converter; the output end of the analog-to-digital converter is the output end of the analog-to-digital conversion circuit; The first high input impedance circuit comprises: a first N-channel field effect transistor, a third resistor, a fourth resistor and a fifth resistor; The drain and input end of the first N-channel field effect transistor are connected to the first output end of the sampling circuit; the source of the first N-channel field effect transistor is connected to the first input end of the analog-to-digital conversion circuit; one end of the third resistor is connected to the gate of the first N-channel field effect transistor; the other end of the third resistor is connected to the first control switch; one end of the fifth resistor is connected to the source of the first N-channel field effect transistor; the other end of the fifth resistor is connected to the ground; one end of the fourth resistor is connected to the gate of the first N-channel field effect transistor; the other end of the fourth resistor is connected to the ground.

2. The high input impedance control circuit for analog input according to claim 1, characterized in that: The sampling circuit comprises: a first resistor and a second resistor; One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground; In order to enable the first output terminal signal of the sampling circuit to pass through the first N-channel field effect transistor, the gate voltage of the first N-channel field effect transistor needs to satisfy the following formula: Wherein, Vg1 is the driving gate voltage of the first N-channel field effect transistor; R3 is the third resistor; R4 is the fourth resistor; V 1GS(th) is the threshold turn-on voltage of the first N-channel field effect transistor; I input It is the analog input current.

3. The high input impedance control circuit for analog input according to claim 1, characterized in that: The second high input impedance circuit includes: a second N-channel field effect transistor, a sixth resistor, a seventh resistor and an eighth resistor; The drain and input end of the second N-channel field effect transistor are connected to the second output end of the sampling circuit; the source of the second N-channel field effect transistor is connected to the second input end of the analog-to-digital conversion circuit; one end of the sixth resistor is connected to the gate of the second N-channel field effect transistor; the other end of the sixth resistor is connected to the second control switch; one end of the eighth resistor is connected to the source of the second N-channel field effect transistor; the other end of the eighth resistor is connected to ground; one end of the seventh resistor is connected to the gate of the second N-channel field effect transistor; and the other end of the seventh resistor is connected to ground.

4. The high input impedance control circuit for analog input according to claim 3, characterized in that: The sampling circuit comprises: a first resistor and a second resistor; One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground; In order to enable the second output terminal signal of the sampling circuit to pass through the second N-channel field effect transistor, the gate voltage of the second N-channel field effect transistor needs to satisfy the following formula: Wherein, R6 is the sixth resistor; R7 is the seventh resistor; V 2GS(th) is the threshold turn-on voltage of the second N-channel field effect transistor; I input It is the analog input current.

5. A high input impedance control method for analog input, characterized in that: The high input impedance control circuit for analog input according to claim 1, the method comprising: During the power-on process, the first control switch is disconnected, and the first high input impedance circuit is in a high impedance state; When power-on is completed, the control unit controls the first control switch to close, and the first high input impedance circuit is turned on; During the power-on process, the second control switch is disconnected, and the second high input impedance circuit is in a high impedance state; When power-on is completed, the control unit controls the second control switch to close, and the second high input impedance circuit is turned on; The first high input impedance circuit includes: a first N-channel field effect transistor, a third resistor R3, a fourth resistor and a fifth resistor; The drain and input end of the first N-channel field effect transistor are connected to the first output end of the sampling circuit; the source of the first N-channel field effect transistor is connected to the first input end of the analog-to-digital conversion circuit; one end of the third resistor is connected to the gate of the first N-channel field effect transistor; the other end of the third resistor is connected to the first control switch; one end of the fifth resistor is connected to the source of the first N-channel field effect transistor; the other end of the fifth resistor is connected to the ground; one end of the fourth resistor is connected to the gate of the first N-channel field effect transistor; the other end of the fourth resistor is connected to the ground; During the power-on process, the first control switch is disconnected and pulled down by the fourth resistor, so that the gate voltage of the first N-channel field effect transistor is zero, the first N-channel field effect transistor is turned off, and the first high input impedance circuit is in a high impedance state; When power-on is completed, the control unit controls the first control switch to close, and the gate drive voltage Vg1 of the first N-channel field effect transistor passes through the voltage divider circuit of the third resistor and the fourth resistor, so that the gate voltage of the first N-channel field effect transistor is: The fifth resistor is pulled down by default, that is, the source of the first N-channel field effect transistor is 0V, the first high input impedance circuit is turned on, Vg1 is the gate drive voltage of the first N-channel field effect transistor Q1; R3 is the third resistor; R4 is the fourth resistor.

6. The high input impedance control method of analog input according to claim 5, characterized in that: The sampling circuit comprises: a first resistor and a second resistor; One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground; In order to enable the first output terminal signal of the sampling circuit to pass through the first N-channel field effect transistor, the gate voltage of the first N-channel field effect transistor needs to satisfy the following formula: Wherein, R1 is the first resistor; R2 is the second resistor; V 1GS(th) is the threshold turn-on voltage of the first N-channel field effect transistor Q1; I input It is the analog input current.

7. The high input impedance control method of analog input according to claim 5, characterized in that: The second high input impedance circuit includes: a second N-channel field effect transistor, a sixth resistor, a seventh resistor and an eighth resistor; The drain and input end of the second N-channel field effect transistor are connected to the second output end of the sampling circuit; the source of the second N-channel field effect transistor is connected to the second input end of the analog-to-digital conversion circuit; one end of the sixth resistor is connected to the gate of the second N-channel field effect transistor; the other end of the sixth resistor is connected to the second control switch; one end of the eighth resistor is connected to the source of the second N-channel field effect transistor; the other end of the eighth resistor is connected to the ground; one end of the seventh resistor is connected to the gate of the second N-channel field effect transistor; the other end of the seventh resistor is connected to the ground; During the power-on process, the second control switch is disconnected and pulled down by the fourth resistor, so that the gate voltage of the second N-channel field effect transistor is zero, the second N-channel field effect transistor is turned off, and the second high input impedance circuit is in a high impedance state; When the power-on is completed, the control unit controls the second control switch to close, and the gate drive voltage Vg2 of the second N-channel field effect transistor passes through the voltage divider circuit of the sixth resistor and the seventh resistor, so that the gate voltage of the second N-channel field effect transistor is: The eighth resistor is pulled down by default, that is, the source of the second N-channel field effect transistor is 0V, and the second high input impedance circuit is turned on, wherein R6 is the sixth resistor and R7 is the seventh resistor.

8. The high input impedance control method of analog input according to claim 7, characterized in that: The sampling circuit comprises: a first resistor R1 and a second resistor R2; One end of the first resistor is connected to one end of the external AI meter, one end of the first resistor is the first output end of the sampling circuit; the other end of the first resistor is connected to one end of the second resistor; one end of the second resistor is the second output end of the sampling circuit; the other end of the second resistor is connected to the ground; In order to enable the second output terminal signal of the sampling circuit to pass through the second N-channel field effect transistor, the gate voltage of the second N-channel field effect transistor needs to satisfy the following formula: Wherein, R6 is the sixth resistor; R7 is the seventh resistor; V 2GS(th) is the threshold turn-on voltage of the second N-channel field effect transistor; I input It is the analog input current.

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