Common electrode compensation circuit and display device

Abstract

Embodiments of the present application relate to a common electrode compensation circuit and display device. The circuit includes: a pixel unit array, a data driver module, a timing control module, a digital-to-analog conversion module, a common voltage compensation module, and a common electrode. The timing control module determines a first grayscale voltage measurement value corresponding to each data line in a data line group at a moment before the current moment, and a second grayscale voltage measurement value corresponding to each data line at the current moment; determines the difference between the first grayscale voltage measurement value and the second grayscale voltage measurement value corresponding to each data line; sums the obtained differences to obtain a total difference; the digital-to-analog conversion module converts the total difference into an analog voltage; and the common voltage compensation module outputs an inverted compensation voltage to the common electrode based on the change in the analog voltage output by the digital-to-analog conversion module. Embodiments of the present application further stabilize the voltage on the common electrode, avoiding abnormal phenomena such as image sticking when displaying images.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a common electrode compensation circuit and a display device. Background Art

[0002] The current method of driving TFT-LCD (Thin Film Transistor Liquid Crystal Display) panels is usually a row-by-row scanning method, that is, when the scanning signal is high, the TFT corresponding to the row in the pixel array is turned on, and data in the column direction can be written into the pixel. Figure 1 As shown, it shows a schematic diagram of the driving method of each pixel unit. It includes a control switch T, a liquid crystal capacitor Clc, a storage capacitor Cst, a G line responsible for transmitting the switching signal, and an S line responsible for transmitting data. One end of Cst and Clc is a pixel electrode, and the other end is a common electrode (VCOM). Since the charging and discharging of liquid crystal is a capacitor structure, if a DC (direct current) circuit is used to drive it, then residual charge will inevitably be generated at both ends of the capacitor, which will be reflected in the display as afterimages. In order to avoid this phenomenon, DC is changed to AC (alternating current). As shown Figure 2 Figure 1 shows the waveform of the signal S-out on the data line. This figure shows that the voltage level on a data line constantly flips polarity relative to VCOM. This polarity flip creates parasitic capacitance between the data line and VCOM, causing VCOM to experience a short-term sudden change. The voltage difference across the LCD is not the theoretical value of DATA - VCOM, but rather DATA - (VCOM + ΔV). This voltage difference changes the brightness, resulting in abnormalities such as image sticking on the display.

[0003] To reduce the impact of parasitic capacitance, the current method performs a logical calculation on the brightness data of the previous row and the brightness data of the current row to calculate the brightness difference. This brightness difference is then used to compensate the data lines of the current row. However, this compensation method is not suitable for situations where the brightness of pixels within a row is inconsistent. In other words, if some pixels in a row are darker and some are brighter, the compensation effect is poor. Summary of the Invention

[0004] In view of this, in order to solve some or all of the above technical problems, the embodiments of the present application provide a common electrode compensation circuit and a display device.

[0005] In a first aspect, an embodiment of the present application provides a common electrode compensation circuit, which includes: a pixel unit array, a data driving module, a timing control module, a digital-to-analog conversion module, a common voltage compensation module and a common electrode, the data driving module includes a data line group; the data driving module is used to output a grayscale voltage to the pixel unit array through the data line group; the timing control module is used to: determine the first grayscale voltage measurement value corresponding to each data line in the data line group at the moment before the current moment, and the second grayscale voltage measurement value corresponding to each data line at the current moment; determine the difference between the first grayscale voltage measurement value and the second grayscale voltage measurement value corresponding to each data line; sum the obtained differences to obtain a total difference; output the total difference to the digital-to-analog conversion module; the digital-to-analog conversion module is used to: convert the total difference into an analog voltage, and output the analog voltage to the common voltage compensation module; the common voltage compensation module is used to: output an inverted compensation voltage to the common electrode according to the change in the analog voltage output by the digital-to-analog conversion module.

[0006] In one possible embodiment, the timing control module is further used to: determine the first grayscale value and the first voltage polarity corresponding to each data line in the data line group at a moment before the current moment, and the second grayscale value and the second voltage polarity corresponding to each data line at the current moment; and search for the first grayscale voltage measurement value corresponding to the first grayscale value and the first voltage polarity, and the second grayscale voltage measurement value corresponding to the second grayscale value and the second voltage polarity from a pre-set grayscale conversion table.

[0007] In one possible embodiment, the grayscale conversion table is pre-set as follows: the positive polarity grayscale voltage corresponding to each grayscale value under the positive voltage polarity is determined, and the positive grayscale voltage measurement value corresponding to each positive polarity grayscale value under the positive voltage polarity is calculated based on the positive polarity grayscale voltage, a preset maximum grayscale voltage and a preset coefficient; the negative polarity grayscale voltage corresponding to each grayscale value under the negative voltage polarity is determined, and the negative grayscale voltage measurement value corresponding to each negative polarity grayscale value under the negative voltage polarity is calculated based on the negative polarity grayscale voltage, the maximum grayscale voltage and the coefficient.

[0008] In one possible embodiment, the digital-to-analog conversion module includes a voltage conversion unit and a digital-to-analog converter; the voltage conversion unit is used to: convert the high-level voltage of the digital signal representing the total difference into a preset voltage to obtain a converted digital signal, wherein the preset voltage matches the switch start voltage inside the digital-to-analog converter; output the converted digital signal to the digital-to-analog converter; the digital-to-analog converter is used to: convert the converted digital signal into an analog voltage, and output the analog voltage to the common voltage compensation module.

[0009] In one possible embodiment, the digital-to-analog conversion module further includes a bit conversion unit; the bit conversion unit is used to: convert the number of bits of the digital signal representing the total difference into a preset number of bits; and output the obtained digital signal with the preset number of bits to the voltage conversion unit.

[0010] In one possible embodiment, the voltage conversion unit includes an inverter, a positive-phase voltage conversion subunit, and a negative-phase voltage conversion subunit; the inverter is used to: perform an inversion operation on the digital signal representing the total difference to obtain an negative-phase digital signal; the positive-phase voltage conversion subunit is used to: convert the high-level voltage of the digital signal representing the total difference into a preset voltage to obtain a positive-phase converted digital signal; the negative-phase voltage conversion subunit is used to: convert the high-level voltage of the negative-phase digital signal into a preset voltage to obtain an negative-phase converted digital signal.

[0011] In one possible embodiment, the digital-to-analog converter includes a reference voltage input terminal, a positive-phase digital signal input terminal, and a negative-phase digital signal input terminal; the reference voltage input terminal is used to receive an input maximum grayscale voltage; the positive-phase digital signal input terminal is used to receive an input positive-phase converted digital signal, and the negative-phase digital signal input terminal is used to receive an input negative-phase converted digital signal; the positive-phase digital signal input terminal and the negative-phase digital signal input terminal are respectively connected to the control terminals of multiple switches, and through a combination of multiple switches, an analog voltage corresponding to the positive-phase converted digital signal is output.

[0012] In one possible embodiment, the common voltage compensation module includes an operational amplifier, a feedback resistor, a compensation resistor, a current limiting resistor and a differential capacitor; one end of the current limiting resistor is connected to the output end of the digital-to-analog conversion module, and the other end is connected to the differential capacitor; one end of the differential capacitor is connected to the current limiting resistor, and the other end is connected to the inverting input end of the operational amplifier; one end of the feedback resistor is connected to the inverting input end, and the other end is connected to the output end of the operational amplifier; one end of the compensation resistor is connected to the non-inverting input end of the operational amplifier, and the other end is connected to the common electrode.

[0013] In a possible implementation, the common voltage compensation module further includes a phase compensation capacitor, one end of the phase compensation capacitor is connected to the inverting input terminal, and the other end is connected to the output terminal of the operational amplifier.

[0014] In a second aspect, an embodiment of the present application provides a display device comprising: a display panel, a panel frame, a power supply module and a data receiving module, wherein the display panel comprises the common electrode compensation circuit described in the first aspect above; the display panel is mounted on the panel frame, the power supply end of the display panel is connected to the power supply module, and the signal receiving end of the display panel is connected to the data receiving module.

[0015] The common electrode compensation circuit and display device provided in the embodiments of the present application pre-record the first grayscale voltage measurement value when the pixel unit is driven at the previous moment, and the second grayscale voltage measurement value when the pixel unit is driven at the current moment. The timing control module calculates the difference between the first grayscale voltage measurement value and the second grayscale voltage measurement value, and sums the differences corresponding to each data line to obtain a total difference. The digital-to-analog conversion module converts the total difference into an analog voltage. The common voltage compensation module responds to the change in the analog voltage and outputs an inverted compensation voltage, thereby achieving the inverted compensation voltage to offset the voltage mutation caused by parasitic capacitance on the common electrode, making the voltage on the common electrode more stable. Since the magnitude of the output inverted compensation voltage is obtained by comprehensively calculating the change in the actual output voltage on the data line, when the display brightness of a row of pixels is inconsistent, the brightness mutation can still be well compensated to avoid abnormal phenomena such as afterimages when displaying the picture. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0019] Figure 1 A schematic diagram of a pixel unit driving method in the prior art;

[0020] Figure 2 A schematic diagram of a waveform of voltage changes on a common electrode due to parasitic capacitance in the prior art;

[0021] Figure 3 A schematic structural diagram of a common electrode compensation circuit provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of a waveform of the reverse compensation voltage provided in an embodiment of the present application compensating the coupling voltage on the common electrode;

[0023] Figure 5 A schematic diagram of the structure of the digital-to-analog conversion module provided in an embodiment of the present application;

[0024] Figure 6 A schematic structural diagram of another digital-to-analog conversion module provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the structure of a voltage conversion unit provided in an embodiment of the present application;

[0026] Figure 8 A waveform diagram of high-level amplification of a digital signal provided in an embodiment of the present application;

[0027] Figure 9 A circuit structure diagram of the positive phase voltage conversion subunit and the negative phase voltage conversion subunit provided in an embodiment of the present application;

[0028] Figure 10 A circuit diagram of a digital-to-analog converter provided in an embodiment of the present application;

[0029] Figure 11 A circuit diagram of a common voltage compensation module provided in an embodiment of the present application;

[0030] Figure 12 A circuit structure diagram of another common voltage compensation module provided in an embodiment of the present application;

[0031] Figure 13 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0032] Reference numerals:

[0033] 300-common electrode compensation circuit; 301-pixel unit array; 302-data drive module; 3021-data line group; 303-timing control module; 304-digital-to-analog conversion module; 3041-voltage conversion unit; 30411-inverter; 30412-positive phase voltage conversion subunit; 30413-negative phase voltage conversion subunit; 3042-digital-to-analog converter; 3043-bit conversion unit; 305-common voltage compensation module; 306-common electrode; 1300-display device; 1301-display panel; 1302-panel frame; 1303-power supply module; 1304-data receiving module. DETAILED DESCRIPTION

[0034] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It is apparent that the described embodiments are only a portion of the embodiments of the present application, rather than all of the embodiments. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions, and numerical values ​​described in these embodiments do not limit the scope of the present application.

[0035] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of the present application are only used to distinguish between different steps, devices, modules and other objects, and neither represent any specific technical meaning nor indicate the logical order between them.

[0036] It should also be understood that in this embodiment, “a plurality of” may refer to two or more than two, and “at least one” may refer to one, two or more than two.

[0037] It should also be understood that any component, data or structure mentioned in the embodiments of the present application can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0038] In addition, the term "and / or" in this application is simply a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the related objects are in an "or" relationship.

[0039] It should also be understood that the description of each embodiment in this application focuses on the differences between the embodiments, and the same or similar aspects can be referenced with each other. For the sake of brevity, they will not be described one by one.

[0040] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0041] Technologies, circuits, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, the above-mentioned technologies, circuits, and devices should be considered part of the specification.

[0042] It should be noted that like reference numerals and letters refer to like items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0043] It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other. To facilitate understanding of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0044] Figure 3This is a structural diagram of a common electrode compensation circuit 300 provided in an embodiment of the present application. This circuit is generally used in a display panel and specifically includes: a pixel unit array 301, a data driving module 302, a timing control module 303, a digital-to-analog conversion module 304, a common voltage compensation module 305, and a common electrode 306. The data driving module includes a data line group 3021. The timing control module 303 is connected to the digital-to-analog conversion module 304 and the data driving module 302, the digital-to-analog conversion module 304 is connected to the common voltage compensation module 305, and the output end of the common voltage compensation module 305 is connected to the common electrode 306. It should be understood that Figure 3 The structure of the common electrode 306 shown is only a schematic structure. In actual scenarios, the shape, position and other properties of the common electrode 306 can be set according to actual needs.

[0045] In this embodiment, the data driving module 302 is configured to output a grayscale voltage to the pixel unit array 301 through the data line group. Figure 3 The P in the figure represents a pixel unit. Under the control of the timing signal output by the timing control module 303, the data driving module 302 can receive grayscale data externally input to each pixel unit in the currently displayed row of pixel units, convert the grayscale data into an analog voltage, and transmit the analog voltage to the currently driven row of pixel units via the data line. This analog voltage forms a voltage difference with the common electrode 306, thereby driving the pixel units to output corresponding grayscale brightness.

[0046] In this embodiment, the timing control module 303 (TCON) can be a controller with logic processing and calculation functions. The timing control module 303 is configured to: determine the first grayscale voltage measurement value corresponding to each data line in the data line group at the moment before the current moment, and the second grayscale voltage measurement value corresponding to each data line at the current moment; determine the difference between the first grayscale voltage measurement value and the second grayscale voltage measurement value corresponding to each data line; sum the obtained differences to obtain a total difference; and output the total difference value to the digital-to-analog conversion module 304.

[0047] Specifically, the current moment is the moment when the current TFT scan line controls some TFT switches to be turned on, so that the corresponding pixel units are connected to the data lines. Correspondingly, the previous moment is the moment when the previous TFT scan line controls other TFT switches to be turned on. For example, the current moment may be the moment when a TFT scan line controls the pixel units of the current row to be connected to the data lines, and the previous moment is the moment when the previous TFT scan line controls the pixel units of the previous row to be connected to the data lines. Optionally, if the pixel units driven at the current moment are the pixel units of the first row, the second grayscale voltage measurement value may be a preset fixed value. For example, it may be a grayscale voltage measurement value corresponding to 255 grayscales (if a data line is currently positive polarity, the second grayscale measurement value corresponds to 255 grayscales under positive polarity; if a data line is currently negative polarity, the second grayscale measurement value corresponds to 255 grayscales under negative polarity).

[0048] The grayscale voltage measurement value can represent the grayscale voltage on the corresponding data line. The correspondence between the grayscale voltage measurement value and the grayscale voltage can be pre-set and recorded in a table or other manner, or expressed by a formula calculation. The timing control module 303 can determine the grayscale voltage based on the grayscale value and polarity of the data line being driven at the current moment, and determine the first grayscale voltage measurement value and the second grayscale voltage measurement value based on the above correspondence. It should be noted that the grayscale voltage measurement value and the grayscale voltage can have a one-to-one correspondence, or multiple grayscale voltages can correspond to one grayscale voltage measurement value.

[0049] The formula for calculating the total difference is shown in the following formula (1):

[0050]

[0051] Among them, V ndata1 Indicates the first grayscale voltage measurement value of the nth data line at the previous moment, V ndata2 Indicates the second grayscale voltage measurement value at the previous moment.

[0052] In this embodiment, the digital-to-analog conversion module 304 is configured to convert the total difference into an analog voltage, and output the analog voltage to the common voltage compensation module 305 .

[0053] Specifically, the total difference is a digital quantity, and therefore, it is necessary to convert the digital quantity into an analog quantity using the digital-to-analog conversion module 304. Optionally, the reference voltage of the digital-to-analog conversion module 304 can match the gamma voltage of the data line. In this case, the total difference can be directly converted into an analog voltage using a DAC. In addition, when the high level of the digital signal of the total difference does not match the high level of the input digital quantity of the DAC, a voltage converter (e.g., a non-inverting proportional amplifier circuit) can be used to set the high level of the digital signal of the total difference to match the digital quantity level requirement of the DAC.

[0054] The common voltage compensation module 305 is configured to output an inverted compensation voltage to the common electrode 306 according to the variation of the analog voltage output by the digital-to-analog conversion module 304 .

[0055] Optionally, the common voltage compensation module 305 may include an inverting differential circuit, which can output a pulse voltage signal in the opposite direction of the voltage change when the input analog voltage changes. The pulse voltage signal can offset the voltage change on the common electrode 306 caused by parasitic capacitance, thereby keeping the voltage on the common electrode 306 stable.

[0056] Optionally, the common voltage compensation module 305 can also detect the change in the input analog voltage in real time (for example, through ADC, etc.). If the change exceeds a preset threshold, it can output a pulse signal that is opposite to the above change through an inverting proportional operation circuit, a delay switch, etc., thereby offsetting the voltage change caused by parasitic capacitance on the common electrode 306.

[0057] like Figure 4 As shown in FIG, it shows a waveform diagram of the inverted compensation voltage output by the common voltage compensation module 305. Among them, DATA represents the timing diagram of the data line switching output voltage, and 1H represents the voltage signal output by the data line when driving a row of pixel units to display the corresponding grayscale. Coupling VCOM is a waveform diagram of the coupling voltage mutation caused by parasitic capacitance. out is a waveform diagram of the inverse compensation voltage output by the common voltage compensation module 305. Figure 4 It can be seen that each time the pixel unit array 301 switches to display a row, the data line is coupled to the common electrode 306 once, and the inverse compensation voltage is output once. After the inverse compensation voltage is superimposed on the coupling voltage on the common electrode 306, the VCOM voltage tends to be stable.

[0058] The common electrode compensation circuit provided in the embodiment of the present application pre-records the first grayscale voltage measurement value when the pixel unit is driven at the previous moment and the second grayscale voltage measurement value when the pixel unit is driven at the current moment. The timing control module calculates the difference between the first grayscale voltage measurement value and the second grayscale voltage measurement value, and sums the differences corresponding to each data line to obtain a total difference. The digital-to-analog conversion module converts the total difference into an analog voltage. The common voltage compensation module responds to the change in the analog voltage and outputs an inverted compensation voltage, thereby achieving the inverted compensation voltage to offset the voltage mutation caused by parasitic capacitance on the common electrode, making the voltage on the common electrode more stable. Since the magnitude of the output inverted compensation voltage is obtained by comprehensively calculating the change in the actual output voltage on the data line, when the display brightness of a row of pixels is inconsistent, the brightness mutation can still be well compensated to avoid abnormal phenomena such as afterimages when displaying the picture.

[0059] In some optional implementations of this embodiment, the timing control module 303 further determines the first grayscale voltage metric value and the second grayscale voltage metric value in the following manner:

[0060] First, the first grayscale value and the first voltage polarity corresponding to each data line in the data line group at a moment before the current moment, and the second grayscale value and the second voltage polarity corresponding to each data line at the current moment are determined.

[0061] Voltage polarity refers to the polarity of the voltage on the data line compared to the common voltage on the common electrode 306. Specifically, a positive difference between the voltage on the data line and the voltage on the common electrode 306 indicates positive polarity, while a negative difference between the voltage on the data line and the voltage on the common electrode 306 indicates negative polarity. Typically, the timing control module 303 can read signals such as the polarity control signal POL (polarity inversion control signal) to determine the voltage polarity of the data line. Grayscale values ​​can also be read from the data driver module 302.

[0062] Then, a first grayscale voltage metric value corresponding to the first grayscale value and the first voltage polarity, and a second grayscale voltage metric value corresponding to the second grayscale value and the second voltage polarity are searched from a preset grayscale conversion table.

[0063] The grayscale conversion table can be set in the timing control module 303 or in another device connected to the timing control module 303. The grayscale conversion table can include two sub-tables, namely a first sub-table corresponding to positive voltage polarity and a second sub-table corresponding to negative voltage polarity. The first sub-table stores grayscale voltage measurement values ​​corresponding to grayscale values ​​(or grayscale voltages) of positive polarity, and the second sub-table stores grayscale voltage measurement values ​​corresponding to grayscale values ​​(or grayscale voltages) of negative polarity. The timing control module 303 can find the corresponding grayscale voltage measurement value based on the voltage polarity and grayscale value of the data line.

[0064] This embodiment pre-sets a grayscale conversion table to quickly determine the grayscale voltage measurement value according to the grayscale value corresponding to each data line, thereby helping to efficiently determine the voltage change on the data line and improve the efficiency of outputting the inverted compensation voltage.

[0065] In some optional implementations of this embodiment, the grayscale conversion table is pre-set as follows:

[0066] The positive polarity grayscale voltage corresponding to each grayscale value under the positive voltage polarity is determined, and the positive polarity grayscale voltage measurement value corresponding to each positive polarity grayscale value under the positive voltage polarity is calculated based on the positive polarity grayscale voltage, a preset maximum grayscale voltage and a preset coefficient.

[0067] A negative grayscale voltage corresponding to each grayscale value under negative voltage polarity is determined, and a negative grayscale voltage metric value corresponding to each negative grayscale value under negative voltage polarity is calculated based on the negative grayscale voltage, the maximum grayscale voltage and the coefficient.

[0068] Specifically, the voltage measurement value can be determined according to the following formula (2):

[0069] Vol data=(Aver Vol / Gamma)*K (2)

[0070] Where Aver Vol is the grayscale voltage calculated based on the Gamma voltage and the internal resistor string of the source IC. Gamma is the maximum grayscale voltage, i.e., 255 grayscale voltage under positive polarity. K is a preset coefficient, for example, 127.

[0071] Typically, the range of Aver Vol is 0-Vmax, where Vmax is the grayscale voltage of 255 under positive polarity. Taking half of Vmax as the common voltage on the common electrode 306, Aver Vol is negative at 0-Vmax / 2 and positive at Vmax / 2-Vmax. Under positive polarity, the grayscale voltage corresponding to the grayscale of 0-255 is Vmax / 2-Vmax, and the grayscale value is positively correlated with the grayscale voltage. Under negative polarity, the grayscale voltage corresponding to the grayscale of 255-0 is 0-Vmax / 2, and the grayscale value is negatively correlated with the grayscale voltage.

[0072] For example, if the maximum grayscale value is 255, K is 127, and the maximum grayscale voltage is 15V, the positive grayscale voltage corresponding to the 255 grayscale in positive polarity is also 15V, and the corresponding positive grayscale voltage measurement value is 127. If the negative grayscale voltage corresponding to the 255 grayscale in negative polarity is 0.46V, the corresponding negative grayscale voltage measurement value is 3.

[0073] After calculating and obtaining the positive grayscale voltage measurement value corresponding to each positive grayscale value and the negative grayscale voltage measurement value corresponding to each negative grayscale value, the grayscale conversion table can be established.

[0074] This embodiment converts each positive polarity grayscale voltage and negative polarity grayscale voltage by setting calculation formulas and parameters to obtain a digital value representing the grayscale voltage. Using the digital value to represent the grayscale voltage improves the efficiency of calculating the grayscale voltage difference on the data line at different times.

[0075] In some optional implementations of this embodiment, such as Figure 5 As shown, the digital-to-analog conversion module 304 includes a voltage conversion unit 3041 and a digital-to-analog converter 3042 .

[0076] The voltage conversion unit 3041 is used to convert the digital signal (A in ) is converted into a preset voltage to obtain a converted digital signal (A out ), wherein the preset voltage matches the switch start voltage inside the digital-to-analog converter; and outputs the converted digital signal to the digital-to-analog converter.

[0077] Specifically, the voltage conversion unit 3041 can achieve voltage conversion by providing a proportional operation circuit, a switching circuit, etc. Generally, a digital-to-analog converter includes multiple switching elements. By controlling the on or off state of each switching element, the digital signal can be converted into an analog voltage and output. The switch start voltage is the voltage that controls the on or off state of the switching element. To ensure that each switching element can be stably controlled to be turned on or off under the action of the digital signal, it is necessary to amplify the amplitude of the digital signal output by the timing control module 303 so that the high-level potential of the digital signal is greater than the above-mentioned switch start voltage to ensure that the switch inside the digital-to-analog converter can be stably turned on or off.

[0078] The digital-to-analog converter 3042 is used to convert the converted digital signal into an analog voltage (U out ), and outputs the analog voltage to the common voltage compensation module 305.

[0079] The reference voltage of the DAC 3042 is the same as the Gamma voltage, that is, the reference voltage is a positive polarity 255 grayscale voltage, and the analog voltage range output by the DAC is 0-Gamma voltage.

[0080] This embodiment provides a voltage conversion unit in the digital-to-analog conversion module to amplify the high-level amplitude of the digital signal output by the timing control module, thereby enabling the switching element in the digital-to-analog converter to be stably turned on or off, thereby improving the accuracy of the analog voltage output by the digital-to-analog converter module.

[0081] In some optional implementations of this embodiment, such as Figure 6 As shown, the digital-to-analog conversion module 304 further includes a bit conversion unit 3043 .

[0082] The bit conversion unit 3043 is used to: convert the number of bits of the digital signal representing the total difference into a preset number of bits; and output the obtained digital signal with the preset number of bits to the voltage conversion unit.

[0083] Typically, to increase computational speed, the data processed by the timing control module 303 has a relatively low bit number, such as 8 bits. To accommodate the number of bits of data processed by the digital-to-analog converter, the digital signal output by the timing control module 303 needs to be converted to 16-bit data, for example, to accommodate the digital-to-analog converter.

[0084] This embodiment sets a bit conversion unit in the digital-to-analog conversion module, which can make the digital signal representing the total difference adapt to the data processing bit number of the digital-to-analog converter, thereby helping to improve the accuracy of the analog voltage output by the analog-to-digital converter, and helping to set digital-to-analog converters with different bits in different models of panels, thereby improving the scenario adaptability of the circuit.

[0085] In some optional implementations of this embodiment, such as Figure 7 As shown, the voltage conversion unit 3041 includes an inverter 30411 , a positive-phase voltage conversion subunit 30412 , and a negative-phase voltage conversion subunit 30413 , and the inverter 30411 is connected to the negative-phase voltage conversion subunit 30413 .

[0086] The inverter 30411 is used to: in ) is inverted to obtain an inverted digital signal (A in ').

[0087] The positive phase voltage conversion subunit 30412 is used to convert the high level voltage of the digital signal representing the total difference into a preset voltage to obtain a positive phase converted digital signal.

[0088] The inverted voltage conversion subunit 30413 is used to convert the high-level voltage of the inverted digital signal into a preset voltage to obtain an inverted converted digital signal.

[0089] like Figure 8 As shown, the digital signal A in A is the digital signal representing the total difference, in ' is the inverted digital signal output by the inverter, DVDD is A in and A in 'High level amplitude. Digital signal OUT1 is the inAfter the positive phase conversion of the high-level amplification, the digital signal OUT2 is the digital signal of A in 'After high-level amplification and inversion conversion of the digital signal, AVDD is the high-level amplitude of OUT1 and OUT2.

[0090] like Figure 9 As shown, MOS transistors M2 and M3 form the positive-phase voltage conversion subunit, while M1 and M4 form the negative-phase voltage conversion subunit. When the gate input of M3 is high, M3 turns on, M4 turns off, and M3's drain is low, turning M2 on and M1 off. OUT1 outputs the amplified high-level AVDD. When the gate input of M4 is high, M4 turns on, M3 turns off, and M4's drain is low, turning M1 on and M2 off. OUT2 outputs the amplified high-level AVDD.

[0091] It should be noted that the positive phase voltage conversion subunit 30412 and the negative phase voltage conversion subunit 30413 can also adopt the same Figure 9 The circuits shown achieve their functions using different circuit structures. Any circuit capable of amplifying the high-level amplitude of a digital signal can serve as the positive-phase voltage conversion subunit and the negative-phase voltage conversion subunit. For example, an operational amplifier can be used to form a proportional operational amplifier circuit, or a voltage comparator, to achieve the functions of the positive-phase voltage conversion subunit and the negative-phase voltage conversion subunit.

[0092] This embodiment implements inversion and amplitude amplification of the digital signal representing the total difference by including an inverter, a positive-phase voltage conversion sub-unit, and a negative-phase voltage conversion sub-unit in the voltage conversion unit. The output positive-phase converted digital signal and the output negative-phase converted digital signal can match the level requirement of the digital-to-analog converter, which helps to make the analog voltage output of the digital-to-analog converter more stable.

[0093] In some optional implementations of this embodiment, the digital-to-analog converter includes a reference voltage input terminal, a positive-phase digital signal input terminal, and a negative-phase digital signal input terminal.

[0094] The reference voltage input terminal receives the maximum grayscale voltage. Typically, the maximum grayscale voltage corresponds to a grayscale value of 255 in positive polarity. Setting the reference voltage to the maximum grayscale voltage causes the analog voltage output by the DAC to range from 0 to the maximum grayscale voltage.

[0095] The positive-phase digital signal input terminal is used to receive an input digital signal after positive-phase conversion, and the negative-phase digital signal input terminal is used to receive an input digital signal after negative-phase conversion.

[0096] The positive-phase digital signal input terminal and the negative-phase digital signal input terminal are respectively connected to the control terminals of multiple switches, and the analog voltage corresponding to the digital signal after positive-phase conversion is output through the combination of multiple switches.

[0097] like Figure 10 As shown, it shows an exemplary circuit structure diagram of a digital-to-analog converter. Due to space limitations, Figure 10 The input data of the digital-to-analog converter shown is 3-bit data. The actual analog-to-digital converter used can input 8-bit data, 12-bit data, 16-bit data, etc. The principles and structures of digital-to-analog converters with different bit numbers are similar. Here, only the 3-bit digital-to-analog converter is used to illustrate the implementation principle.

[0098] Figure 10 D2, D1, and D0 are the positive-phase converted digital signals output by the positive-phase voltage conversion subunit. That is, the inverted converted digital signal output by the inverted voltage conversion subunit. Figure 9 V0-V7 are the voltage values ​​after the maximum grayscale voltage is evenly divided into 8 segments.

[0099] like Figure 10 As shown, when D2, D1, and D0 input the binary number 100, When the binary number 011 is input, the MOS tube marked with "×" in the figure is cut off, and the other MOS tubes are turned on. Therefore, V out =V4. That is, when the total difference is the decimal number 4, the output analog voltage is V4.

[0100] This embodiment provides a combination of multiple switching elements in the digital-to-analog converter to receive the input positive-phase digital signal and negative-phase digital signal, thereby stably controlling the on and off states of each switching element within the digital-to-analog converter, thereby helping to more accurately output the analog voltage corresponding to the above-mentioned total difference and improving the accuracy and stability of the output negative-phase compensation voltage.

[0101] In some optional implementations of this embodiment, such as Figure 11 As shown, the common voltage compensation module 305 includes an operational amplifier OA, a feedback resistor R, a compensation resistor R′, a current limiting resistor Ri and a differential capacitor C1.

[0102] like Figure 11 As shown, one end of the current limiting resistor Ri is connected to the output end of the digital-to-analog conversion module 304, and the other end is connected to the differential capacitor; one end of the differential capacitor C1 is connected to the current limiting resistor, and the other end is connected to the inverting input end of the operational amplifier OA; one end of the feedback resistor R is connected to the inverting input end, and the other end is connected to the output end of the operational amplifier OA; one end of the compensation resistor R' is connected to the non-inverting input end of the operational amplifier OA, and the other end is connected to the common electrode (VCOM).

[0103] Figure 11 The circuit shown constitutes an inverting differential circuit, V out The analog voltage signal output by the digital-to-analog conversion module 304 is used by the current-limiting resistor Ri to limit the input current; the compensation resistor R' is used to ensure the symmetry of the external resistors of the differential amplifier circuit at the input stage of the operational amplifier. The current on the feedback resistor R is Output voltage It can be seen that the output voltage and the rate of change of the input voltage are in a differential relationship and have opposite phases.

[0104] Optional, such as Figure 12 As shown, a diode D can also be connected in parallel with the feedback resistor R to ensure that the operational amplifier operates in the amplification region.

[0105] This embodiment responds to changes in the analog voltage output by the digital-to-analog conversion module by providing an inverting differential circuit in the common voltage compensation module, and outputs a compensation voltage with a polarity opposite to the coupled mutation voltage on the common electrode. This allows the analog circuit with a simple structure to compensate for the voltage mutation on the common electrode in a timely manner, thereby improving the timeliness of the output compensation voltage and making the voltage on the common electrode more stable.

[0106] In some optional implementations of this embodiment, such as Figure 12 As shown, the common voltage compensation module 305 further includes a phase compensation capacitor C2 , one end of the phase compensation capacitor C2 is connected to the inverting input terminal, and the other end is connected to the output terminal of the operational amplifier.

[0107] By setting a phase compensation capacitor, the phase of the inverted compensation voltage signal output by the differential circuit can be adjusted so that the phase of the inverted compensation voltage and the coupling voltage generated by the parasitic capacitance on the common electrode 306 tend to be consistent, thereby more effectively offsetting the coupling voltage and further improving the stability of the voltage on the common electrode 306.

[0108] Figure 13 A schematic diagram of the structure of a display device 1300 provided in an embodiment of the present application is shown in FIG. Figure 13 As shown, the display device includes:

[0109] Display panel 1301, panel frame 1302, power module 1303 and data receiving module 1304;

[0110] The display panel 1301 includes the common electrode compensation circuit. The display panel 1301 is mounted on a panel frame 1302 .

[0111] The power supply end of the display panel 1301 is connected to the power module 1303 , and the signal receiving end of the display panel 1301 is connected to the data receiving module 1304 .

[0112] The power module 1303 can provide the display panel 1301 with the power required for operation. The data receiving module 1304 can receive input data. The display panel 1301 drives corresponding pixels to display corresponding colors according to the received data.

[0113] In addition, the display device Figure 13 In addition to the parts shown, it may also include a memory for storing data and programs, a processor for running application programs, a data transmission bus, various data interfaces (such as a network interface, a user interface), etc.

[0114] The display device provided in the embodiment of the present application, by providing the above-mentioned common electrode compensation circuit, realizes compensation for the coupling voltage generated by the parasitic capacitance on the common electrode when the voltage output by the data line suddenly changes, so as to offset the voltage mutation on the common electrode, thereby avoiding the brightness mutation on the display screen and improving the stability of the display screen.

[0115] Professionals should also be further aware that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different circuits to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0116] The steps of the circuits or algorithms described in conjunction with the embodiments disclosed herein may be implemented using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0117] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an", and "said" as used herein may also be meant to include plural forms. The terms "comprise", "include", "contain", and "have" are inclusive and therefore specify the presence of the stated features, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The circuit steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0118] The foregoing is merely a list of specific embodiments of the present application, intended to enable those skilled in the art to understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the broadest scope consistent with the principles and novel features of the present application.

Claims

1. A common electrode compensation circuit, characterized in that: The circuit includes: a pixel unit array, a data driving module, a timing control module, a digital-to-analog conversion module, a common voltage compensation module and a common electrode, the data driving module includes a data line group, the data line group is connected to the pixel units in the pixel unit array, the timing control module is connected to the data driving module and the digital-to-analog conversion module, the digital-to-analog conversion module is connected to the common voltage compensation module, and the output end of the common voltage compensation module is connected to the common electrode; The data driving module is used to output a grayscale voltage to the pixel unit array through the data line group under the control of the timing signal output by the timing control module; The timing control module is configured to: determine a first grayscale voltage measurement value corresponding to each data line in the data line group at a moment before a current moment, and a second grayscale voltage measurement value corresponding to each data line at a current moment; determine a difference between the first grayscale voltage measurement value and the second grayscale voltage measurement value corresponding to each data line; sum the obtained differences to obtain a total difference; and output the total difference to the digital-to-analog conversion module; The digital-to-analog conversion module is used to: convert the total difference into an analog voltage, and output the analog voltage to the common voltage compensation module; The common voltage compensation module is used to: output an inverted compensation voltage to the common electrode according to the change in the analog voltage output by the digital-to-analog conversion module; The digital-to-analog conversion module includes a voltage conversion unit and a digital-to-analog converter; The voltage conversion unit is configured to: convert a high-level voltage of the digital signal representing the total difference into a preset voltage to obtain a converted digital signal, wherein the preset voltage matches a switch start voltage within the digital-to-analog converter; and output the converted digital signal to the digital-to-analog converter; The digital-to-analog converter is used to: convert the converted digital signal into an analog voltage, and output the analog voltage to the common voltage compensation module; The voltage conversion unit includes an inverter, a positive-phase voltage conversion subunit and a negative-phase voltage conversion subunit, wherein the inverter is connected to the negative-phase voltage conversion subunit; The inverter is used to: perform an inversion operation on the digital signal representing the total difference to obtain an inverted digital signal; The positive phase voltage conversion subunit is used to: convert the high level voltage of the digital signal representing the total difference into a preset voltage to obtain a positive phase converted digital signal; The inverted voltage conversion subunit is used to convert the high-level voltage of the inverted digital signal into a preset voltage to obtain an inverted converted digital signal.

2. The circuit according to claim 1, wherein: The timing control module is further configured to: Determining a first grayscale value and a first voltage polarity corresponding to each data line in the data line group at a moment before the current moment, and a second grayscale value and a second voltage polarity corresponding to each data line at the current moment; A first grayscale voltage metric value corresponding to the first grayscale value and the first voltage polarity, and a second grayscale voltage metric value corresponding to the second grayscale value and the second voltage polarity are searched from a preset grayscale conversion table.

3. The circuit according to claim 2, characterized in that The grayscale conversion table is pre-set as follows: Determining a positive polarity grayscale voltage corresponding to each grayscale value under a positive voltage polarity, and calculating a positive grayscale voltage metric value corresponding to each positive polarity grayscale value under the positive voltage polarity based on the positive polarity grayscale voltage, a preset maximum grayscale voltage, and a preset coefficient; A negative grayscale voltage corresponding to each grayscale value under negative voltage polarity is determined, and a negative grayscale voltage metric value corresponding to each negative grayscale value under negative voltage polarity is calculated based on the negative grayscale voltage, the maximum grayscale voltage and the coefficient.

4. The circuit according to claim 1, wherein: The digital-to-analog conversion module also includes a bit conversion unit; The bit conversion unit is used to: convert the number of bits of the digital signal representing the total difference into a preset number of bits; and output the obtained digital signal with the preset number of bits to the voltage conversion unit.

5. The circuit according to claim 1, wherein: The digital-to-analog converter includes a reference voltage input terminal, a positive-phase digital signal input terminal, and a negative-phase digital signal input terminal; The reference voltage input terminal is used to receive an input maximum grayscale voltage; The positive-phase digital signal input terminal is used to receive an input positive-phase converted digital signal, and the negative-phase digital signal input terminal is used to receive an input negative-phase converted digital signal; The positive-phase digital signal input terminal and the negative-phase digital signal input terminal are respectively connected to control terminals of a plurality of switches, and an analog voltage corresponding to the positive-phase converted digital signal is output through a combination of the plurality of switches.

6. The circuit according to claim 1, wherein: The common voltage compensation module includes an operational amplifier, a feedback resistor, a compensation resistor, a current limiting resistor and a differential capacitor; One end of the current limiting resistor is connected to the output end of the digital-to-analog conversion module, and the other end is connected to the differential capacitor; One end of the differential capacitor is connected to the current limiting resistor, and the other end is connected to the inverting input terminal of the operational amplifier; One end of the feedback resistor is connected to the inverting input terminal, and the other end is connected to the output terminal of the operational amplifier; One end of the compensation resistor is connected to the non-inverting input terminal of the operational amplifier, and the other end is connected to the common electrode.

7. The circuit according to claim 6, characterized in that The common voltage compensation module further includes a phase compensation capacitor, one end of which is connected to the inverting input terminal, and the other end of which is connected to the output terminal of the operational amplifier.

8. A display device, characterized in that: include: A display panel, a panel frame, a power module and a data receiving module, wherein the display panel includes the common electrode compensation circuit according to any one of claims 1 to 7; The display panel is mounted on the panel frame, a power supply end of the display panel is connected to the power module, and a signal receiving end of the display panel is connected to the data receiving module.

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