Quantum circuit generation method and device based on balanced boolean function and electronic equipment

Abstract

The present disclosure provides a quantum circuit generation method and device based on balanced Boolean functions and electronic equipment, relating to the technical field of quantum information technology. The quantum circuit generation method based on balanced Boolean functions comprises: extracting a minimum term set from a global truth table of a balanced Boolean function; determining at least one target minimum term set based on the mapping positions of a plurality of minimum terms in Euclidean space; and mapping the at least one target minimum term set on a quantum circuit using a double control non-gate to generate a target quantum circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of quantum information technology, and more particularly, to a quantum circuit generation method and device based on balanced Boolean functions and an electronic device. BACKGROUND

[0002] As a basic role in the design of a classical computer chip, a Boolean function is different from a classical computer in that many classical logic operations are not easy to constitute in a quantum circuit, such as an AND operation; on the contrary, an XOR operation is naturally implemented by a CNOT gate. Therefore, it is necessary to effectively implement a Boolean function.

[0003] Existing quantum circuit synthesis methods include an XOR and graph (XAG) method and an ESOP method. The XAG method uses XOR and AND logic gates to represent a function, however, the XAG method needs to use auxiliary bits to store intermediate results, which increases the complexity of the circuit and the possible error rate. The ESOP method usually needs a large number of multi-control Toffoli (MCT) gates and control bits, and as the number of control bits increases, the complexity of the multi-control Toffoli gate operation also increases, thereby increasing the possibility of errors, and thus the fidelity of these quantum gates in the quantum circuit is low. SUMMARY

[0004] Therefore, the present disclosure provides a quantum circuit generation method and device based on balanced Boolean functions and an electronic device.

[0005] One aspect of the present disclosure provides a quantum circuit generation method based on balanced Boolean functions, comprising: extracting a minimum term set from a global truth table of the balanced Boolean function; determining at least one target minimum term set based on the mapping positions of the plurality of minimum terms in the Euclidean space; and mapping the at least one target minimum term set on the quantum circuit using a double control non-gate to generate a target quantum circuit.

[0006] According to an embodiment of the present disclosure, the determination of the at least one target minimum term set based on the mapping positions of the plurality of minimum terms in the Euclidean space comprises: determining at least one candidate minimum term set from the minimum term set; adjusting the quantum bit states included in the at least one candidate minimum term set using a single control non-gate and / or a three control non-gate until the mapping positions of the four candidate minimum terms included in the candidate minimum term set in the Euclidean space satisfy the parallelogram condition, in the case that the mapping positions of the four candidate minimum terms included in the candidate minimum term set in the Euclidean space do not satisfy the parallelogram condition; and determining the candidate minimum term set that satisfies the parallelogram condition as a target minimum term set.

[0007] According to an embodiment of the present disclosure, the adjusting, by the single control NOT gate and / or the three control NOT gate, the quantum bit state included in the at least one candidate minterm until the mapping positions of the four candidate minterms included in the candidate minterm set in the Euclidean space satisfy the parallelogram condition comprises: adjusting, by the single control NOT gate and / or the three control NOT gate, the quantum bit state included in the at least one candidate minterm to obtain an adjusted quantum bit state of the at least one candidate minterm; and updating the mapping positions of the at least one candidate minterm in the Euclidean space based on the adjusted quantum bit state of the at least one candidate minterm until the mapping positions of the four candidate minterms included in the candidate minterm set in the Euclidean space satisfy the parallelogram condition.

[0008] According to an embodiment of the present disclosure, the mapping, by the two control NOT gate, the at least one target minterm set on the quantum circuit to generate the target quantum circuit comprises: mapping, by the two control NOT gate, the at least one target minterm set on the quantum circuit to generate a first target sub-circuit; updating the minterm set based on the four target minterms included in the at least one target minterm set to obtain an updated minterm set, wherein the updated minterm set includes remaining minterms other than the four target minterms; mapping, by the two control NOT gate, the updated minterm set on the quantum circuit to generate a second target sub-circuit; and obtaining the target quantum circuit based on the first target sub-circuit and the second target sub-circuit.

[0009] According to an embodiment of the present disclosure, the mapping, by the two control NOT gate, the updated minterm set on the quantum circuit to generate the second target sub-circuit comprises: in a case where the mapping positions of the four remaining minterms included in the updated minterm set in the Euclidean space do not satisfy the parallelogram condition, adjusting, by the single control NOT gate and / or the three control NOT gate, the quantum bit state included in the at least one remaining minterm until the mapping positions of the four remaining minterms in the Euclidean space satisfy the parallelogram condition; determining the four remaining minterms satisfying the parallelogram condition as a target remaining minterm set; and mapping, by the two control NOT gate, the target remaining minterm set on the quantum circuit to generate the second target sub-circuit.

[0010] According to an embodiment of the present disclosure, the method further comprises: mapping combinations of a plurality of quantum bit states included in the global truth table at a plurality of vertices included in a preset cubic configuration in the Euclidean space according to an initial mapping relationship to determine mapping positions of a plurality of minterms included in the minterm set in the Euclidean space.

[0011] According to an embodiment of the present disclosure, the method further includes packaging a plurality of quantum gates included in the target quantum circuit to obtain a packaging module of the target quantum circuit, wherein the packaging module is configured to provide an input / output interface of a Cirq library.

[0012] Another aspect of the present disclosure provides a quantum circuit generation device based on a balanced Boolean function, comprising: an extraction module configured to extract a plurality of minimal terms from a global truth table of the balanced Boolean function; a determination module configured to determine at least one target minimal term set based on mapping positions of the plurality of minimal terms in a Euclidean space; and a mapping module configured to map the at least one target minimal term set on the quantum circuit using a double-controlled NOT gate to generate a target quantum circuit.

[0013] Another aspect of the present disclosure provides an electronic device, comprising: one or more processors; a memory configured to store one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method described above.

[0014] Another aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the instructions, when executed, implement the method described above.

[0015] Another aspect of the present disclosure provides a computer program product, comprising computer-executable instructions, wherein the instructions, when executed, implement the method described above.

[0016] According to an embodiment of the present disclosure, by extracting all possible minimal terms in the global truth table of the quantum bit balanced Boolean function, and based on the parallelogram condition of geometric representation, all possible minimal terms are synthesized into a target quantum circuit using a double-controlled NOT gate, thereby realizing the conversion from the input truth table to the target quantum circuit without using auxiliary bits, reducing the complexity and resource requirements of the circuit; in addition, the complex circuit function can also be better realized in the case of fewer control bits. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A flowchart of a quantum circuit generation method based on a balanced Boolean function according to an embodiment of the present disclosure is schematically shown;

[0019] Figure 2schematic diagram of a global truth table based on a geometric representation according to embodiments of the present disclosure is schematically shown;

[0020] Figure 3 a schematic diagram of a target quantum circuit according to embodiments of the present disclosure is schematically shown;

[0021] Figure 4 a schematic diagram of a global truth table based on a geometric representation according to embodiments of the present disclosure is schematically shown;

[0022] Figure 5 a schematic diagram of a target quantum circuit according to another embodiment of the present disclosure is schematically shown;

[0023] Figure 6 a block diagram of a quantum circuit generation apparatus based on a balanced Boolean function according to embodiments of the present disclosure is schematically shown; and

[0024] Figure 7 a block diagram of an electronic device adapted to implement a quantum circuit generation method based on a balanced Boolean function according to embodiments of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely exemplary and is not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it would be apparent to one skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present disclosure.

[0026] The terms used herein are merely used to describe specific embodiments and are not intended to limit the present disclosure. The terms "include", "comprise", and the like used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0027] All terms used herein, including technical and scientific terms, have the same meanings as those generally understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of the present specification, and should not be interpreted in an idealized or excessively formal manner.

[0028] In the case of using expressions like "at least one of A, B, and C", it will be understood that the phrase is meant to mean any of the individual permutations, e.g., A alone, B alone, C alone, A and B together, A and C together, B and C together, as well as A and B and C together.

[0029] In a quantum computer, the execution of a quantum algorithm generally needs to go through multiple steps such as program generation, hardware-related program compilation, actual hardware execution, etc. Among them, quantum program generation is to convert the calculation process in the algorithm into a quantum program circuit from the quantum algorithm. The implementation of any quantum algorithm needs to first design a corresponding quantum function and quantum circuit, use appropriate quantum gates and quantum functions to implement corresponding operations, and thus execute the corresponding algorithm.

[0030] As a basic role in the design of a classical computer chip, a Boolean function is different from a classical computer in that many classical logic operations are not easy to constitute in a quantum circuit, such as an AND operation; on the contrary, an XOR operation is naturally implemented by a CNOT gate. Therefore, it is very necessary to effectively implement a Boolean function. However, due to the special nature of quantum computing, there are fidelity problems, quantum decoherence, and continuous quantum error correction in quantum gate operations. These distortion effects will be superimposed, resulting in a greater possibility of error results. Therefore, it is particularly important to design an efficient quantum circuit to implement a Boolean function.

[0031] Existing quantum circuit synthesis methods include an XOR-AND graph (XAG) method and an exclusive sum of products (ESOP) method. The XAG method uses XOR and AND logic gates to represent a function, however, the XAG method needs to use auxiliary bits to store intermediate results, which increases the complexity of the circuit and the possible error rate. The ESOP method usually needs a large number of multi-control Toffoli (MCT) gates and control bits. With the increase in the number of control bits, the complexity of the multi-control Toffoli gate operation also increases, thereby increasing the possibility of errors, so the fidelity of these gates in the quantum circuit is low.

[0032] Therefore, the embodiment of the present disclosure extracts all possible minterms in the global truth table of the quantum bit balanced Boolean function, and synthesizes all possible minterms into a target quantum circuit by using a double control non-gate based on the parallelogram condition of geometric representation, so as to realize the conversion from the input truth table to the target quantum circuit without using auxiliary bits, thereby reducing the complexity and resource demand of the circuit; in addition, the complex circuit function can be better realized under the condition of fewer control bits.

[0033] Specifically, the embodiment of the present disclosure provides a quantum circuit generation method based on a balanced Boolean function, comprising: extracting a set of minterms from a global truth table of a balanced Boolean function; determining at least one target minterm set based on the mapping positions of a plurality of minterms in the Euclidean space; and mapping the at least one target minterm set on a quantum circuit by using a double control non-gate to generate a target quantum circuit.

[0034] It should be noted that the quantum circuit generation method, device and electronic equipment based on a balanced Boolean function determined by the embodiment of the present disclosure can be used in the field of quantum information technology, such as the field of quantum circuit mapping technology and the field of quantum computing technology. The parallel mapping method and device of the quantum circuit determined by the embodiment of the present disclosure can also be used in any field other than the field of quantum information technology, and the application field of the parallel mapping method and device of the quantum circuit determined by the embodiment of the present disclosure is not limited.

[0035] According to the embodiment of the present disclosure, a quantum bit is the most basic unit in quantum computing, which can represent the superposition state of 0 and 1, and a quantum logic gate is the most basic control mode in quantum computing. In quantum computing, we may use quantum logic gates and quantum circuits to construct and operate quantum bits to achieve the purpose of controlling the circuit. Among them, the quantum logic gate includes a single-bit quantum logic gate and a multi-bit quantum logic gate.

[0036] According to the embodiment of the present disclosure, the number of quantum bits can be represented by a digital subscript in a quantum algorithm or quantum program, for example, a group of quantum bits q0, q1, q2 can represent the 0th, 1st and 2nd quantum bits respectively.

[0037] According to the embodiment of the present disclosure, a Boolean function can be related to describing and processing logical problems, which accepts one or more Boolean values (i.e. true or false, usually represented by 1 and 0) as input and returns a Boolean value as output. The input of a Boolean function can be one or more Boolean variables, and the output is a single Boolean value, which is calculated based on the value of the input Boolean variable. This calculation is performed by logical operators (such as AND, OR, NOT, etc.). In quantum computing, the input and output of a Boolean function can be quantum bits.

[0038] According to an embodiment of the present disclosure, a balanced Boolean function is used to represent a Boolean function whose number of outputs of 1 and number of outputs of 0 are approximately equal for all possible inputs of the function. Specifically, for an n-ary Boolean function (i.e., a function that accepts n Boolean values as inputs), if the number of outputs of 1 is equal to the number of outputs of 0, or the difference between the two is no more than 1, among all 2^n possible input combinations of the function, the function is referred to as a balanced Boolean function.

[0039] Figure 1 A flowchart of a method for generating a quantum circuit based on a balanced Boolean function according to an embodiment of the present disclosure is schematically shown.

[0040] As shown in Figure 1 , the method includes operations S101-S103.

[0041] In operation S101, a set of minterms is extracted from a global truth table of a balanced Boolean function.

[0042] According to an embodiment of the present disclosure, the global truth table of a balanced Boolean function can be used to represent a complete list of input variable combinations of the balanced Boolean function and their corresponding calculation values. The calculation values can be used to represent the output results of the balanced Boolean function.

[0043] Specifically, for a balanced Boolean function with n inputs, the global truth table of the function has 2 n rows, each row representing a possible input variable combination, each column representing a proposition or a logical expression, and the true or false values of the propositions or expressions. Among the 2 n possible input variable combinations, the number of rows with output results of 1 and the number of rows with output results of 0 are approximately equal.

[0044] According to an embodiment of the present disclosure, in quantum computing, due to the characteristics of quantum computing, the input quantum bits and the output quantum bits can not directly represent a certain value (e.g., 0 or 1), but are in a superposition state. By measuring the input quantum bit state and the output quantum bit state, the quantum bit state can be determined to be 0 or 1. Therefore, in the global truth table corresponding to a balanced Boolean function with multiple quantum bit states as input variables, each row can represent a possible combination of quantum bit states, and each column can represent a measurement result of a quantum bit state.

[0045] For example, based on a 4-qubit balanced Boolean function, the input variables are four qubits q0, q1, q2, q3. If the states of the four qubits are measured, 16 rows of possible combinations of qubit states and measurement results of each qubit state can be obtained to form a global truth table of the 4-qubit balanced Boolean function. Among them, the combinations of qubit states with output result of 1 and the combinations of qubit states with output result of 0 can each have 8 rows. The combinations of qubit states can be represented in binary, such as (q0, q1, q2, q3) represented as 1111 and (q0', q1', q2', q3') represented as 0000.

[0046] According to an embodiment of the present disclosure, in the global truth table of the balanced Boolean function, each row of the combination of qubit states with output result of 1 can be regarded as a minterm. A plurality of combinations of qubit states with output result of 1 are extracted from the global truth table to form a set of minterms. In a specific embodiment of the present disclosure, the set of minterms can include all minterms in the global truth table.

[0047] In operation S102, at least one target minterm set is determined based on the mapping positions of the plurality of minterms in the Euclidean space.

[0048] According to an embodiment of the present disclosure, the combination of qubit states of each minterm in the set of minterms can be regarded as a mapping point in the Euclidean space. Based on the mapping positions of the plurality of minterms in the Euclidean space, a target minterm set satisfying a parallelogram condition can be determined. The target minterm set includes four minterms in the set of minterms that satisfy the parallelogram condition. The parallelogram condition can be used to represent that the four minterms form a parallelogram in the Euclidean space.

[0049] According to a specific embodiment of the present disclosure, the mapping positions of the plurality of minterms in the Euclidean space can be determined based on the coordinates of the mapping points. The parallelogram condition can further include that the four minterms satisfy the geometric properties of the parallelogram in the Euclidean space. For example, if the coordinates of the four points A, B, C, D corresponding to any four minterms in the plurality of minterms in the Euclidean space satisfy the vector relationship that vector AB is equal to vector DC and vector BC is equal to vector AD, it can be considered that the four minterms satisfy the parallelogram condition.

[0050] In operation S103, the at least one target minterm set is mapped on a quantum circuit using a double-controlled NOT gate to generate a target quantum circuit.

[0051] According to an embodiment of the present disclosure, in quantum computing, a double-controlled NOT gate (also referred to as a Toffoli gate or a CCNOT gate) is a three-qubit gate with one target bit and two control bits, and the double-controlled NOT gate can be used to perform a NOT operation on the target qubit based on the states of the two control bits, that is, to flip the state of the target qubit.

[0052] According to an embodiment of the present disclosure, the double-controlled NOT gate can be used to map the target set of minterms satisfying the parallelogram to a quantum circuit, and to synthesize a sub-circuit performing four minterm operations in the target minterm until all minterms included in the set of minterms are synthesized into the quantum circuit to generate the target quantum circuit. In addition, the single-controlled NOT gate and the double-controlled NOT gate can be combined to synthesize the target set of minterms satisfying the parallelogram.

[0053] According to an embodiment of the present disclosure, by extracting all possible minterms in the global truth table of the quantum bit balanced Boolean function, and using the double-controlled NOT gate to synthesize all possible minterms into the target quantum circuit based on the parallelogram condition of the geometric representation, the conversion from the input truth table to the target quantum circuit is realized without using auxiliary bits, thereby reducing the complexity and resource requirements of the circuit. In addition, the complex circuit function can also be well realized in the case of a small number of control bits.

[0054] According to an embodiment of the present disclosure, based on the mapping positions of the plurality of minterms in the Euclidean space, determining the at least one target set of minterms includes: determining at least one candidate set of minterms from the set of minterms; in the case that the mapping positions of the four candidate minterms included in the candidate set of minterms in the Euclidean space do not satisfy the parallelogram condition, adjusting the mapping positions of the at least one candidate minterm in the Euclidean space using the single-controlled NOT gate and / or the triple-controlled NOT gate until the mapping positions of the four candidate minterms included in the candidate set of minterms in the Euclidean space satisfy the parallelogram condition; and determining the candidate set of minterms satisfying the parallelogram condition as the target set of minterms.

[0055] According to an embodiment of the present disclosure, the candidate set of minterms includes four candidate minterms, and the four candidate minterms can be any four minterms included in the set of minterms.

[0056] According to an embodiment of the present disclosure, the single-controlled NOT gate (also referred to as a CNOT gate) is a two-qubit gate with one target bit and one control bit, and the single-controlled NOT gate can perform a NOT operation on the target qubit based on the state of the control bit, that is, to flip the state of the target qubit.

[0057] According to an embodiment of the present disclosure, a three-control NOT gate (also referred to as a 3-MCT gate) is a four-qubit gate having one target qubit and three control qubits, and the three-control NOT gate can perform a NOT operation on the target qubit based on the states of the three control qubits, i.e., flip the state of the target qubit.

[0058] According to an embodiment of the present disclosure, for each candidate minterm set including four minterms, it is determined whether the mapping positions of the four minterms in the Euclidean space satisfy the parallelogram condition. If the parallelogram condition is satisfied, the candidate minterm set can be determined as the target minterm set. If the parallelogram condition is not satisfied, the quantum bit states included in one or more candidate minterms of the four candidate minterms can be adjusted by using a single-control NOT gate and / or a three-control NOT gate.

[0059] According to an embodiment of the present disclosure, adjusting the mapping positions of the at least one candidate minterm in the Euclidean space by using the single-control NOT gate and / or the three-control NOT gate until the mapping positions of the four candidate minterms included in the candidate minterm set in the Euclidean space satisfy the parallelogram condition includes: adjusting the quantum bit states included in the at least one candidate minterm by using the single-control NOT gate and / or the three-control NOT gate to obtain adjusted quantum bit states of the at least one candidate minterm; and updating the mapping positions of the at least one candidate minterm in the Euclidean space based on the adjusted quantum bit states of the at least one candidate minterm until the mapping positions of the four candidate minterms included in the candidate minterm set in the Euclidean space satisfy the parallelogram condition.

[0060] According to an embodiment of the present disclosure, for the spatial properties of the four candidate minterms included in the candidate minterm set, the state of the target quantum bit is flipped according to the state of the control quantum bit by using the single-control NOT gate and / or the three-control NOT gate to realize the conversion of the quantum bit states of one or more candidate minterms, thereby indirectly updating the mapping positions of the candidate minterms in the Euclidean space.

[0061] For example, the conversion from the combination 1100 of the measured quantum bit states in the binary representation to 0010 can be realized by using a three-control NOT gate or a combination of a single-control NOT gate and a double-control NOT gate, and in this scenario, the three-control NOT gate or the combination of the single-control NOT gate and the double-control NOT gate can represent (1100, 0010).

[0062] According to an embodiment of the present disclosure, based on the mapping positions of the adjusted quantum bit states of the at least one candidate minimal term in the multi-dimensional space, it is determined whether the mapping positions of the four currently selected candidate minimal terms in the Euclidean space satisfy the parallelogram condition, and if the parallelogram condition is not satisfied, the above steps are repeated to select another candidate minimal term for adjustment until the mapping positions of all selected candidate minimal terms in the Euclidean space satisfy the parallelogram condition.

[0063] According to an embodiment of the present disclosure, in the case where the four candidate minimal terms satisfy the parallelogram condition, the quantum gate used for adjusting the quantum bit state and the double-controlled NOT gate used for generating the target quantum circuit can be synthesized on the quantum circuit to obtain the final target quantum circuit.

[0064] Embodiments of the present disclosure adjust the quantum bit state by using a triple-controlled NOT gate and / or a combination of a single-controlled NOT gate and a double-controlled NOT gate, so that the candidate minimal term set satisfies the geometric constraint condition of the parallelogram, so as to construct these minimal terms into a target quantum circuit by using a double-controlled NOT gate, thereby improving the flexibility of quantum circuit synthesis generation and also helping to reduce the number of quantum gate operations to reduce the complexity of quantum computing.

[0065] According to an embodiment of the present disclosure, mapping the at least one target minimal term set on the quantum circuit by using the double-controlled NOT gate to generate the target quantum circuit comprises: mapping the at least one target minimal term set on the quantum circuit by using the double-controlled NOT gate to generate a first target sub-circuit; updating the minimal term set based on the four target minimal terms included in the at least one target minimal term set to obtain an updated minimal term set; mapping the updated minimal term set on the quantum circuit by using the double-controlled NOT gate to generate a second target sub-circuit; and obtaining the target quantum circuit based on the first target sub-circuit and the second target sub-circuit.

[0066] According to an embodiment of the present disclosure, for the first target minimal term set satisfying the parallelogram condition, the logical functions of the four minimal terms in the target minimal term set are mapped to the quantum circuit by using the double-controlled NOT gate or the combination of the single-controlled NOT gate and the double-controlled NOT gate to generate the first target sub-circuit.

[0067] According to an embodiment of the present disclosure, after generating the first target sub-circuit, the minimal term set is updated based on the four target minimal terms included in the first target minimal term set that has been processed. Specifically, the four target minimal terms that have been implemented in the first target sub-circuit can be removed from the initial minimal term set to obtain an updated minimal term set composed of remaining minimal terms.

[0068] According to an embodiment of the present disclosure, if the mapping positions of the four remaining min terms included in the updated min term set in the Euclidean space do not satisfy the parallelogram condition, the quantum bit states included in at least one of the remaining min terms are adjusted by using a single control NOT gate and / or a three control NOT gate until the mapping positions of the four remaining min terms in the Euclidean space satisfy the parallelogram condition.

[0069] According to an embodiment of the present disclosure, the four remaining min terms satisfying the parallelogram condition are determined as a target remaining min term set.

[0070] According to an embodiment of the present disclosure, the remaining min terms in the target remaining min term set are mapped on the quantum circuit by using a double control NOT gate or a combination of a single control NOT gate and a double control NOT gate to generate a second target sub-circuit, and the four target min terms that have been implemented in the second target sub-circuit are removed from the updated min term set.

[0071] According to an embodiment of the present disclosure, the first target sub-circuit and the second target sub-circuit are combined together to form a complete target quantum circuit.

[0072] Embodiments of the present disclosure reduce the complexity of the overall circuit by converting the target min term set into a plurality of target sub-circuits until all the min terms included in the min term set are converted into the target quantum circuit through continuous iteration, where each target sub-circuit is constructed based on a group of simple min terms that satisfy a certain condition, thereby constructing a complex quantum circuit in a modular manner.

[0073] According to an embodiment of the present disclosure, the quantum circuit generation method based on the balanced Boolean function further includes: mapping the combinations of the plurality of quantum bit states included in the global truth table at the plurality of vertices included in the preset cubic configuration in the Euclidean space according to the initial mapping relationship, to determine the mapping positions of the plurality of min terms included in the min term set in the Euclidean space.

[0074] According to an embodiment of the present disclosure, the plurality of quantum gates included in the target quantum circuit are packaged to obtain a packaging module of the target quantum circuit.

[0075] According to an embodiment of the present disclosure, in the process of optimizing the quantum circuit, equivalent conversion of quantum gates, merging adjacent gates, or applying quantum compilation and circuit optimization algorithms can be used to reduce the number and complexity of gates in the circuit.

[0076] According to an embodiment of the present disclosure, the optimized target quantum circuit can be packaged as a function or a class that accepts input quantum bits and applies the circuit logic of the target quantum circuit, so as to be reused in other quantum algorithms.

[0077] According to an embodiment of the present disclosure, for a packaged circuit, an input / output interface of a database can be provided, such as an interface of an open source Cirq library, so as to directly generate a circuit that can be used by the same. Among them, the Cirq library provides rich interfaces and functions to support the creation, simulation and execution of quantum circuits.

[0078] Figure 2 A schematic diagram of a global truth table based on a geometric representation according to an embodiment of the present disclosure is schematically shown.

[0079] Figure 3 A schematic diagram of a target quantum circuit according to an embodiment of the present disclosure is schematically shown.

[0080] According to an embodiment of the present disclosure, the global truth table based on the 4-qubit balanced Boolean function is shown in Table 1, and the global truth table has 16 rows, wherein the input variables are four qubit states, denoted as q0, q1, q2, q3, each row can represent a possible combination of qubit states, and each column can represent a measurement result of a qubit state. q4 represents the output result of the 4-qubit balanced Boolean function.

[0081] Based on the global truth table shown in Table 1, each row in Table 1 is mapped at a plurality of vertices included in a preset cubic configuration in Euclidean space to determine the mapping positions of a plurality of minimum terms included in a minimum term set in the Euclidean space. Among them, the minimum term set is {0000, 0011, 0101, 0110, 0111, 1001, 1010, 1100}, and the minimum term set is described in decimal as {0, 3, 5, 6, 7, 9, 10, 12}.

[0082] Table 1

[0083]

[0084] As Figure 2 shown, each black vertex represents a minimum term, and the output value corresponding to the coordinates of each black vertex is 1. Each white vertex represents a remaining term in the global truth table, and the output value corresponding to the coordinates of each white vertex is 0.

[0085] For convenience of description, the coordinates are described in decimal in an embodiment of the present disclosure. In the circuit of this embodiment, one Toffoli gate can represent four minimum terms, and one 3-MCT gate can represent two special minimum terms. The same minimum term is covered twice and is equal to not being selected.

[0086] Based on the mapping position of each minterm included in the minterm set in the Euclidean space, four candidate minterms {0, 3, 9, 10} are randomly selected, since the four candidate minterms do not satisfy the parallelogram condition, a Toffoli gate and two CNOT gates can be used to construct the minterms {0, 3, 8, 11} that satisfy the parallelogram condition, and then a Toffoli gate is used to construct the minterms {8, 9, 10, 11} that satisfy the parallelogram condition. Since {8, 11} is covered twice, the same minterm is covered twice and is equal to not being selected, and finally two CNOT gates and two Toffoli gates are used to construct the first target sub-circuit for realizing the logical function of the minterms {0, 3, 9, 10}.

[0087] {0, 3, 9, 10} is removed from the minterm set, and the updated minterm set is {5, 6, 7, 12}, since the four remaining minterms do not satisfy the parallelogram condition, a 3-MCT gate can be used to represent {4, 12}, and the minterm 1100 of 12 in decimal is mapped to the mapping point of the remaining item 0100 of 4 in decimal, which can convert the four remaining minterms into target minterms that satisfy the parallelogram condition. At this time, the updated minterm set becomes {4, 5, 6, 7}, and a Toffoli gate can be used to construct the set. Therefore, a 3-MCT gate and two Toffoli gates are finally used to construct the second target sub-circuit for realizing the logical function of the minterms {0, 3, 9, 10}. The first target sub-circuit and the second target sub-circuit are synthesized, and the target quantum circuit as shown in FIG. 4 can be obtained. Figure 3

[0088] Figure 4 A schematic diagram of a global truth table based on geometric representation according to an embodiment of the present disclosure is schematically shown.

[0089] Figure 5 A schematic diagram of a target quantum circuit according to another embodiment of the present disclosure is schematically shown.

[0090] According to another embodiment of the present disclosure, the global truth table based on a 4-qubit balanced Boolean function is shown in Table 2.

[0091] ​Based on the global truth table shown in Table 2, mapping each row in Table 2 at a plurality of vertices included in a preset cubic configuration in the Euclidean space respectively to determine a plurality of minterms included in the minimum term set at the mapping positions in the Euclidean space. Wherein the minimum term set is {0010, 0101, 0110, 0111, 1000, 1001, 1011, 1100}, and the minimum term set is described in decimal as {2, 5, 6, 7, 8, 9, 11, 12}.

[0092] Table 2

[0093]

[0094] As Figure 4 shown, based on the mapping positions of each minterm included in the minimum term set in the Euclidean space, four candidate minterms {2, 6, 8, 12} are randomly selected therefrom, and a first target sub-circuit for implementing the logic function of the minterms {2, 6, 8, 12} can be constructed by using one Toffoli gate and two CNOT gates.

[0095] Removing {2, 6, 8, 12} from the minimum term set, the updated minimum term set is {5, 7, 9, 11}, and a second target sub-circuit for implementing the logic function of the minterms {5, 7, 9, 11} can be constructed by using one Toffoli gate and two CNOT gates. Integrating the first target sub-circuit and the second target sub-circuit, a target quantum circuit as Figure 5 shown can be obtained.

[0096] According to another specific embodiment of the present disclosure, Table 3 shows the optimization effect of the quantum circuit generation method based on the balanced Boolean function. The number of quantum gates and the circuit depth in the quantum circuit including all 4 quantum bit balanced Boolean functions.

[0097] Table 3

[0098]

[0099] As shown in Table 3, by comparing with the current mainstream ESOP method which is not applicable to auxiliary bits, the quantum circuit generation method based on the balanced Boolean function proposed in the embodiment of the present disclosure reduces the number of CNOT gates by 55.6%, the number of single-bit gates by 61.3%, the number of double-bit gates by 56.0%, and the circuit depth by 61.3%. By converting the global truth table of any one 4 quantum bit balanced Boolean function into a target quantum circuit, at most only one Toffoli gate is needed, and the optimal quantum circuit generation method can be achieved without using auxiliary bits, saving quantum bit resources, and achieving better running results in the current quantum device.

[0100] Figure 6 A block diagram of a quantum circuit generation apparatus based on a balanced Boolean function according to an embodiment of the present disclosure is shown schematically.

[0101] As shown in Figure 6 , the quantum circuit generation apparatus based on the balanced Boolean function includes an extraction module 610, a determination module 620, and a mapping module 630.

[0102] The extraction module 610 is configured to extract a set of minterms from a global truth table of the balanced Boolean function.

[0103] The determination module 620 is configured to determine at least one target set of minterms based on mapping positions of the plurality of minterms in the Euclidean space.

[0104] The mapping module 630 is configured to map the at least one target set of minterms on a quantum circuit using double-controlled NOT gates to generate a target quantum circuit.

[0105] According to an embodiment of the present disclosure, the determination module 620 includes a first determination submodule, a first adjustment submodule, and a second determination submodule.

[0106] The first determination submodule is configured to determine at least one candidate set of minterms from the set of minterms.

[0107] The first adjustment submodule is configured to adjust quantum bit states included in the at least one candidate set of minterms using single-controlled NOT gates and / or triple-controlled NOT gates until mapping positions of four candidate minterms included in the candidate set of minterms in the Euclidean space satisfy a parallelogram condition, in a case where the mapping positions of the four candidate minterms in the Euclidean space do not satisfy the parallelogram condition.

[0108] The second determination submodule is configured to determine the candidate set of minterms satisfying the parallelogram condition as the target set of minterms.

[0109] According to an embodiment of the present disclosure, the first adjustment submodule includes a first adjustment unit and a first update unit.

[0110] The first adjustment unit is configured to adjust quantum bit states included in the at least one candidate minterm using single-controlled NOT gates and / or triple-controlled NOT gates to obtain adjusted quantum bit states of the at least one candidate minterm.

[0111] The first update unit is configured to update mapping positions of the at least one candidate minterm in the Euclidean space based on the adjusted quantum bit states of the at least one candidate minterm until mapping positions of four candidate minterms included in the candidate set of minterms in the Euclidean space satisfy a parallelogram condition.

[0112] According to an embodiment of the present disclosure, the mapping module 630 comprises a first mapping submodule, a first updating submodule, a second mapping submodule, and a third determining submodule.

[0113] The first mapping submodule is configured to map the at least one target minterm set on the quantum circuit by using the Toffoli gate to generate a first target subcircuit.

[0114] The first updating submodule is configured to update the minterm set based on the four target minterms included in the at least one target minterm set to obtain an updated minterm set.

[0115] The second mapping submodule is configured to map the updated minterm set on the quantum circuit by using the Toffoli gate to generate a second target subcircuit.

[0116] The third determining submodule is configured to obtain the target quantum circuit based on the first target subcircuit and the second target subcircuit.

[0117] According to an embodiment of the present disclosure, the second mapping submodule comprises

[0118] The second adjusting unit is configured to adjust the quantum bit state included in the at least one remaining minterm by using the Toffoli gate and / or the Toffoli gate until the mapping positions of the four remaining minterms in the Euclidean space satisfy the parallelogram condition.

[0119] The first determining unit is configured to determine the four remaining minterms satisfying the parallelogram condition as a target remaining minterm set.

[0120] The first mapping unit is configured to map the target remaining minterm set on the quantum circuit by using the Toffoli gate to generate a second target subcircuit.

[0121] According to an embodiment of the present disclosure, the quantum circuit generation apparatus based on the balanced Boolean function further comprises a mapping position determining module.

[0122] The mapping position determining module is configured to map the combination of the plurality of quantum bit states included in the global truth table at the plurality of vertices included in the preset cubic configuration in the Euclidean space according to the initial mapping relationship to determine the mapping positions of the plurality of minterms included in the minterm set in the Euclidean space.

[0123] According to an embodiment of the present disclosure, the quantum circuit generation apparatus based on the balanced Boolean function further comprises a packaging module.

[0124] The encapsulation module is configured to encapsulate a plurality of quantum gates included in a target quantum circuit to obtain an encapsulation module of the target quantum circuit.

[0125] Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure, or at least part of functions of any one or more of the modules, sub-modules, units, sub-units, can be implemented in one module. Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure can be split into a plurality of modules for implementation. Any one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure can be implemented at least in part as a hardware circuit, for example, a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable manner of hardware or firmware by integrating or packaging the circuit, or in any one of software, hardware and firmware or in a proper combination of any one or more of them. Alternatively, one or more of the modules, sub-modules, units, sub-units according to embodiments of the present disclosure can be implemented at least in part as computer program modules, which can perform corresponding functions when the computer program modules are run.

[0126] For example, any one or more of the extraction module 610, the determination module 620, the mapping module 630 can be combined in one module / unit / sub-unit for implementation, or any one of the modules / units / sub-units can be split into a plurality of modules / units / sub-units. Alternatively, at least part of the functions of one or more of the modules / units / sub-units can be combined with at least part of the functions of other modules / units / sub-units and implemented in one module / unit / sub-unit. According to embodiments of the present disclosure, at least one of the extraction module 610, the determination module 620, the mapping module 630 can be implemented at least in part as a hardware circuit, for example, a field programmable gate array (FPGA), a programmable logic array (PLA), a system on chip, a system on substrate, a system on package, an application specific integrated circuit (ASIC), or any other reasonable manner of hardware or firmware by integrating or packaging the circuit, or in any one of software, hardware and firmware or in a proper combination of any one or more of them. Alternatively, at least one of the extraction module 610, the determination module 620, the mapping module 630 can be implemented at least in part as computer program modules, which can perform corresponding functions when the computer program modules are run.

[0127] It should be noted that the quantum circuit generation device based on balanced Boolean function in the embodiments of this disclosure corresponds to the quantum circuit generation method based on balanced Boolean function in the embodiments of this disclosure. For a detailed description of the quantum circuit generation device based on balanced Boolean function, please refer to the quantum circuit generation method based on balanced Boolean function, which will not be repeated here.

[0128] Figure 7 A block diagram of an electronic device suitable for implementing a quantum circuit generation method based on balanced Boolean functions, according to an embodiment of the present disclosure, is shown schematically. Figure 7 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0129] like Figure 7 As shown, an electronic device according to an embodiment of the present disclosure includes a processor 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory ROM 702 or a program loaded from a storage portion 708 into a random access memory RAM 703. The processor 701 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 701 may also include onboard memory for caching purposes. The processor 701 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0130] RAM 703 stores various programs and data required for the operation of the electronic device. Processor 701, ROM 702, and RAM 703 are interconnected via bus 704. Processor 701 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 702 and / or RAM 703. It should be noted that the programs may also be stored in one or more memories other than ROM 702 and RAM 703. Processor 701 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0131] According to an embodiment of the present disclosure, the electronic device can further include an input / output (I / O) interface 705 also connected to the bus 704. The electronic device can further include one or more of the following components connected to the input / output (I / O) interface 705: an input part 706 including a keyboard, a mouse, etc.; an output part 707 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage part 708 including a hard disk, etc.; and a communication part 709 including a network interface card such as a LAN card, a modem, etc. The communication part 709 performs communication processing via a network such as the Internet. A driver 710 is also connected to the input / output (I / O) interface 705 as necessary. A removable medium 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the driver 710 as necessary, so that a computer program read therefrom is installed in the storage part 708 as necessary.

[0132] According to an embodiment of the present disclosure, the method flow according to the embodiment of the present disclosure can be implemented as a computer software program. For example, the embodiment of the present disclosure includes a computer program product including a computer program carried on a computer-readable storage medium, the computer program containing program codes for executing the method shown in the flow chart. In such an embodiment, the computer program can be downloaded and installed from the network by the communication part 709, and / or installed from the removable medium 711. When the computer program is executed by the processor 701, the above-described functions defined in the system implementing the embodiment of the present disclosure are performed. According to an embodiment of the present disclosure, the system, device, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0133] The present disclosure also provides a computer-readable storage medium, which can be included in the device / apparatus / system described in the above embodiments; or can exist separately without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, when the one or more programs are executed, the method according to the embodiment of the present disclosure is implemented.

[0134] According to an embodiment of the present disclosure, the computer readable storage medium can be a non-volatile computer readable storage medium. For example, it can include, but is not limited to, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, a computer readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in connection with an instruction execution system, apparatus, or device.

[0135] For example, according to an embodiment of the present disclosure, the computer readable storage medium can include one or more memories other than the ROM 702 and / or the RAM 703 and / or the ROM 702 and the RAM 703 described above.

[0136] Embodiments of the present disclosure also include a computer program product, which includes a computer program containing program codes for executing the method provided by the embodiments of the present disclosure, and when the computer program product is run on an electronic device, the program codes are used to make the electronic device implement the method for generating a quantum circuit based on a balanced Boolean function provided by the embodiments of the present disclosure.

[0137] When the computer program is executed by the processor 701, the above-mentioned functions defined in the system / apparatus of the embodiments of the present disclosure are performed. According to an embodiment of the present disclosure, the system, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0138] In one embodiment, the computer program can rely on a tangible storage medium such as an optical storage device, a magnetic storage device, etc. In another embodiment, the computer program can also be transmitted, distributed, and downloaded in the form of a signal on a network medium, and be downloaded and installed through the communication part 709, and / or be installed from the detachable medium 711. The program codes contained in the computer program can be transmitted by any appropriate network medium, including but not limited to wireless, wired, etc., or any suitable combination of the foregoing.

[0139] According to embodiments of the present disclosure, program code of the computer program for performing the methods provided by the embodiments of the present disclosure can be written in any combination of one or more programming languages, including a high-level procedural and / or object-oriented programming language, and / or an assembly / machine language. Programming languages include, but are not limited to, Java, C++, python, "C" language, or the like. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on a remote computing device, or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, such as through the Internet using an Internet Service Provider.

[0140] The computer program product of the present disclosure can be a computer program product, which is a machine-readable medium (media) having exact sequences of instructions, program, code segments, routines, subroutines, programs, functions, objects, processing options / script modules, or any combination of the above, which, when executed by a processor in a computing device, cause the processor to carry out the steps of the methods described herein. The machine-readable medium can be a transitory or non-transitory computer-readable medium. The machine-readable medium can be a tangible computer-readable medium. The machine-readable medium can be a non-transitory computer-readable medium. The machine-readable medium can be a computer-readable storage medium. The machine-readable medium can be a non-transitory computer-readable storage medium. The machine-readable medium can be a computer-readable non-transitory storage medium. The machine-readable medium can be a computer-readable tangible storage medium. The machine-readable medium can be a computer-readable non-transitory tangible storage medium. The machine-readable medium can be a computer-readable non-transitory storage medium that is not a signal. The machine-readable medium can be a computer-readable non-transitory storage medium that is tangible.

[0141] The above-described embodiments of the present disclosure are merely descriptive and are not intended to limit or restrict the scope of the present disclosure. Although the above-described embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A method for generating a quantum circuit based on a balanced Boolean function, comprising: extracting a set of minterms from a global truth table of the balanced Boolean function, wherein the set of minterms comprises a plurality of minterms, and each minterm is a combination of quantum bit states with a calculated value of 1 in the global truth table; determining at least one target set of minterms based on mapped positions of the plurality of minterms in a Euclidean space, wherein the target set of minterms comprises four minterms in the set of minterms that satisfy a parallelogram condition, and the parallelogram condition comprises that the four minterms form a parallelogram in the Euclidean space; and mapping the at least one target set of minterms on the quantum circuit by using double-controlled NOT gates to generate a target quantum circuit.

2. The method of claim 1, wherein, The determining at least one target set of minterms based on mapped positions of the plurality of minterms in a Euclidean space comprises: determining at least one candidate set of minterms from the set of minterms; in a case that mapped positions of four candidate minterms included in the candidate set of minterms in the Euclidean space do not satisfy the parallelogram condition, adjusting quantum bit states included in the at least one candidate set of minterms by using single-controlled NOT gates and / or triple-controlled NOT gates until mapped positions of four candidate minterms included in the candidate set of minterms in the Euclidean space satisfy the parallelogram condition; and determining the candidate set of minterms that satisfy the parallelogram condition as the target set of minterms.

3. The method of claim 2, wherein, The adjusting quantum bit states included in the at least one candidate set of minterms by using single-controlled NOT gates and / or triple-controlled NOT gates until mapped positions of four candidate minterms included in the candidate set of minterms in the Euclidean space satisfy the parallelogram condition comprises: adjusting quantum bit states included in the at least one candidate set of minterms by using the single-controlled NOT gates and / or the triple-controlled NOT gates to obtain adjusted quantum bit states of the at least one candidate set of minterms; and updating mapped positions of the at least one candidate set of minterms in the Euclidean space based on the adjusted quantum bit states of the at least one candidate set of minterms until mapped positions of four candidate minterms included in the candidate set of minterms in the Euclidean space satisfy the parallelogram condition.

4. The method of claim 2, wherein, The mapping the at least one target set of minterms on the quantum circuit by using double-controlled NOT gates to generate a target quantum circuit comprises: mapping the at least one target set of minterms on the quantum circuit by using double-controlled NOT gates to generate a first target sub-circuit; updating the set of minterms based on four target minterms included in the at least one target set of minterms to obtain an updated set of minterms, wherein the updated set of minterms comprises remaining minterms other than the four target minterms; mapping the updated set of minterms on the quantum circuit by using the double-controlled NOT gates to generate a second target sub-circuit; and obtaining the target quantum circuit based on the first target sub-circuit and the second target sub-circuit.

5. The method of claim 4, wherein, mapping the updated set of minterms on the quantum circuit using the two-control NOT gate to generate a second target subcircuit includes: in a case where mapping positions of four remaining minterms included in the updated set of minterms in the Euclidean space do not satisfy the parallelogram condition, adjusting quantum bit states included in the at least one remaining minterm using the one-control NOT gate and / or the three-control NOT gate until mapping positions of the four remaining minterms in the Euclidean space satisfy the parallelogram condition; determining the four remaining minterms satisfying the parallelogram condition as a target set of remaining minterms; and mapping the target set of remaining minterms on the quantum circuit using the two-control NOT gate to generate a second target subcircuit.

6. The method of claim 2, wherein, The method further includes: mapping combinations of quantum bit states included in the global truth table at a plurality of vertices included in a preset cubic configuration in the Euclidean space according to an initial mapping relationship to determine mapping positions of a plurality of minterms included in the set of minterms in the Euclidean space.

7. The method of claim 1, wherein, The method further includes: packaging a plurality of quantum gates included in the target quantum circuit to obtain a packaging module of the target quantum circuit, wherein the packaging module is configured to provide an input / output interface of a Cirq library.

8. A quantum circuit generation apparatus based on a balanced Boolean function, comprising: an extraction module configured to extract a set of minterms from a global truth table of the balanced Boolean function, wherein the set of minterms includes a plurality of minterms, and each minterm is a combination of quantum bit states with a calculated value of 1 in the global truth table; a determination module configured to determine at least one target set of minterms based on mapping positions of the plurality of minterms in a Euclidean space, wherein the target set of minterms includes four minterms in the set of minterms satisfying a parallelogram condition, and the parallelogram condition includes that the four minterms form a parallelogram in the Euclidean space; a mapping module configured to map the at least one target set of minterms on the quantum circuit using a two-control NOT gate to generate a target quantum circuit.

9. An electronic device, comprising: one or more processors; a memory configured to store one or more programs, wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1-7.

10. A computer-readable storage medium having stored thereon executable instructions that, when executed by a processor, cause the processor to perform the method of any one of claims 1-7.

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