Method and system for testing gate oxide failure of silicon carbide device under test

Abstract

The present application provides a method and system for testing the gate oxide failure of a silicon carbide device to be tested. The method determines the limit gate voltage, reference gate leakage current and target ramp voltage of the target silicon carbide device to be tested according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, so as to accurately obtain the required parameters for judging whether the gate oxide of the silicon carbide device to be tested has failed. Finally, the reference gate leakage current and the target ramp voltage are used to test the non-target silicon carbide device to be tested to determine whether the gate oxide of the non-target silicon carbide device to be tested has failed. By judging the decrease in threshold voltage and the increase in gate leakage current, devices with gate oxide defects are screened out, thereby solving the problem that the existing scheme lacks a scheme for efficiently and quickly screening the gate oxide failure of silicon carbide devices.

Description

Technical Field

[0001] The present application relates to the technical field of silicon carbide devices, and in particular to a method for testing gate oxide failure of a silicon carbide device to be tested, a silicon carbide device to be tested, a system and an electronic device. Background Art

[0002] After the silicon carbide device passes the conventional electrical parameter test, it will suddenly fail in actual work, mainly manifested as gate breakdown, which is related to gate oxide defects. Gate oxide defects are divided into intrinsic defects and extrinsic defects. The intrinsic defect is that the silicon carbide MOSFET has a high interface state density at the SiC / SiO2 interface due to lattice mismatch, C dangling bonds, oxygen vacancies, etc. The high-density interface state affects the performance of the device and the reliability of the gate oxide layer. Extrinsic defects are caused by epitaxial or substrate defects, metal impurities, particles, or other foreign impurities doped into the gate oxide layer, which produce microscopic flaws or defects at the SiC / SiO2 interface or inside SiO2, causing local oxide layer thinning. Before the silicon carbide MOSFET device leaves the factory or is used, gate oxide screening is performed to eliminate defective devices, which can improve the reliability of silicon carbide devices and reduce early failure rate. In existing research work, there are two methods for screening the gate oxide layer of silicon carbide devices: one is the electrical terminal test, which usually applies a gate voltage stress pulse of a predetermined amplitude and time to each device to observe the change in gate leakage current. There is no standard for the pulse amplitude and time of this method. When the gate voltage is large, the gate oxide layer defects capture or release electrons under the pulse stress, resulting in a drift of the threshold voltage. When the gate voltage is small, for devices with fewer defects, the gate leakage current is small, and the purpose of screening cannot be achieved; the other is the high-temperature gate bias test, in which the device is subjected to a lower gate voltage for a longer time at high temperature. This method may cause the threshold voltage and on-resistance to drift seriously because the gate is subjected to bias and high temperature stress for a long time, affecting the device life. Therefore, how to efficiently and quickly screen the gate oxide layer of silicon carbide devices has become a key technical problem that needs to be solved urgently.

[0003] That is, the existing solutions lack an efficient and rapid solution for screening gate oxide failures of silicon carbide devices. Summary of the invention

[0004] The main purpose of the present application is to provide a test method for gate oxide failure of a silicon carbide device to be tested, a silicon carbide device to be tested, a system and an electronic device, so as to at least solve the problem that the existing solutions lack a solution for efficiently and quickly screening gate oxide failure of silicon carbide devices.

[0005] In order to achieve the above object, according to one aspect of the present application, a method for testing gate oxide failure of a silicon carbide device to be tested is provided, the method comprising:

[0006] Based on the continuously increasing ramp voltage, the ramp voltage is applied to the gate of the target silicon carbide device to be tested, a plurality of test gate leakage currents and a plurality of test threshold voltages are obtained, and a gate leakage current mapping relationship and a threshold voltage mapping relationship are generated, wherein the gate leakage current mapping relationship represents the relationship between the ramp voltage and the test gate leakage current, and the threshold voltage mapping relationship represents the relationship between the ramp voltage and the test threshold voltage;

[0007] Determining, according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, a limit gate voltage, a reference gate leakage current and a target ramp voltage of the target silicon carbide device to be tested, wherein the limit gate voltage is one of all the ramp voltages applied, the reference gate leakage current is the test gate leakage current corresponding to the limit gate voltage, and the target ramp voltage is the ramp voltage corresponding to the limit gate voltage;

[0008] The reference gate leakage current and the target ramp voltage are used to test a non-target silicon carbide device to be tested to determine whether a gate oxide layer of the non-target silicon carbide device to be tested fails.

[0009] Optionally, obtaining a gate leakage current mapping relationship and a threshold voltage mapping relationship includes:

[0010] Based on continuously increasing the ramp voltage, applying the ramp voltage to the gate of the target silicon carbide device to be tested to obtain a plurality of test gate leakage currents and a plurality of test threshold voltages;

[0011] The gate leakage current mapping relationship and the threshold voltage mapping relationship are generated based on all the applied ramp voltages, all the tested gate leakage currents, and all the tested threshold voltages.

[0012] Optionally, using the reference gate leakage current and the target ramp voltage to test a non-target silicon carbide device to be tested to determine whether a gate oxide layer of the non-target silicon carbide device to be tested fails includes:

[0013] Acquiring an initial threshold voltage of the non-target silicon carbide device to be tested, wherein the initial threshold voltage of the non-target silicon carbide device to be tested is a turn-on voltage threshold of the non-target silicon carbide device to be tested in an initial state;

[0014] Applying the target ramp voltage to the gate of the non-target silicon carbide device to be tested to obtain a detection gate leakage current and a detection threshold voltage;

[0015] When the detection threshold voltage is less than the initial threshold voltage of the non-target silicon carbide device to be tested, and / or the detection gate leakage current is greater than the reference gate leakage current, determining that the gate oxide layer of the non-target silicon carbide device to be tested has failed;

[0016] When the detection threshold voltage is greater than or equal to the initial threshold voltage of the non-target silicon carbide device to be tested, and the detection gate leakage current is less than or equal to the reference gate leakage current, it is determined that the gate oxide layer of the non-target silicon carbide device to be tested is valid.

[0017] Optionally, based on continuously increasing the ramp voltage, applying the ramp voltage to the gate of the target silicon carbide device to be tested to obtain a plurality of test gate leakage currents and a plurality of test threshold voltages, including:

[0018] The ramp voltage is continuously increased with a preset step length as a reference, and the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain a plurality of the test gate leakage currents and a plurality of the test threshold voltages.

[0019] Optionally, in the process of applying the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage to obtain multiple test gate leakage currents and multiple test threshold voltages, the method further includes:

[0020] Acquiring an initial threshold voltage of a target silicon carbide device to be tested, wherein the initial threshold voltage of the target silicon carbide device to be tested is a turn-on voltage threshold of the target silicon carbide device to be tested in an initial state;

[0021] Applying the ramp voltage to the gate of the target silicon carbide device to be tested for the first time to obtain a test threshold voltage;

[0022] According to the initial threshold voltage and the test threshold voltage of the target silicon carbide device to be tested, it is determined that the gate oxide layer of the target silicon carbide device to be tested has failed, or the ramp voltage is continuously increased as a reference and the ramp voltage is applied to the gate of the target silicon carbide device to be tested.

[0023] Optionally, determining that a gate oxide layer of the target silicon carbide device to be tested has failed according to the initial threshold voltage and the test threshold voltage of the target silicon carbide device to be tested, or continuing to apply the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage, comprises:

[0024] When the test threshold voltage is less than the initial threshold voltage of the target silicon carbide device to be tested, determining that a gate oxide layer of the target silicon carbide device to be tested is failed;

[0025] When the test threshold voltage is greater than or equal to the initial threshold voltage of the target silicon carbide device to be tested, the ramp voltage is continuously applied to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage.

[0026] Optionally, in the process of applying the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage to obtain multiple test gate leakage currents and multiple test threshold voltages, the method also includes: when the current ramp voltage is greater than or equal to the maximum value of the target ramp voltage, determining that the current ramp voltage is the last time the ramp voltage was applied to the gate of the target silicon carbide device to be tested.

[0027] Optionally, the method further includes: determining the target ramp voltage maximum value to be a preset ramp voltage maximum value corresponding to a specification of the target silicon carbide device to be tested.

[0028] Optionally, the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on a continuously increasing ramp voltage to obtain a plurality of test gate leakage currents, including: short-circuiting the drain and source of the target silicon carbide device to be tested, and applying the ramp voltage to the gate of the target silicon carbide device to be tested based on a continuously increasing ramp voltage to obtain a plurality of test gate leakage currents;

[0029] Based on the continuously increasing ramp voltage, the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain multiple test threshold voltages, including: based on the continuously increasing ramp voltage, after applying the ramp voltage to the gate of the target silicon carbide device to be tested, the gate and the drain of the target silicon carbide device to be tested are short-circuited to obtain the multiple test threshold voltages.

[0030] Optionally, a test system for gate oxide failure of a silicon carbide device to be tested comprises a first switching device, a second switching device, a voltage application module and a current application module, wherein a first selection end of the first switching device is used to be electrically connected to the voltage application module, a second selection end of the first switching device is used to be electrically connected to the current application module, a fixed end of the first switching device is used to be electrically connected to the first selection end of the second switching device and the gate of the target silicon carbide device to be tested, respectively, a second selection end of the second switching device is used to be grounded, and a fixed end of the second switching device is electrically connected to the drain of the target silicon carbide device to be tested;

[0031] Based on the continuously increasing ramp voltage, after applying the ramp voltage to the gate of the target silicon carbide device to be tested, the gate and the drain of the target silicon carbide device to be tested are short-circuited to obtain a plurality of the test threshold voltages, including: electrically connecting the first selection end of the first switching device to the voltage application module, and grounding the second selection end of the second switching device, so that the drain and the source of the target silicon carbide device to be tested are short-circuited to obtain a plurality of the test gate leakage currents;

[0032] The gate and drain of the target silicon carbide device to be tested are short-circuited, and the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on a continuously increasing ramp voltage to obtain a plurality of test threshold voltages, including: electrically connecting the second selection end of the first switching device to the current application module respectively, and electrically connecting the fixed end of the first switching device and the first selection end of the second switching device to short-circuit the gate and drain of the target silicon carbide device to be tested to obtain a plurality of test threshold voltages.

[0033] According to another aspect of the present application, a silicon carbide device to be tested is provided, wherein the silicon carbide device to be tested is tested by using any one of the gate oxide layer failure testing methods for the silicon carbide device to be tested.

[0034] According to another aspect of the present application, a test system for gate oxide failure of a silicon carbide device to be tested is provided, the system comprising: a first switching device, a second switching device, a voltage application module, a current application module and a silicon carbide device to be tested, wherein the first selection end of the first switching device is used to be electrically connected to the voltage application module, the second selection end of the first switching device is used to be electrically connected to the current application module, the fixed end of the first switching device is used to be electrically connected to the first selection end of the second switching device and the gate of the target silicon carbide device to be tested, respectively, the second selection end of the second switching device is used to be grounded, and the fixed end of the second switching device is electrically connected to the drain of the target silicon carbide device to be tested, wherein the silicon carbide device to be tested is tested using any one of the test methods for gate oxide failure of the silicon carbide device to be tested.

[0035] Optionally, the voltage application module includes: a voltage source meter and a first voltage meter, the first end of the voltage source meter and the first end of the first voltage meter are respectively used to electrically connect to the first selection end of the first switching device, and the second end of the voltage source meter and the second end of the first voltage meter are respectively grounded.

[0036] Optionally, the current application module includes: a current source meter and a second voltmeter, the first end of the current source meter and the first end of the second voltmeter are respectively used to be electrically connected to the second selection end of the first switching device, and the second end of the current source meter and the second end of the second voltmeter are respectively grounded.

[0037] Optionally, the gate oxide layer failure test system of the silicon carbide device to be tested further includes an ammeter, which is used to be electrically connected between the first selection end of the first switching device and the voltage application module.

[0038] According to another aspect of the present application, an electronic device is provided, and the electronic device includes any one of the gate oxide layer failure testing systems for the silicon carbide device to be tested.

[0039] By applying the technical solution of the present application, the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on a continuously increasing ramp voltage, so as to obtain multiple test gate leakage currents and multiple test threshold voltages, and the limit gate voltage, the reference gate leakage current and the target ramp voltage of the target silicon carbide device to be tested are determined according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, so as to accurately obtain the required parameters for judging whether the gate oxide layer of the silicon carbide device to be tested is failed, and finally the reference gate leakage current and the target ramp voltage are used to test the non-target silicon carbide device to be tested to determine whether the gate oxide layer of the non-target silicon carbide device to be tested is failed. For devices with defective gate oxide layers, when a voltage is applied to the gate, the electric field in the oxide layer is locally enhanced, so that hole capture is dominant, and the FN tunneling current is enhanced, thereby causing changes in the threshold voltage and the gate leakage current. Devices with gate oxide layer defects are screened out by judging that the threshold voltage is reduced and the gate leakage current is increased, thereby solving the problem that the existing scheme lacks a scheme for efficiently and quickly screening the gate oxide layer failure of silicon carbide devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings constituting part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0041] Figure 1 A schematic flow chart of a method for testing gate oxide failure of a silicon carbide device to be tested provided in accordance with an embodiment of the present application is shown;

[0042] Figure 2 A schematic diagram of a voltage test process mapping relationship provided according to an embodiment of the present application is shown;

[0043] Figure 3 A schematic diagram showing a mapping relationship of threshold voltages under different gate voltages provided according to an embodiment of the present application is shown;

[0044] Figure 4 A schematic diagram of a test system for gate oxide layer failure of a silicon carbide device to be tested provided in accordance with an embodiment of the present application is shown. DETAILED DESCRIPTION

[0045] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0046] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0049] FN tunneling current refers to Fermi-Dirac tunneling current, which is a phenomenon of transferring charge between two conductors through the tunneling effect. When there is a potential difference between the two conductors, electrons can cross the potential barrier through the tunneling effect to form a current between the two conductors. This current is usually manifested in nanoscale devices and can be used to realize high-speed, low-power electronic devices. FN tunneling current has important application value in semiconductor devices, quantum dot devices and other fields.

[0050] As introduced in the background technology, after the silicon carbide device passes the conventional electrical parameter test, it will suddenly fail in actual work, which is mainly manifested as gate breakdown, which is related to the gate oxide layer defects. Gate oxide layer defects are divided into intrinsic defects and extrinsic defects. The intrinsic defect is that the silicon carbide MOSFET produces a higher interface state density at the SiC / SiO2 interface due to lattice mismatch, C hanging bonds, oxygen vacancies, etc. The high-density interface state affects the performance of the device and the reliability of the gate oxide layer. Extrinsic defects are caused by epitaxy or substrate defects, metal impurities, particles, or other foreign impurities incorporated into the gate oxide layer, which produce microscopic flaws or defects at the SiC / SiO2 interface or inside SiO2, causing local oxide layer thinning. Before the silicon carbide MOSFET device leaves the factory or is used, the gate oxide layer is screened to remove defective devices, which can improve the reliability of the silicon carbide device and reduce the early failure rate. In existing research work, there are two methods for screening the gate oxide layer of silicon carbide devices: one is an electrical terminal test, which usually applies a gate voltage stress pulse of a predetermined amplitude and time to each device to observe the change in gate leakage current. There is no standard for the pulse amplitude and time of this method. When the gate voltage is large, the gate oxide layer defects capture or release electrons under the pulse stress, resulting in a drift of the threshold voltage. When the gate voltage is small, for devices with fewer defects, the gate leakage current is small, and the screening purpose cannot be achieved; the other is a high-temperature gate bias test, in which the device is subjected to a lower gate voltage for a longer time at high temperature. This method may cause the threshold voltage and on-resistance to drift seriously because the gate is subjected to bias and high-temperature stress for a long time, affecting the life of the device. In order to solve the problem that the existing scheme lacks a scheme for efficiently and quickly screening the gate oxide layer failure of silicon carbide devices, the embodiments of the present application provide a test method for gate oxide layer failure of a silicon carbide device to be tested, a silicon carbide device to be tested, a system and an electronic device.

[0051] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0052] Figure 1 FIG. 1 is a flow chart of a method for testing gate oxide failure of a silicon carbide device to be tested according to an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0053] Step S101, obtaining a gate leakage current mapping relationship and a threshold voltage mapping relationship, wherein the gate leakage current mapping relationship represents a relationship between a ramp voltage and a test gate leakage current, and the threshold voltage mapping relationship represents a relationship between a ramp voltage and a test threshold voltage;

[0054] The gate leakage current mapping relationship and the threshold voltage mapping relationship can both be displayed in the form of curves.

[0055] Based on the continuously increasing ramp voltage, the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain multiple test gate leakage currents and multiple test threshold voltages, and a gate leakage current mapping relationship and a threshold voltage mapping relationship are generated, wherein the gate leakage current mapping relationship represents the relationship between the ramp voltage and the test gate leakage current, and the threshold voltage mapping relationship represents the relationship between the ramp voltage and the test threshold voltage;

[0056] In one embodiment of the present application, obtaining a gate leakage current mapping relationship and a threshold voltage mapping relationship includes:

[0057] Based on the continuously increasing ramp voltage, the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain a plurality of test gate leakage currents and a plurality of test threshold voltages;

[0058] The gate leakage current mapping relationship and the threshold voltage mapping relationship are generated based on all the applied ramp voltages, all the tested gate leakage currents and all the tested threshold voltages.

[0059] The type of applied ramp voltage is a gradient ramp.

[0060] In one embodiment of the present application, the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, and multiple test gate leakage currents and multiple test threshold voltages are obtained, including:

[0061] The ramp voltage is continuously increased with a preset step length as a reference, and the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain the multiple test gate leakage currents and the multiple test threshold voltages.

[0062] Specifically, the preset step size may be 1V, and by continuously increasing the ramp voltage based on the preset step size, the gate leakage current mapping relationship and the threshold voltage mapping relationship obtained subsequently can more accurately show the changes in current and voltage.

[0063] In one embodiment of the present application, in the process of applying the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage to obtain multiple test gate leakage currents and multiple test threshold voltages, the method further includes:

[0064] Obtaining an initial threshold voltage of a target silicon carbide device to be tested, wherein the initial threshold voltage of the target silicon carbide device to be tested is a turn-on voltage threshold of the target silicon carbide device to be tested in an initial state;

[0065] Applying the ramp voltage to the gate of the target silicon carbide device to be tested for the first time to obtain a test threshold voltage;

[0066] According to the initial threshold voltage and the test threshold voltage of the target silicon carbide device to be tested, it is determined that the gate oxide layer of the target silicon carbide device to be tested has failed, or the ramp voltage is continuously increased to apply the ramp voltage to the gate of the target silicon carbide device to be tested.

[0067] Specifically, after the ramp voltage is applied for the first time, the initial threshold voltage and the test threshold voltage are compared. If the threshold voltage drops, it means that the oxide layer has failed. If the threshold voltage remains unchanged or increases, the ramp voltage should continue to be applied to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage.

[0068] In one embodiment of the present application, according to the initial threshold voltage and the test threshold voltage of the target silicon carbide device to be tested, determining that the gate oxide layer of the target silicon carbide device to be tested has failed, or continuing to apply the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage, including:

[0069] In a case where the test threshold voltage is less than the initial threshold voltage of the target silicon carbide device to be tested, determining that the gate oxide layer of the target silicon carbide device to be tested is failed;

[0070] When the test threshold voltage is greater than or equal to the initial threshold voltage of the target silicon carbide device to be tested, the ramp voltage is continuously applied to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage.

[0071] Specifically, after the ramp voltage is applied for the first time, the initial threshold voltage and the test threshold voltage are compared. If the threshold voltage drops, it means that the oxide layer has failed. If the threshold voltage remains unchanged or increases, the ramp voltage should continue to be applied to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage.

[0072] Step S102, determining the limit gate voltage, reference gate leakage current and target ramp voltage of the target silicon carbide device to be tested according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, wherein the limit gate voltage is one of all the ramp voltages applied, the reference gate leakage current is the test gate leakage current corresponding to the limit gate voltage, and the target ramp voltage is the ramp voltage corresponding to the limit gate voltage;

[0073] Step S103 , using the reference gate leakage current and the target ramp voltage to test a non-target silicon carbide device to be tested, to determine whether a gate oxide layer of the non-target silicon carbide device to be tested is failed.

[0074] In the above steps, by applying the ramp voltage to the gate of the target silicon carbide device to be tested with the ramp voltage continuously increased as a reference, a plurality of test gate leakage currents and a plurality of test threshold voltages are obtained, and according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, the limit gate voltage, the reference gate leakage current and the target ramp voltage of the target silicon carbide device to be tested are determined, so that the required parameters for judging whether the gate oxide layer of the silicon carbide device to be tested is failed are accurately obtained. Finally, the non-target silicon carbide device to be tested is tested using the reference gate leakage current and the target ramp voltage to determine whether the gate oxide layer of the non-target silicon carbide device to be tested is failed. For devices with defective gate oxide layers, when a voltage is applied to the gate, the electric field in the oxide layer is locally enhanced, so that hole capture is dominant, and the FN tunneling current is enhanced, thereby causing changes in the threshold voltage and the gate leakage current. Devices with defective gate oxide layers are screened out by judging that the threshold voltage is reduced and the gate leakage current is increased, thereby solving the problem that the existing scheme lacks a scheme for efficiently and quickly screening gate oxide layer failures of silicon carbide devices.

[0075] In one embodiment of the present application, the reference gate leakage current and the target ramp voltage are used to test a non-target silicon carbide device to be tested, and determining whether a gate oxide layer of the non-target silicon carbide device to be tested fails includes:

[0076] Acquiring an initial threshold voltage of the non-target silicon carbide device to be tested, wherein the initial threshold voltage of the non-target silicon carbide device to be tested is a turn-on voltage threshold of the non-target silicon carbide device to be tested in an initial state;

[0077] Applying the target ramp voltage to the gate of the non-target silicon carbide device to be tested to obtain a detection gate leakage current and a detection threshold voltage;

[0078] When the detection threshold voltage is less than the initial threshold voltage of the non-target silicon carbide device to be tested, and / or the detection gate leakage current is greater than the reference gate leakage current, determining that the gate oxide layer of the non-target silicon carbide device to be tested has failed;

[0079] When the detection threshold voltage is greater than or equal to the initial threshold voltage of the non-target silicon carbide device to be tested, and the detection gate leakage current is less than or equal to the reference gate leakage current, it is determined that the gate oxide layer of the non-target silicon carbide device to be tested is valid.

[0080] Specifically, each test needs to compare the obtained detection threshold voltage with the corresponding initial threshold voltage, and at the same time, compare the obtained detection gate leakage current with the reference gate leakage current, and determine whether the gate oxide layer of the above-mentioned non-target silicon carbide device to be tested has failed based on the comparison results.

[0081] In one embodiment of the present application, in the process of applying the above-mentioned ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage to obtain multiple test gate leakage currents and multiple test threshold voltages, the above-mentioned method also includes: when the above-mentioned ramp voltage at the current time is greater than or equal to the maximum value of the target ramp voltage, determining that the above-mentioned ramp voltage at the current time is the above-mentioned ramp voltage applied to the gate of the above-mentioned target silicon carbide device to be tested for the last time.

[0082] In an embodiment of the present application, the method further includes: determining the target ramp voltage maximum value to be a preset ramp voltage maximum value corresponding to the specification of the target silicon carbide device to be tested.

[0083] In one embodiment of the present application, the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, and a plurality of test gate leakage currents are obtained, including: short-circuiting the drain and source of the target silicon carbide device to be tested, and applying the ramp voltage to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, and obtaining a plurality of test gate leakage currents;

[0084] Based on the continuously increasing ramp voltage, the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain multiple test threshold voltages, including: based on the continuously increasing ramp voltage, after applying the ramp voltage to the gate of the target silicon carbide device to be tested, the gate and drain of the target silicon carbide device to be tested are short-circuited to obtain the multiple test threshold voltages.

[0085] Specifically, the drain and source of the target silicon carbide device to be tested are short-circuited, and the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, thereby achieving the purpose of determining multiple test gate leakage currents; based on the continuously increasing ramp voltage, after the ramp voltage is applied to the gate of the target silicon carbide device to be tested, the gate and drain of the target silicon carbide device to be tested are short-circuited to obtain multiple test threshold voltages, thereby achieving the purpose of determining multiple test threshold voltages.

[0086] In one embodiment of the present application, a test system for gate oxide failure of a silicon carbide device to be tested comprises a first switching device, a second switching device, a voltage application module and a current application module, wherein the first selection end of the first switching device is used to be electrically connected to the voltage application module, the second selection end of the first switching device is used to be electrically connected to the current application module, the fixed end of the first switching device is used to be electrically connected to the first selection end of the second switching device and the gate of the target silicon carbide device to be tested, respectively, the second selection end of the second switching device is used to be grounded, and the fixed end of the second switching device is electrically connected to the drain of the target silicon carbide device to be tested;

[0087] The drain and source of the target silicon carbide device to be tested are short-circuited, and the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, so as to obtain a plurality of test gate leakage currents, including: the drain and source of the target silicon carbide device to be tested are short-circuited by electrically connecting the first selection end of the first switching device to the voltage application module, and the second selection end of the second switching device is grounded, so as to obtain a plurality of the test gate leakage currents;

[0088] Specifically, by electrically connecting the first selection end of the above-mentioned first switching device to the above-mentioned voltage application module, and grounding the second selection end of the above-mentioned second switching device, the drain and source of the above-mentioned target silicon carbide device to be tested are short-circuited, so that the voltage application module applies a ramp voltage to the gate of the target silicon carbide device to be tested.

[0089] Based on the continuously increasing ramp voltage, after the ramp voltage is applied to the gate of the target silicon carbide device to be tested, the gate and the drain of the target silicon carbide device to be tested are short-circuited to obtain the multiple test threshold voltages, including: electrically connecting the second selection end of the first switching device to the current application module respectively, and electrically connecting the fixed end of the first switching device and the first selection end of the second switching device to short-circuit the gate and the drain of the target silicon carbide device to be tested, so as to obtain the multiple test threshold voltages.

[0090] Specifically, the second selection end of the first switching device is electrically connected to the current application module, and the fixed end of the first switching device is electrically connected to the first selection end of the second switching device, so that the gate and the drain of the target silicon carbide device to be tested are short-circuited, so that the current application module applies a small current I to the drain. DS , the measured voltage between the gate and the source is the threshold voltage.

[0091] In addition, a specific embodiment is provided:

[0092] Step S1: Testing the initial threshold voltage V of the SiC MOSFET device to be testedGS(th)0 .

[0093] Step S2: Repeatedly apply a ramp voltage V to the gate GS (Gradually increase from zero to the set value V GS ), each time gradually increasing the gate voltage V GS +ΔV GS , the gate leakage current mapping relationship I is measured during each voltage application process G -V G , test threshold voltage V after voltage application GS(th) , and the test continues until the device gate fails. The ramp voltage VGS1 applied to the device for the first time is the working voltage in the factory data sheet, and the threshold voltage V GS(th)1 and gate leakage current mapping relationship I G1 -V G1 ; Apply the ramp voltage V for the second time GS2 =V GS1 +ΔV GS , test device threshold voltage V GS(th)2 and gate leakage current mapping relationship I G2 -V G2 ; And so on, the ramp voltage V is applied for the i-th time GSi =V GSi +iΔV GS , test device threshold voltage V GS(th)i and gate leakage current mapping relationship I Gi -V Gi , where the gate voltage increment ΔV GS The smaller it is, the more accurate the screening limit voltage will be. 1V or 2V is recommended.

[0094] Step S3: respectively draw threshold voltage mapping relationship and gate leakage current mapping relationship diagrams under different gate voltages.

[0095] Step S4: Determine the screening limit gate voltage, and take the gate voltage corresponding to the threshold voltage starting to drop and the gate leakage current mapping relationship before drifting in the threshold voltage vs. gate voltage mapping relationship as the screening limit gate voltage V GSmax .

[0096] Step S5: Under normal temperature, the gate oxide layer of the device under test is screened and tested, and a limit gate voltage V is applied to the gate. Gmax The ramp voltage is used to determine the changes in the threshold voltage and gate leakage current. If the threshold voltage does not change relative to the initial value and the gate leakage current meets the specification value, the device is considered qualified.

[0097] The threshold voltage test method in step S1, step S2 and step S5 is as follows: the drain and gate of the silicon carbide device to be tested are short-circuited, and a small current IDS is applied to the drain according to the device data sheet. The voltage between the gate and the source measured is the threshold voltage.

[0098] The ramp voltage application method and gate leakage current measurement method in step S2 and step S5 are as follows: the drain and source of the silicon carbide device to be tested are short-circuited, a ramp voltage is applied to the gate, and a mapping relationship between gate leakage current and gate voltage change is measured.

[0099] By controlling the second switch device, the drain and source of the device under test DUT are short-circuited, and by controlling the first switch device, it is connected to the ammeter, and a ramp voltage V is applied to the device under test through the voltage source meter. G , and test the gate leakage current through the ammeter at the same time. Switch the second switch device to short-circuit the drain and gate of the device under test DUT, switch the first switch device to connect to the current source meter, and apply the threshold voltage to the device under test through the current source meter to measure the small current I DS , the second voltmeter tests the voltage between the gate and the source, which is the threshold voltage.

[0100] Select a silicon carbide device DUT1 to be tested and test the initial threshold voltage V GS(th)0 =2.908V.

[0101] A ramp voltage from 0 to 20 V is applied to the gate of the device DUT1, and the gate leakage current mapping relationship is measured. The mapping relationship is the gate leakage current changing with the gate voltage I G1 -V G1 , test threshold voltage V GS(th)1 =2.908V; apply a ramp voltage from 0 to 22V and measure the gate leakage current mapping relationship I G2 -V G2 , test threshold voltage V GS(th)1 =2.908V; apply a ramp voltage from 0 to 24V and measure the gate leakage current mapping relationship I G3 -V G3 , test threshold voltage V GS(th)1 =2.908V; gradually increase the gate ramp voltage in 2V increments until the device gate fails at 52V.

[0102] like Figure 2 As shown, the drain and source of the device are short-circuited, that is, V DS =0V, the gate is applied with a ramp voltage V GS0 , measure the gate leakage current during the voltage application process, then remove the gate voltage, short-circuit the gate and drain of the device, apply a pulse of small current, and test the threshold voltage. Then the drain and source of the device are short-circuited again, and a ramp voltage V is applied to the gate. GS0 +ΔV GS , and repeat the above process.

[0103] The threshold voltage under different gate voltages is shown in Table 1 and Figure 3 shown.

[0104] Table 1

[0105]

[0106] from Figure 3 It can be seen that when the gate voltage is greater than 36V, the threshold voltage decreases and the gate leakage current drifts to the left. Therefore, 36V is determined to be the screening limit gate voltage for this batch of devices.

[0107] A ramp voltage of 0-36V is applied to the gate of the device DUT2 to be screened, and the gate leakage current is tested to be 20nA, and the threshold voltage is 2.908V. The device DUT2 is judged to be qualified. A ramp voltage of 0-36V is applied to the gate of the device DUT3 to be screened, and the gate leakage current is tested to be 1uA, and the threshold voltage is 2.593V. The device DUT3 is judged to be unqualified.

[0108] The present application also provides a silicon carbide device to be tested, wherein the silicon carbide device to be tested is tested by using any one of the above-mentioned gate oxide layer failure testing methods of the silicon carbide device to be tested.

[0109] By applying the ramp voltage to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, a plurality of test gate leakage currents and a plurality of test threshold voltages are obtained, and according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, the limit gate voltage, the reference gate leakage current and the target ramp voltage of the target silicon carbide device to be tested are determined, so that the required parameters for judging whether the gate oxide layer of the silicon carbide device to be tested is failed are accurately obtained. Finally, the non-target silicon carbide device to be tested is tested using the reference gate leakage current and the target ramp voltage to determine whether the gate oxide layer of the non-target silicon carbide device to be tested is failed. For devices with defective gate oxide layers, when voltage is applied to the gate, the electric field in the oxide layer is locally enhanced, hole capture is dominant, and FN tunneling current is enhanced, thereby causing changes in threshold voltage and gate leakage current. Devices with defective gate oxide layers are screened out by judging that the threshold voltage is reduced and the gate leakage current is increased, thereby solving the problem that the existing scheme lacks a scheme for efficiently and quickly screening gate oxide layer failures of silicon carbide devices.

[0110] The present application also provides a test system for gate oxide failure of a silicon carbide device to be tested, such as Figure 4 As shown, the system includes: a first switch device K 1 , the second switch device K 2, a voltage applying module C1, a current applying module C2 and a silicon carbide device to be tested DUT, the first selection end of the above-mentioned first switching device is used to be electrically connected to the above-mentioned voltage applying module, the second selection end of the above-mentioned first switching device is used to be electrically connected to the above-mentioned current applying module, the fixed end of the above-mentioned first switching device is used to be electrically connected to the first selection end of the above-mentioned second switching device and the gate of the target silicon carbide device to be tested respectively, the second selection end of the above-mentioned second switching device is used to be grounded, and the fixed end of the above-mentioned second switching device is electrically connected to the drain of the above-mentioned target silicon carbide device to be tested, wherein any one of the above-mentioned gate oxide layer failure test methods of the silicon carbide device to be tested is adopted to test the above-mentioned silicon carbide device to be tested.

[0111] By applying the ramp voltage to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, a plurality of test gate leakage currents and a plurality of test threshold voltages are obtained, and according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, the limit gate voltage, the reference gate leakage current and the target ramp voltage of the target silicon carbide device to be tested are determined, so that the required parameters for judging whether the gate oxide layer of the silicon carbide device to be tested is failed are accurately obtained. Finally, the non-target silicon carbide device to be tested is tested using the reference gate leakage current and the target ramp voltage to determine whether the gate oxide layer of the non-target silicon carbide device to be tested is failed. For devices with defective gate oxide layers, when voltage is applied to the gate, the electric field in the oxide layer is locally enhanced, hole capture is dominant, and FN tunneling current is enhanced, thereby causing changes in threshold voltage and gate leakage current. Devices with defective gate oxide layers are screened out by judging that the threshold voltage is reduced and the gate leakage current is increased, thereby solving the problem that the existing scheme lacks a scheme for efficiently and quickly screening gate oxide layer failures of silicon carbide devices.

[0112] In one embodiment of the present application, Figure 4 As shown, the voltage application module C1 includes: a voltage source meter and a first voltage meter V1, the first end of the voltage source meter and the first end of the first voltage meter are respectively used to be electrically connected to the first selection end of the first switching device, and the second end of the voltage source meter and the second end of the first voltage meter are respectively grounded.

[0113] The voltage source meter is used for providing a ramp voltage, and the first voltage meter is used for detecting the ramp voltage.

[0114] In one embodiment of the present application, Figure 4 As shown, the current applying module C2 includes: a current source table I DS and a second voltmeter V2, the first end of the current source meter and the first end of the second voltmeter are respectively used to be electrically connected to the second selection end of the first switching device, and the second end of the current source meter and the second end of the second voltmeter are respectively grounded.

[0115] The current source meter is used to provide a small current I DS , the second voltmeter is used to detect the threshold voltage.

[0116] In one embodiment of the present application, Figure 4 As shown, the gate oxide layer failure test system of the silicon carbide device to be tested further includes an ammeter A1, which is used to be electrically connected between the first selection terminal of the first switching device and the voltage applying module.

[0117] The ammeter detects the gate leakage current.

[0118] The present application also provides an electronic device, which includes any one of the above-mentioned gate oxide layer failure testing systems for the silicon carbide device to be tested. By applying the ramp voltage to the gate of the target silicon carbide device to be tested based on the continuously increasing ramp voltage, a plurality of test gate leakage currents and a plurality of test threshold voltages are obtained, and according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, the limit gate voltage, the reference gate leakage current and the target ramp voltage of the target silicon carbide device to be tested are determined, so that the required parameters for judging whether the gate oxide layer of the silicon carbide device to be tested is failed are accurately obtained. Finally, the non-target silicon carbide device to be tested is tested using the reference gate leakage current and the target ramp voltage to determine whether the gate oxide layer of the non-target silicon carbide device to be tested is failed. For devices with defective gate oxide layers, when voltage is applied to the gate, the electric field in the oxide layer is locally enhanced, hole capture is dominant, and FN tunneling current is enhanced, thereby causing changes in threshold voltage and gate leakage current. Devices with defective gate oxide layers are screened out by judging that the threshold voltage is reduced and the gate leakage current is increased, thereby solving the problem that the existing scheme lacks a scheme for efficiently and quickly screening gate oxide layer failures of silicon carbide devices.

[0119] It should be noted that the above electrical connection can be a direct electrical connection or an indirect electrical connection. Direct electrical connection means that two devices are directly connected, and indirect electrical connection means that other devices such as capacitors and resistors are also connected between the connected A and B.

[0120] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0121] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0122] 1) The test method for gate oxide failure of the silicon carbide device to be tested of the present application, by taking the ramp voltage as a reference, applying the ramp voltage to the gate of the target silicon carbide device to be tested, obtaining multiple test gate leakage currents and multiple test threshold voltages, and determining the limit gate voltage, the reference gate leakage current and the target ramp voltage of the target silicon carbide device to be tested according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, so as to accurately obtain the required parameters for judging whether the gate oxide layer of the silicon carbide device to be tested has failed, and finally using the reference gate leakage current and the target ramp voltage to determine whether the gate oxide layer of the silicon carbide device to be tested has failed. The target ramp voltage is used to test the non-target silicon carbide device to be tested to determine whether the gate oxide layer of the non-target silicon carbide device to be tested has failed. For devices with defective gate oxide layers, when voltage is applied to the gate, the electric field in the oxide layer will be locally enhanced, so that hole capture is dominant, and the FN tunneling current is enhanced, thereby causing changes in the threshold voltage and the gate leakage current. By judging that the threshold voltage decreases and the gate leakage current increases, devices with gate oxide layer defects are screened out, thereby solving the problem that the existing solutions lack a solution for efficiently and quickly screening the gate oxide layer failure of silicon carbide devices.

[0123] 2) The gate oxide layer failure test system of the silicon carbide device to be tested of the present application, by taking the ramp voltage as a reference, applying the ramp voltage to the gate of the target silicon carbide device to be tested, obtaining multiple test gate leakage currents and multiple test threshold voltages, and determining the limit gate voltage, the reference gate leakage current and the target ramp voltage of the target silicon carbide device to be tested according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, so as to accurately obtain the required parameters for judging whether the gate oxide layer of the silicon carbide device to be tested has failed, and finally using the reference gate leakage current and the target ramp voltage to determine whether the gate oxide layer of the silicon carbide device to be tested has failed. The target ramp voltage is used to test the non-target silicon carbide device to be tested to determine whether the gate oxide layer of the non-target silicon carbide device to be tested has failed. For devices with defective gate oxide layers, when voltage is applied to the gate, the electric field in the oxide layer will be locally enhanced, so that hole capture is dominant, and the FN tunneling current is enhanced, thereby causing changes in the threshold voltage and the gate leakage current. By judging that the threshold voltage decreases and the gate leakage current increases, devices with gate oxide layer defects are screened out, thereby solving the problem that the existing solutions lack a solution for efficiently and quickly screening the gate oxide layer failure of silicon carbide devices.

[0124] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for testing gate oxide failure of a silicon carbide device to be tested, characterized in that: include: Acquire a gate leakage current mapping relationship and a threshold voltage mapping relationship, wherein the gate leakage current mapping relationship represents a relationship between a ramp voltage and a test gate leakage current, and the threshold voltage mapping relationship represents a relationship between the ramp voltage and a test threshold voltage; Determine, according to the gate leakage current mapping relationship and the threshold voltage mapping relationship, a limit gate voltage, a reference gate leakage current and a target ramp voltage of the target silicon carbide device to be tested, wherein the limit gate voltage is one of all the ramp voltages applied, the reference gate leakage current is the test gate leakage current corresponding to the limit gate voltage, and the target ramp voltage is the ramp voltage corresponding to the limit gate voltage; Using the reference gate leakage current and the target ramp voltage, a non-target silicon carbide device to be tested is tested to determine whether a gate oxide layer of the non-target silicon carbide device to be tested fails; The non-target silicon carbide device to be tested is tested using the reference gate leakage current and the target ramp voltage to determine whether a gate oxide layer of the non-target silicon carbide device to be tested fails, including: Acquiring an initial threshold voltage of the non-target silicon carbide device to be tested, wherein the initial threshold voltage of the non-target silicon carbide device to be tested is a turn-on voltage threshold of the non-target silicon carbide device to be tested in an initial state; Applying the target ramp voltage to the gate of the non-target silicon carbide device to be tested to obtain a detection gate leakage current and a detection threshold voltage; When the detection threshold voltage is less than the initial threshold voltage of the non-target silicon carbide device to be tested, and / or the detection gate leakage current is greater than the reference gate leakage current, determining that the gate oxide layer of the non-target silicon carbide device to be tested has failed; When the detection threshold voltage is greater than or equal to the initial threshold voltage of the non-target silicon carbide device to be tested, and the detection gate leakage current is less than or equal to the reference gate leakage current, determining that the gate oxide layer of the non-target silicon carbide device to be tested is valid; Obtain gate leakage current mapping relationship and threshold voltage mapping relationship, including: Short-circuiting the drain and source of the target silicon carbide device to be tested, and applying the ramp voltage to the gate of the target silicon carbide device to be tested with the ramp voltage continuously increased as a reference, to obtain a plurality of test gate leakage currents; Based on the continuously increasing ramp voltage, after applying the ramp voltage to the gate of the target silicon carbide device to be tested, the gate and the drain of the target silicon carbide device to be tested are short-circuited to obtain a plurality of test threshold voltages; The gate leakage current mapping relationship and the threshold voltage mapping relationship are generated based on all the applied ramp voltages, all the tested gate leakage currents, and all the tested threshold voltages.

2. The method according to claim 1, characterized in that Based on the continuously increasing ramp voltage, the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain multiple test gate leakage currents and multiple test threshold voltages, including: The ramp voltage is continuously increased with a preset step length as a reference, and the ramp voltage is applied to the gate of the target silicon carbide device to be tested to obtain a plurality of test gate leakage currents and a plurality of test threshold voltages.

3. The method according to claim 1, characterized in that In the process of applying the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage to obtain multiple test gate leakage currents and multiple test threshold voltages, the method further includes: Acquiring an initial threshold voltage of a target silicon carbide device to be tested, wherein the initial threshold voltage of the target silicon carbide device to be tested is a turn-on voltage threshold of the target silicon carbide device to be tested in an initial state; Applying the ramp voltage to the gate of the target silicon carbide device to be tested for the first time to obtain a test threshold voltage; According to the initial threshold voltage and the test threshold voltage of the target silicon carbide device to be tested, it is determined that the gate oxide layer of the target silicon carbide device to be tested has failed, or the ramp voltage is continuously increased as a reference and the ramp voltage is applied to the gate of the target silicon carbide device to be tested.

4. The method according to claim 3, characterized in that Determining that a gate oxide layer of the target silicon carbide device to be tested has failed according to the initial threshold voltage and the test threshold voltage of the target silicon carbide device to be tested, or continuing to apply the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage, comprising: When the test threshold voltage is less than the initial threshold voltage of the target silicon carbide device to be tested, determining that a gate oxide layer of the target silicon carbide device to be tested is failed; When the test threshold voltage is greater than or equal to the initial threshold voltage of the target silicon carbide device to be tested, the ramp voltage is continuously applied to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage.

5. The method according to claim 1, characterized in that In the process of applying the ramp voltage to the gate of the target silicon carbide device to be tested based on continuously increasing the ramp voltage to obtain multiple test gate leakage currents and multiple test threshold voltages, the method further includes: When the current ramp voltage is greater than or equal to the target ramp voltage maximum value, it is determined that the current ramp voltage is the ramp voltage applied to the gate of the target silicon carbide device to be tested for the last time.

6. The method according to claim 5, characterized in that The method further comprises: The target ramp voltage maximum value is determined to be a preset ramp voltage maximum value corresponding to the specification of the target silicon carbide device to be tested.

7. The method according to claim 1, characterized in that A test system for gate oxide failure of a silicon carbide device to be tested comprises a first switching device, a second switching device, a voltage application module and a current application module, wherein a first selection end of the first switching device is used to be electrically connected to the voltage application module, a second selection end of the first switching device is used to be electrically connected to the current application module, a fixed end of the first switching device is used to be electrically connected to the first selection end of the second switching device and the gate of the target silicon carbide device to be tested, respectively, a second selection end of the second switching device is used to be grounded, and a fixed end of the second switching device is electrically connected to the drain of the target silicon carbide device to be tested; The drain and source of the target silicon carbide device to be tested are short-circuited, and the ramp voltage is applied to the gate of the target silicon carbide device to be tested based on a continuously increasing ramp voltage, so as to obtain a plurality of test gate leakage currents, including: the drain and source of the target silicon carbide device to be tested are short-circuited by electrically connecting the first selection end of the first switching device to the voltage application module, and the second selection end of the second switching device is grounded, so as to obtain a plurality of the test gate leakage currents; Based on continuously increasing the ramp voltage, after the ramp voltage is applied to the gate of the target silicon carbide device to be tested, the gate and the drain of the target silicon carbide device to be tested are short-circuited to obtain a plurality of the test threshold voltages, including: electrically connecting the second selection end of the first switching device to the current application module respectively, and electrically connecting the fixed end of the first switching device and the first selection end of the second switching device to short-circuit the gate and the drain of the target silicon carbide device to be tested, to obtain a plurality of the test threshold voltages.

8. A test system for gate oxide failure of a silicon carbide device to be tested, characterized in that: include: A first switching device, a second switching device, a voltage application module, a current application module and a silicon carbide device to be tested, wherein the first selection end of the first switching device is used to be electrically connected to the voltage application module, the second selection end of the first switching device is used to be electrically connected to the current application module, the fixed end of the first switching device is used to be electrically connected to the first selection end of the second switching device and the gate of the target silicon carbide device to be tested, respectively, the second selection end of the second switching device is used to be grounded, and the fixed end of the second switching device is electrically connected to the drain of the target silicon carbide device to be tested, wherein the silicon carbide device to be tested is tested using the test method for gate oxide failure of the silicon carbide device to be tested described in any one of claims 1 to 7.

9. The gate oxide layer failure testing system of the silicon carbide device to be tested according to claim 8, characterized in that: The voltage application module includes: a voltage source meter and a first voltage meter, the first end of the voltage source meter and the first end of the first voltage meter are respectively used to be electrically connected to the first selection end of the first switching device, and the second end of the voltage source meter and the second end of the first voltage meter are respectively grounded.

10. The gate oxide layer failure testing system of the silicon carbide device to be tested according to claim 8, characterized in that: The current application module includes: a current source meter and a second voltmeter, wherein the first end of the current source meter and the first end of the second voltmeter are respectively used to be electrically connected to the second selection end of the first switching device, and the second end of the current source meter and the second end of the second voltmeter are respectively grounded.

11. The gate oxide layer failure testing system of the silicon carbide device to be tested according to claim 8, characterized in that: The gate oxide layer failure testing system of the silicon carbide device to be tested further includes an ammeter, which is used to be electrically connected between the first selection end of the first switching device and the voltage application module.

12. An electronic device, characterized in that: A test system for gate oxide failure of a silicon carbide device to be tested comprising any one of claims 8 to 11.

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