Semiconductor structure and method for manufacturing the same

Abstract

The embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a first substrate, the first substrate having a central region and an edge region; forming a first dielectric layer covering the central region and the edge region, wherein the thickness of the first dielectric layer covering the edge region gradually decreases in a direction away from the central region; forming a first filling layer of the first dielectric layer covering the edge region; flattening the first filling layer, and forming a first edge region on the surface of the first filling layer that is flush with the surface of the first dielectric layer in the central region. The semiconductor structure obtained by the manufacturing method provided by the embodiment of the present disclosure has a larger area of ​​flat surface, which can effectively improve the problem of large uneven areas in the edge region and the central region, and further increase the effective use area of ​​the substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] With the rapid growth of data capacity demand, increasing packaging density to improve integration and thus obtain higher storage capacity has become an important goal of integrated circuit manufacturing at this stage. Under this prospect, 3D-IC (three-dimensional integrated circuit) technology has been widely used. It is a technology that stacks and bonds wafers with the same or different functions together. This technology has the advantages of high performance, low cost and high integration.

[0003] Stacking bonding is a key process in 3D packaging technology, which is used to stack multiple wafers or chips in the vertical direction and achieve electrical connections. This technology can significantly improve the integration density of chips, shorten the signal transmission path, reduce power consumption, and reduce the package volume. It is an important technology in the fields of high-performance computing, storage, and mobile devices. The firmness between the bonding surfaces during the bonding process directly affects the yield of the stacking bonding process. If there is a problem of poor bonding between the surfaces bonded to each other, there will be risks such as cracking and bonding failure in subsequent thinning or other processes. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure with higher integration and a method for manufacturing the same.

[0005] Problems to be solved by the technical spirit of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a first substrate, the first substrate having a central area and an edge area; forming a first dielectric layer covering the central area and the edge area, wherein the thickness of the first dielectric layer covering the edge area gradually decreases in a direction away from the central area; forming a first filling layer of the first dielectric layer covering the edge area; and flattening the first filling layer to form a first edge area on the surface of the first filling layer that is flush with the surface of the first dielectric layer in the central area.

[0007] The manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure also includes: providing a second substrate, the second substrate having a central area and an edge area; forming a second dielectric layer covering the central area and the edge area on the second substrate, wherein the thickness of the second dielectric layer covering the edge area gradually decreases in a direction away from the central area; forming a second filling layer covering the second dielectric layer on the edge area; planarizing the second filling layer, and forming a second edge area on the surface of the second filling layer that is flush with the surface of the second dielectric layer in the central area; aligning and bonding the second substrate to the first substrate so that the central area of ​​the first substrate is bonded to the central area of ​​the second substrate, and the first edge area is bonded to the second edge area.

[0008] The manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure also includes: performing a first edge trimming on the bonded first substrate and the second substrate, removing a portion of the edge area of ​​the first substrate and a portion of the edge area of ​​the second substrate, and at the same time, a portion of the first edge area and a portion of the second edge area are also removed; thinning the first substrate to form a first bonding body.

[0009] The method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure further includes: bonding a plurality of first bonding bodies to each other to form a second bonding body.

[0010] In the manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure, before bonding multiple first bonding bodies to each other to form a second bonding body, after thinning the first substrate, it also includes: forming a first bonding surface on the surface of the thinned first substrate, and the step of forming the first bonding surface includes: depositing a third dielectric layer covering the central area and the edge area on the surface of the thinned first substrate, and the thickness of the third dielectric layer gradually decreases in the direction away from the central area; depositing a third filling layer on the third dielectric layer in the edge area, flattening the third filling layer, and forming a third edge area on the surface of the third filling layer that is flush with the surface of the third dielectric layer in the central area; bonding multiple first bonding bodies to each other to form a second bonding body includes: bonding the central areas of the multiple first bonding bodies to each other, and bonding the third edge areas of the multiple first bonding bodies to each other.

[0011] The manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure also includes: performing a second edge trimming on the second bonding body, removing a portion of the edge area of ​​the second substrate retained after the first edge trimming and a portion of the third edge area in each first bonding body, wherein the width of the edge area of ​​the second substrate removed in the first edge trimming is the same as the width of the edge area removed in the second edge trimming.

[0012] In the manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure, after the central regions of the plurality of first bonding bodies are bonded to each other and the third edge regions of the plurality of first bonding bodies are bonded to each other, the method further includes: thinning the second substrate to form a second bonding body.

[0013] The manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure also includes: providing a third substrate, the third substrate having a central area and an edge area; forming a fourth dielectric layer covering the central area and the edge area, wherein the thickness of the fourth dielectric layer covering the edge area gradually decreases in a direction away from the central area; forming a fourth filling layer of the fourth dielectric layer covering the edge area; flattening the fourth filling layer, forming a fourth edge area on the surface of the fourth filling layer that is flush with the surface of the fourth dielectric layer in the central area; forming a second bonding surface on the surface of the thinned second bonding body; aligning and bonding the third substrate with the second bonding body so that the central area and the fourth edge area of ​​the third substrate are bonded to the second bonding surface.

[0014] In the manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure, after the second substrate is aligned and bonded to the first substrate, the method further includes: filling a first bonding layer between the first substrate and the second substrate, the first bonding layer at least covering the first dielectric layer, the second dielectric layer and the unbonded surfaces of the first filling layer and the second filling layer.

[0015] In the method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure, after forming the first bonding layer, the first substrate is thinned to form a first bonding body.

[0016] The method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure further includes: bonding a plurality of first bonding bodies to each other to form a second bonding body.

[0017] In the manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure, before bonding multiple first bonding bodies to each other to form a second bonding body, after thinning the first substrate, it also includes: forming a first bonding surface on the surface of the thinned first substrate, and the step of forming the first bonding surface includes: depositing a third dielectric layer covering the central area and the edge area on the surface of the thinned first substrate, and the thickness of the third dielectric layer gradually decreases in the direction away from the central area; depositing a third filling layer on the third dielectric layer in the edge area, flattening the third filling layer, and forming a third edge area on the surface of the third filling layer that is flush with the surface of the third dielectric layer in the central area; bonding multiple first bonding bodies to each other to form a second bonding body includes: bonding the central areas of the multiple first bonding bodies to each other, and bonding the third edge areas of the multiple first bonding bodies to each other.

[0018] In the semiconductor structure manufacturing method provided by some embodiments of the present disclosure, after the central regions of the plurality of first bonding bodies are bonded to each other and the third edge regions of the plurality of first bonding bodies are bonded to each other, the second bonding layer is filled between the first bonding bodies.

[0019] In the manufacturing method of the semiconductor structure provided by some embodiments of the present disclosure, after forming a first dielectric layer covering the central area and the edge area, and before forming a first filling layer of the first dielectric layer covering the edge area, the manufacturing method also includes: forming a first bonding pad in the first dielectric layer in the central area; after forming the first bonding pad, flattening the first dielectric layer so that the surface of the first bonding pad is flush with the surface of the first dielectric layer.

[0020] In the method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure, after forming the first edge region, the method further includes: forming a first bonding pad in the first dielectric layer, wherein a surface of the first bonding pad is flush with a surface of the first dielectric layer.

[0021] Some embodiments of the present disclosure also provide a semiconductor structure, including: a first substrate, the first substrate having a central region and an edge region; a first dielectric layer, the first dielectric layer covering the central region and the edge region, wherein the thickness of the first dielectric layer covering the edge region gradually decreases in a direction away from the central region; and a first filling layer, the first filling layer being formed above the first dielectric layer in the edge region, the surface of the first filling layer being flush with the surface of the first dielectric layer in the central region.

[0022] The semiconductor structure provided by some embodiments of the present disclosure also includes: a second substrate, the first substrate having a central area and an edge area; a second dielectric layer, the second dielectric layer covers the central area and the edge area of ​​the second substrate, wherein the thickness of the second dielectric layer covering the edge area gradually decreases in a direction away from the central area; a second filling layer, the second filling layer is formed above the second dielectric layer in the edge area, and the surface of the second filling layer is flush with the surface of the second dielectric layer in the central area; the first dielectric layer in the central area of ​​the first substrate is aligned and bonded with the second dielectric layer in the central area of ​​the second substrate, and the first filling layer is aligned and bonded with the second filling layer.

[0023] The semiconductor structure provided by some embodiments of the present disclosure further includes: a first bonding layer, which is arranged between the first substrate and the second substrate after bonding, and the first bonding layer at least covers the unbonded surfaces of the first filling layer and the second filling layer.

[0024] In the semiconductor structure provided by some embodiments of the present disclosure, the maximum radial distance from the center of the central region to the center of the central region is R1, the maximum radial distance from the first filling layer to the center of the central region is R2, and the maximum radial distance from the first bonding layer to the center of the central region is R3, wherein the difference between R2 and R1 is greater than the difference between R3 and R2.

[0025] The semiconductor structure surface obtained by the manufacturing method provided by the embodiment of the present disclosure has a larger flat area, which can effectively improve the problem of large uneven areas in the edge area and the center area, and further increase the effective use area of ​​the substrate or wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the embodiments of the present disclosure, and together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0027] Figure 1 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 2-Figure 10 A cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure; Fig.11 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 12-Figure 18 A cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure; Fig.19 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figure 20-Figure 22 A cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure; Fig.23 A cross-sectional top view of a semiconductor structure provided for an embodiment of the present disclosure.

[0028] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0030] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 A schematic diagram of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Figure 1 As shown, the method comprises the following steps: S101, providing a first substrate, wherein the first substrate has a central area and an edge area. Figure 2 In the embodiment of the present disclosure, the first substrate may be a substrate of a wafer, such as Figure 2 As shown, the first substrate 10 has a central region 101 and an edge region 102, and the edge region 102 is arranged around the central region 101. The central region 101 may be a region in the first substrate 10 where the semiconductor device 20 is arranged, and the edge region 102 may be a peripheral edge region of the wafer where the semiconductor device is arranged or not arranged.

[0032] The semiconductor device 20 may be a CMOS device, a memory device and / or other passive devices. The memory device may include a volatile memory or a non-volatile memory, etc. The volatile memory may include, for example, a DRAM, etc. In some embodiments, when the semiconductor device 20 is a DRAM memory device, it may be a storage element consisting of a transistor and a capacitor, or may be a collection of multiple storage elements.

[0033] S102, forming a first dielectric layer, wherein the first dielectric layer is formed on the first substrate, covering the central region and the edge region, wherein the thickness of the first dielectric layer covering the edge region gradually decreases in a direction away from the central region. Figure 2 , a first dielectric layer 40 is formed on the first substrate 10, and the first dielectric layer 40 covers the central region 101 and the edge region 102. The central region 101 is also provided with an interconnection layer 30 electrically connected to the semiconductor device 20, and the interconnection layer 30 is provided in the first dielectric layer 40. A first bonding pad 70 is provided in the first dielectric layer 40, and the first bonding pad 70 has a surface exposed to the first dielectric layer 40.

[0034] In some embodiments, the formation of the interconnection layer 30 is accompanied by the formation of an isolation dielectric. Therefore, the first dielectric layer 40 may be a dielectric layer formed after the interconnection layer 30 is formed. In this case, the first dielectric layer 40 is formed on the interconnection layer 30 .

[0035] The interconnection layer 30 may include one or more conductive layers, vias connecting the conductive layers, and contact plugs connected to the semiconductor device 20. The interconnection layer 30 may be made of metal material, such as tungsten, aluminum, copper, etc.

[0036] The first bonding pad 70 may include one or more conductive layers and vias connecting the conductive layers. The first bonding pad 70 may be made of metal material, such as copper, tin, gold, tungsten or other metals or alloys thereof.

[0037] The first dielectric layer 40 may be a laminated structure formed of an isolation material, including an interlayer dielectric layer, an intermetallic dielectric layer, etc. The isolation material may be a combination of one or more of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, LK dielectric material, etc., and is used to provide electrical isolation for each conductive layer and each via, contact plug, etc. in the interconnection layer 30. When the first dielectric layer 40 is located on the interconnection layer 30, the first dielectric layer 40 may be a laminated structure or a single-layer structure formed of an isolation material, and is mainly used to provide isolation for the first bonding pad 70 and a bonding dielectric surface.

[0038] The first substrate 10 further includes a through-hole interconnection structure 80 , such as TSV, penetrating a portion of the first substrate 10 . The through-hole interconnection structure 80 is connected to the interconnection layer 30 .

[0039] The central region 101 of the first substrate 10 has a relatively flat surface, and the edge region 102 is not flat enough relative to the central region 101, and is a curved surface with a certain curvature. This is because when preparing the semiconductor device 20, it is necessary to go through multiple processes such as thin film deposition and photoresist spin coating. Since the deposition reaction gas or photoresist is unevenly distributed at the center and edge of the wafer, the thickness of the material in the edge region is different from that in the central region, which may affect the accuracy of subsequent processes and the performance of the device. Therefore, the edge region of the wafer is usually not provided with the same semiconductor device as the central region, and some test structures may be provided to monitor the process quality.

[0040] Since the surfaces of the central region 101 and the edge region 102 of the first substrate 10 are uneven, for the same reason, when forming the first dielectric layer 40 , the thickness of the first dielectric layer 40 covering the edge region 102 gradually decreases in a direction away from the central region 101 .

[0041] In some embodiments, the first substrate 10 may be a circular substrate or wafer, and the direction away from the central region 101 is the radial direction from the center to the edge of the first substrate 10 .

[0042] In some embodiments, since the surface of the first dielectric layer 40 in the edge region 102 is uneven with the surface in the center region 101, this unevenness will affect the yield of subsequent processes. For example, when the first substrate 10 is bonded to another substrate or wafer, this edge unevenness will lead to an uneven bonding surface. The uneven bonding surface will directly lead to bonding failure in the edge region 102, forming a bonding smear. This failed bonding is a subsequent process, such as chipping of material on the unbonded edge region when the first substrate 10 is thinned. In order to prevent such problems from occurring, an edge trimming process can be used to remove the edge region 102 by cutting. Figure 3 An edge trimming process is performed on the first substrate 10 and the first dielectric layer 40 to remove the edge region 102 and the first dielectric layer 40 having an uneven surface on the edge region 102, for example, the edge region 102 having a width D1 is removed, and only the central region 101 and its corresponding portion are retained. Since the central region 101 has a relatively flat surface, the stability of subsequent processes can be guaranteed.

[0043] Although the edge trimming process can eliminate the yield risk caused by the unevenness of the surface edge area, the area of ​​the entire substrate or wafer is fixed and precious. Taking a 12-inch wafer as an example, generally speaking, the diameter of a 12-inch wafer is 300 mm (about 11.81 inches), that is, the radius is about 150 mm. The inventors of the present disclosure have found that when the radial distance changes from 147 mm or 147.5 mm to 150 mm, the thickness difference of the first dielectric layer 40 on its surface is not less than 2.5 microns. In other words, if the unevenness of the edge area is to be eliminated, when performing edge trimming, at least the area with a radial distance of 2.5 mm to 3 mm needs to be trimmed from the edge of the first substrate. This means that the effective area of ​​the first substrate for preparing semiconductor devices will become smaller.

[0044] In some embodiments, the edge trimming process may occur after the first substrate 10 is bonded to another substrate. Figure 4As shown, the other substrate has a structure that is the same as or similar to the first substrate 10, a semiconductor device 20' and an interconnection layer 30' connected to the semiconductor device 20' are arranged in the first dielectric layer 40' in the central region 101' of the other substrate, a first bonding pad 70' is arranged in the first dielectric layer 40', a through-hole interconnection structure 80' is arranged in the other substrate, and the through-hole interconnection structure 80' is connected to the interconnection layer 30'.

[0045] When the first substrate 10 is bonded to another substrate, the central region 101 and the central region 101' are aligned and bonded to achieve the bonding of the first bonding pad 70 and the first bonding pad 70' and the bonding of the first dielectric layer 40 and the first dielectric layer 40'. After the bonding is completed, the edge region 102' of the other substrate 10' and the first dielectric layer 40' located on the edge region 102' are trimmed by the edge trimming process. At the same time, the edge region 102 of the first substrate 10 and the first dielectric layer 40 thereon are also trimmed, thereby removing the bonding failure region between the edge region 102 and the edge region 102'. The width of the trimmed region is also D1, thereby reducing the risk of subsequent processes.

[0046] In some embodiments, three or more substrates or wafers may be bonded to each other. Figure 5 As shown, Figure 5A schematic diagram of three semiconductor substrates or wafers bonded to each other is shown. Another substrate 200 is provided, and the other substrate 200 has the same or similar structure as the first substrate 10. It has a central area 201 and an edge area 202, and the central area 201 and the edge area 202 are provided with a first dielectric layer 203, and the first dielectric layer 203 in the central area 201 is provided with a semiconductor device 204 and an interconnection layer 205 connecting the semiconductor device 204. The first bonding pad 206 is arranged in the first dielectric layer 203, and a through-hole interconnection structure 207 is formed in the substrate 200 and connected to the interconnection layer 205. Before the substrate 10' is bonded, the other substrate on the first substrate 10 is thinned to expose the through-hole interconnection structure 80', and another bonding pad 70' is formed on the surface of the exposed through-hole interconnection structure 80', and the surface of the thinned other substrate is used as the bonding surface, and the other bonding pad 70' is bonded to the first bonding pad 206 on the surface of the substrate 200. To ensure the bonding effect, the substrate 200 is edge trimmed before bonding, and the width of the trimmed area is D2, which is greater than D1. This is because it is difficult to keep the width of the edge trimmed area of ​​the substrate 200 and the substrate 10 completely consistent. In order to avoid poor bonding caused by trimming errors, it is generally necessary to trim the edge of the substrate 200 more to ensure that the substrate 200 is well bonded to the surface of another substrate. It can be seen that when multiple substrates or wafers are stacked and bonded, in order to ensure the bonding effect, the area of ​​the trimmed area of ​​the substrate or wafer will gradually increase, the area of ​​the substrate or wafer will be wasted, the number of effective chips on the substrate or wafer will decrease, and the production cost will increase.

[0047] After the interconnection layer 30 and the first dielectric layer 40 are completed, the manufacturing method of the embodiment of the present disclosure further includes: S103, forming a first filling layer of the first dielectric layer covering the edge area. Figure 6 As shown, a first filling layer 50 is deposited on the surface of the first dielectric layer 40 in the edge region 102. The formation of the first filling layer 50 can be achieved by means of an annular mold, and the mold can be an annular ring covering the central region 101, that is, the central region 101 is covered by the annular ring, and the edge region 102 is exposed outside the annular ring, and then the first filling layer 50 is formed on the edge region 102 by deposition or the like. The first filling layer 50 has a surface higher than the first dielectric layer 40 on the central region 101, that is, the first filling layer 50 has a portion protruding relative to the first dielectric layer 40 on the central region 101. The first filling layer 50 may include an oxide, such as silicon oxide. "Silicon oxide" is referred to herein as a compound containing silicon and oxygen atoms, including any and all stoichiometric possibilities of Si. x O y , x and y can be integers or non-integers.

[0048] S104, planarizing the first filling layer, and forming a first edge region on the surface of the first filling layer that is flush with the surface of the first dielectric layer in the central region. Figure 7 As shown, after forming the first filling layer 50, a planarization process is performed to planarize the first filling layer 50, and a first edge region 103 is formed on the surface of the first filling layer 50. The first edge region 103 has a surface flush with the first dielectric layer 40 on the central region 101. Due to the limitation of process conditions, the flushness here can be completely flush or substantially flush. The planarization process can be a chemical mechanical polishing process (CMP) or an etching planarization process. The planarization process can also planarize the first dielectric layer 40 on the central region 101 at the same time, so that the first dielectric layer 40 on the central region 101 and the first filling layer 50 form a flat surface.

[0049] The manufacturing method provided by the embodiment of the present disclosure has a larger area of ​​flat surface of the semiconductor structure, which can effectively improve the problem of large uneven area of ​​the edge area, and further increase the effective use area of ​​the substrate or wafer. Taking a 12-inch wafer as an example, the edge area with a radial distance from 147 mm or 147.5 mm to 150 mm has an uneven surface. After the manufacturing method of the above embodiment is used for this uneven area, the edge area with a radial distance from 147 mm or 147.5 mm to 149 mm or 149.5 mm will obtain a surface that is flush or relatively flush with the center area, effectively improving the morphology of the edge area.

[0050] In some embodiments, after forming the first dielectric layer covering the central region and the edge region, and before forming the first filling layer of the first dielectric layer covering the edge region, a first bonding pad is formed in the first dielectric layer in the central region. The process of forming the first bonding pad is described in detail below in conjunction with the corresponding drawings. Figure 8 As shown, a first dielectric layer 40 is formed covering the central region 101 and the edge region 102. Fig. 9 After forming the first dielectric layer 40, the first dielectric layer 40 is patterned, and a first bonding material layer 701 is formed in the first dielectric layer 40 in the central area 101. The process of forming the first bonding material layer 701 may adopt a deposition, electroplating or other process. After forming the first bonding material layer 701, the first bonding material layer 701 is planarized, and first bonding pads 70 that are isolated from each other and have surfaces exposed to the first dielectric layer 40 are formed in the first dielectric layer 40. The surfaces of the first bonding pads 70 are flush or substantially flush with the surface of the first dielectric layer 40, such as Figure 2 In some embodiments, there is a certain height difference between the surface of the first bonding pad 70 and the surface of the first dielectric layer 40 , which is also considered as a flush situation in the present disclosure.

[0051] In some embodiments, after forming the first bonding pad 70, the steps of forming a first filling layer 50 on the surface of the first dielectric layer 40 on the edge region 102 of the first substrate 10 and subsequently planarizing the first filling layer 50 to form a first edge region 103 are performed. Figure 6 and Figure 7 shown.

[0052] In the method for forming the first bonding pad provided in the above embodiment, the first bonding pad has been formed before the first filling layer is formed, that is, a surface planarization process needs to be performed to planarize the first bonding material and the first dielectric layer before the first filling layer is formed. After the first filling layer is formed, a surface planarization process is performed on the surface of the first filling layer.

[0053] The embodiment of the present disclosure also provides another method for forming a first bonding pad. The process of forming the first bonding pad is described in detail below in conjunction with the corresponding drawings. Figure 6 and Figure 7 , firstly forming the first dielectric layer 40 and the first filling layer 50, then planarizing the first filling layer 50, and forming the first edge region 103 on the surface of the first filling layer 50 which is flush with the surface of the first dielectric layer 40 in the central region 101. In this planarizing process, the surface of the first dielectric layer 40 in the central region 101 can also be planarized at the same time.

[0054] Continue to see Fig.10 After the surfaces of the first dielectric layer 40 and the first filling layer 50 are planarized to form the first edge region 103, the first dielectric layer 40 is patterned, and a first bonding material layer 701 is formed in the first dielectric layer 40 in the central region 101. The process of forming the first bonding material layer 701 may adopt a deposition, electroplating or other process. After the first bonding material layer 701 is formed, the first bonding material layer 701 is planarized, and first bonding pads 70 that are isolated from each other and have surfaces exposed to the first dielectric layer 40 are formed in the first dielectric layer 40. The surfaces of the first bonding pads 70 are flush or substantially flush with the surface of the first dielectric layer 40, such as Figure 7 shown.

[0055] In the method for forming the first bonding pad provided in the above embodiment, the first bonding pad is formed after the first filling layer is subjected to surface planarization so that the surface of the first filling layer is substantially flush with the surface of the first dielectric layer. That is, there is no need to perform a surface planarization process on the first dielectric layer before forming the first filling layer, saving the cost of the planarization process. After forming the first filling layer, a surface planarization process can be performed to achieve that the surfaces of the first filling layer and the first dielectric layer are substantially flush, and after subsequently forming the first bonding material layer, a surface planarization process is performed again to obtain the first bonding pad.

[0056] In some embodiments, the first bonding pad also includes a portion of the first bonding pad connected to the interconnect layer and a portion of the first bonding pad not connected to the interconnect layer, the portion of the first bonding pad connected to the interconnect layer is used to realize the lead-out of the interconnect layer signal, and the portion of the first bonding pad not connected to the interconnect layer is mainly used to increase the density of the first bonding pad or other bonding performance considerations. In some embodiments, the first bonding pad of the present disclosure can also be completely connected to the interconnect layer without being limited by the structure in the accompanying drawings.

[0057] Some other embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, specifically, Fig.11 As shown, Fig.11 This is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. The steps are listed below.

[0058] S201, providing a second substrate, wherein the second substrate has a central area and an edge area.

[0059] S202, forming a second dielectric layer covering the central area and the edge area on the second substrate, wherein the thickness of the second dielectric layer covering the edge area gradually decreases in a direction away from the central area.

[0060] S203, forming a second filling layer covering the second dielectric layer on the edge region.

[0061] S204 , planarizing the second filling layer to form a second edge region on the surface of the second filling layer that is flush with the surface of the second dielectric layer in the central region.

[0062] The second substrate may adopt the same structure and the same manufacturing method as the first substrate. Steps S201 to S204 correspond to steps S101 to S104. Therefore, steps S201 to S204 will not be described in detail here.

[0063] The specific structure of the second substrate can be found in Fig.12The second substrate 11 includes a central region 111 and an edge region 112, and the edge region 112 is arranged around the central region 111. The second dielectric layer 41 is formed in the central region 111 and the edge region 112 at the same time, and the thickness of the second dielectric layer 41 on the edge region 112 gradually decreases in the direction away from the central region 111. The second filling layer 51 is formed on the surface of the second dielectric layer 41 on the edge region 112, and has a second edge region 113 flush with the surface of the second dielectric layer 41 in the central region 111. The second filling layer 51 and the first filling layer 50 can be made of the same material. A semiconductor device 21 is also arranged in the central region 111, and a semiconductor device may or may not be arranged in the edge region 112. The semiconductor device 21 may be a device of the same type as the semiconductor device 20, or a device of a different type. The central region 111 also includes an interconnection layer 31 connecting the semiconductor device 21, and the interconnection layer 31 is arranged in the second dielectric layer 41. The interconnection layer 31 may have the same structure and be obtained by the same process as the interconnection layer 30; a second bonding pad 71 is provided in the second dielectric layer 41 of the central region 111, and the second bonding pad 71 is connected to the interconnection layer 31. The second bonding pad 71 may have the same structure and be obtained by the same process as the first bonding pad 70. The central region 111 of the second substrate 11 also includes a through-hole interconnection structure 81 that penetrates a portion of the second substrate 11, and the interconnection layer 31 is connected through the interconnection structure 81.

[0064] Continue to see Fig.11 and Fig.12 After the first substrate and the second substrate are processed, step S301 is performed, that is, the first substrate and the second substrate are aligned and bonded, so that the central area of ​​the first substrate is bonded to the central area of ​​the second substrate, and the first edge area is bonded to the second edge area.

[0065] The central region of the first substrate and the central region of the second substrate may be bonded by a dielectric-to-dielectric direct bonding process, or by a dielectric-to-dielectric or metal-to-metal bonding process, for example, a first bonding pad in the central region of the first substrate and a second bonding pad in the central region of the second substrate are bonded to each other. The first edge region and the second edge region may be bonded by a dielectric-to-dielectric direct bonding process.

[0066] Continue to see Fig.11 and Fig.13After the first substrate is bonded to the second substrate, step S302 is performed: the first edge trimming is performed on the bonded first substrate and the second substrate, a part of the edge region of the first substrate and a part of the edge region of the second substrate are removed, and the first substrate is thinned to form a first bonding body. During the first edge trimming process, a part of the first edge region and a part of the second edge region are also removed, and finally a first bonding body 200 is formed. The width of the first edge trimming is D3, the edge region 102 of the first substrate 10 is partially removed, and a part of the edge region 102 is retained; the first edge region 103 is also partially removed, and a part of the first filling layer 50 is retained. The edge region 112 of the second substrate 11 is also partially removed, and a part of the edge region 112 is retained; the second edge region 113 is also partially removed, and a part of the second filling layer 51 is retained. The retained part of the first filling layer 50 and the retained part of the second filling layer 51 are bonded to each other. In some embodiments, the first edge region 103 and the second edge region 113 may also be completely retained, that is, the first edge trimming only needs to remove part of the edge regions 102 and 112 except the first edge region 103 and the second edge region 113. After the first substrate 10 and the second substrate 11 are bonded, trimming and removing part of the first edge region 103 and part of the second edge region 113 can further improve the yield of the bonding edge.

[0067] In some embodiments, see Fig.13 After the first edge trimming, the first substrate is thinned to expose the other end of the through-hole interconnect structure 80 in the central area 101 of the first substrate 10, and the first substrate 10 reaches a predetermined thickness, thereby forming a first bonding body 200. The thinning treatment methods mainly include grinding and chemical mechanical polishing (CMP). Grinding is to remove the material on the surface of the wafer by mechanical means to achieve the purpose of thinning. Chemical mechanical polishing is a more sophisticated thinning method that combines the effects of chemical reaction and mechanical friction to achieve high-precision thinning and flattening. CMP can provide higher surface quality and more precise thickness control, but the process is relatively slow and the cost is also high. The first bonding body formed after thinning the first substrate can be further used for three-dimensional packaging to obtain products with smaller packaging size and higher integration.

[0068] In some embodiments, after forming the first bonding body 200 , the first bonding body 200 is singulated using a cutting tool, such as a cutting blade or a laser, to singulate the first bonding body 200 .

[0069] Continue to see Fig.11 and Fig.14After forming the first bonding body 200, the method further includes executing step S303 to form a first bonding surface on the surface of the thinned first substrate. The specific process of forming the first bonding surface is as follows:

[0070] like Fig.14 As shown, a third dielectric layer 42 covering the central region 101 and the edge region 102 is formed on the thinned surface of the first substrate 10. In the direction away from the central region 101, the third dielectric layer 42 has a gradually decreasing thickness, that is, the thickness of the third dielectric layer 42 above the edge region 102 gradually decreases with the increase of the radial distance. This is because, in the process of thinning the first substrate 10, the surface of the edge region 102 will still be uneven with the central region 101. Even if the central region 101 and the edge region 102 of the first substrate 10 are flush with each other, after the third dielectric layer 42 is formed, it is necessary to perform a surface planarization process on the third dielectric layer 42. Also due to the limitation of the process, the thickness of the third dielectric layer 42 in the edge region 102 will decrease with the increase of the radial distance. Therefore, after forming the third dielectric layer 42, the third filling layer 52 is covered on the third dielectric layer 42 in the edge region 102, and the third filling layer 52 is planarized, so that a third edge region 213 flush with the surface of the third dielectric layer 42 in the central region 101 is formed on the surface of the third filling layer 52 in the edge region 102. The third edge region 213 and the surface of the third dielectric layer 42 in the central region 101 form a first bonding surface 201.

[0071] The third dielectric layer 42 may have the same composition and be formed by the same process as the first dielectric layer 40 and the second dielectric layer 41 , and the third filling layer 52 may have the same composition and be formed by the same process as the first filling layer 50 and the second filling layer 51 .

[0072] The process of forming the first bonding surface 201 also includes the process of forming the third bonding pad 702. The third bonding pad 702 is formed in the third dielectric layer 42. The formation of the third bonding pad 702 can refer to the aforementioned process of forming the first bonding pad 70, which will not be repeated here.

[0073] Continue to see Fig.11 , Fig.15 and Fig.16 After the first bonding surface is formed, step S304 is performed to bond the plurality of first bonding bodies to each other to form a second bonding body.

[0074] like Fig.15As shown, the two first bonding bodies 200 are bonded to each other through the first bonding surface 201 to form the second bonding body 1, that is, the third dielectric layers 42 of the central area 101 are aligned and bonded to each other, and the third filling layers 52 of the third edge area 213 are bonded to each other. The bonding of the central area 101 can include dielectric-to-dielectric direct bonding and metal-to-metal direct bonding, for example, including the bonding of the third dielectric layers 42 and the bonding of the third bonding pads 702. The bonding of the third edge area 213 can include dielectric-to-dielectric direct bonding.

[0075] Fig.15 The figure shows a situation where two first bonding bodies are bonded to each other. In some embodiments, more than two first bonding bodies can be bonded to each other to form a bonding body with a higher degree of integration. The bonding body with a higher degree of integration can be obtained by bonding multiple second bonding bodies or by bonding more than two first bonding bodies. Whether it is bonding more than two first bonding bodies or bonding multiple second bonding bodies, the aforementioned steps of thinning and forming the third dielectric layer and the third filling layer are repeated to form the first bonding surface, which will not be repeated here. In some embodiments, the bonding body with a higher degree of integration includes four or more first bonding bodies or two or more second bonding bodies.

[0076] In some embodiments, in step S302, during the thinning process of the first substrate, the structure to be bonded in the first substrate is exposed, and after the thinning is completed, multiple first bonding bodies can be directly bonded, thereby omitting the step of forming the first bonding surface and saving process costs.

[0077] Continue to see Fig.16 After the two first bonding bodies 200 are bonded to each other to form the second bonding body 1, the second bonding body 1 is subjected to a second edge trimming, and the portion of the edge region 112 and the portion of the third edge region 213 of the second substrate 10 in each first bonding body 200 that are retained after the first edge trimming are removed to complete the second edge trimming, and the width of the second edge trimming is D4. In some embodiments, the width D3 of the first edge trimming is the same as the width D4 of the second edge trimming, because the surface of each first bonding body 200 forms a first bonding surface that is flat and extends to the edge region 102, so that the third edge region 213 that is flush with the third dielectric layer 52 of the central region 101 is formed in the edge region 102 of the first substrate 10 by forming the third filling layer 52, thereby ensuring that the two first bonding bodies can achieve stable bonding through the first bonding surface, and no more edge regions need to be removed during the second edge trimming process, and the use area of ​​the substrate or wafer is avoided from being wasted due to edge trimming while ensuring the bonding yield.

[0078] Continue to see Fig.17In some embodiments, after the second edge trimming of the second bonding body 1 is completed, the second substrate 11 is thinned to a target thickness, and finally the second bonding body 1 is formed. The thinning of the second substrate 11 means that the through-hole interconnection structure 81 in the second substrate 11 is exposed from the other side of the second substrate 11. Fig.17 2 shows a schematic diagram of the structure after a portion of the second substrate 11 is thinned. In some embodiments, all the second substrates 11 in the second bonding body 1 are thinned. In some embodiments, the second substrate 11 is thinned to the same thickness as the first substrate 10.

[0079] In some embodiments, after forming the second bonding body, multiple second bonding bodies can be further bonded to form a bonding structure with a higher degree of integration. Before bonding each second bonding body, the same process steps as the aforementioned formation of the first bonding surface can be used to form the bonding surface of each second bonding body to achieve the bonding of each second bonding body. The specific implementation process will not be repeated here.

[0080] In some embodiments, after forming the second bonding body 1 , the second bonding body 1 is singulated using a cutting tool, such as a cutting blade or a laser or other cutting tool.

[0081] In some embodiments, after forming the second bonding body, a third substrate is further provided to be bonded to the second bonding body, such as Fig.17 As shown, Fig.17 Schematic diagram of the structure of the third substrate bonded to the second bonding body. The third substrate 12 includes a central area 121 and an edge area 122, and the edge area 122 is arranged around the central area 121. The fourth dielectric layer 43 is formed in the central area 121 and the edge area 122 at the same time, and the thickness of the fourth dielectric layer 43 on the edge area 122 gradually decreases in the direction away from the central area 121. The fourth filling layer 53 is formed on the surface of the fourth dielectric layer 43 on the edge area 122, and has a fourth edge area 313 flush with the surface of the fourth dielectric layer 43 in the central area 121. The fourth filling layer 53 can be made of the same material as the first filling layer 50. A semiconductor device 22 is also arranged in the central area 121, and a semiconductor device can be arranged or not arranged in the edge area 122. The semiconductor device 22 can be a device of the same type as the semiconductor device 20, or a device of a different type. Fig.14The semiconductor device 22 shown in the figure is different from the semiconductor device 20 and the semiconductor device 21. The central area 121 also includes an interconnection layer 32 connected to the semiconductor device 22, and the interconnection layer 32 is arranged in the fourth dielectric layer 43. The interconnection layer 32 can be an interconnection layer composed of multiple layers of metal wires. A fourth bonding pad 72 is arranged in the fourth dielectric layer 43, and the fourth bonding pad 72 is connected to or not connected to the interconnection layer 32. A through-hole interconnection structure 82 that penetrates a portion of the third substrate 12 is arranged in the central area 121 of the third substrate 12, and the through-hole interconnection structure 82 is connected to the interconnection layer 32.

[0082] The third substrate 12 has the same structural features as the first substrate 10 and the second substrate 11. The formation methods of the fourth dielectric layer 43, the fourth filling layer 53 and the fourth edge region 313 are the same as the formation methods of the filling layers and the edge regions on the surfaces of the first substrate 10 and the second substrate 11 in the aforementioned embodiments. The fourth bonding pad 72 has the same formation method as the first bonding pad 70, which will not be repeated here.

[0083] Continue to see Fig.17 After the second substrate 11 in the second bonding body is thinned, a second bonding surface 202 is formed on the surface of the thinned second substrate 11. The method for forming the second bonding surface 202 can refer to Fig.11 The formation method of the first bonding surface 201 shown in the figure, the second bonding surface 202 includes the surface of the fifth dielectric layer 44 located on the central area 111 of the second substrate 11 and the surface of the fifth filling layer 54 located on the edge area 112 of the second substrate 11 and the fifth bonding pad 703 located in the fifth dielectric layer 44, and the fifth bonding pad 703 is connected to the through-hole interconnection structure 81 in the central area 111 of the second substrate 11. The structure and formation method of the fifth bonding pad 703 are the same as those of the third bonding pad 702, and will not be repeated here.

[0084] After the second bonding body 1 is bonded to the third substrate 12, a third edge trimming is performed, and finally the following is obtained: Fig.18 During the third edge trimming, the portion of the edge region 122 of the third substrate 12 and the portion where the second bonding surface 202 of the second bonding body 1 is not completely bonded to the fourth edge region on the third substrate 12 are removed, and the width of the third edge trimming is the same as the width of the first edge trimming and the second edge trimming.

[0085] In some embodiments, each semiconductor device in the second bonding body 1 is a memory device, such as a DRAM, and the semiconductor device in the third substrate 12 is a logic device.

[0086] In some embodiments, after the second bonding body is bonded to the third substrate, the bonding structure formed by the second bonding body and the third substrate is singulated using a cutting tool, such as a cutting blade or a laser or other cutting tool.

[0087] The present disclosure also provides a schematic flow chart of another semiconductor structure manufacturing method. Fig.11 and Fig.19 As shown, after the first substrate and the second substrate are aligned and bonded, that is, after step S301, step S401 is performed on the bonded first substrate and the second substrate.

[0088] S401, filling a first bonding layer between the first substrate and the second substrate, wherein the first bonding layer at least covers the first dielectric layer, the second dielectric layer, and the unbonded surfaces of the first filling layer and the second filling layer. Fig. 20 shown. Fig. 20 for Fig.12 Schematic diagram of the structure after the first substrate 10 and the second substrate 11 are bonded. The first bonding layer 60 is formed between the first substrate 10 and the second substrate 11 after bonding, and specifically, the first bonding layer 60 is formed between the gap between the first substrate 10 and the second substrate 11 after bonding, and at least covers the first dielectric layer 40, the second dielectric layer 41, and the unbonded surfaces of the first filling layer 50 and the second filling layer 51. Since the outer surface of a portion of the first dielectric layer 40 in the edge region 102 of the first substrate 10 is not completely covered by the first filling layer 50 when the first filling layer 50 is formed, the outer surface of a portion of the first dielectric layer 40 in the edge region 102 of the first substrate 10 after bonding and the unbonded surface of the first filling layer 50 will be exposed. Similarly, after the second filling layer 51 is formed, the outer surface of a portion of the second dielectric layer 41 in the edge region 112 of the second substrate 11 and the unbonded surface of the second filling layer 51 are also exposed.

[0089] In some embodiments, after forming the first bonding layer, step S402 is performed to thin the first substrate to form a first bonding body. Fig. 20 After forming the first bonding layer 60, the first substrate 10 is thinned to form the first bonding body 300. The thinning of the first substrate 10 is performed from the other surface away from the first dielectric layer 40. The thinning process mainly includes grinding and chemical mechanical polishing (CMP). The purpose is to thin the first substrate 10 to a target thickness to meet the requirements of product miniaturization.

[0090] In some embodiments, the first bonding layer 60 is a material with good fluidity, which can be well filled into the gap between the first substrate 10 and the second substrate 11, such as underfill. The first bonding layer 60 can be applied between the first substrate 10 and the second substrate 11 by a dispensing process.

[0091] In the embodiments of the present disclosure, by applying a first bonding layer between the first substrate and the second substrate after bonding, a supporting layer can be further formed between the edge areas of the first substrate and the second substrate to fill and support the edge areas of the first substrate and the second substrate, thereby further improving the edge stability of the first bonding body.

[0092] In some embodiments, after forming the first bonding body 300, the step S403 is continued to be performed to bond a plurality of first bonding bodies to each other to form a second bonding body. Fig.21 As shown, Fig.21 for Fig. 20 FIG. 4 is a schematic diagram of a structure of a second bonding body 400 formed after bonding two first bonding bodies 300. In some embodiments, before bonding the two first bonding bodies 300, a first bonding surface is first formed on the thinned surface of the first substrate 10 in the first bonding body 300. The specific process of forming the first bonding surface is the same as Fig.15 And the corresponding description will not be repeated here.

[0093] Continue to see Fig.21 After the bonding of the two first bonding bodies 300 is completed, that is, the central regions of the first bonding bodies 300 are bonded to each other and the third edge regions of the first bonding bodies 300 are bonded to each other, the second bonding layer 61 is filled in the gap between the two first bonding bodies 300 to form the second bonding body 400. The material and formation method of the second bonding layer 61 are the same as those of the first bonding layer 60, and will not be repeated here.

[0094] In some embodiments, after forming the second bonding body 400, the thickness of the second substrate 11 is further reduced, and a bonding surface is formed on the surface of the second substrate 11 to achieve bonding of multiple second bonding bodies 400. The formation of the bonding surface on the surface of the second substrate 11 can refer to the formation process of the second bonding surface described above, and will not be repeated here. After the multiple second bonding bodies 400 are bonded, the third bonding layer can be continuously filled between the bonding bodies. The formation process and material of the third bonding layer are the same as the first bonding layer and the second bonding layer.

[0095] In some embodiments, multiple second bonding bodies 400 may be further bonded to form a bonding structure with a higher degree of integration.

[0096] In some embodiments, before the plurality of second bonding bodies 400 are further bonded, the second bonding body 400 is thinned. When the second bonding body 400 is thinned, only one side of the second substrate 11 may be thinned, or both sides of the second bonding body 400 may be thinned. Fig. 22 As shown, Fig. 22Schematic diagram of the structure obtained after thinning both sides of the second bonding body 400. A fourth dielectric layer 43, a fourth filling layer 53 and a fifth bonding pad 703 are formed on the surface of the thinned second substrate 11. The fourth dielectric layer 43, the fourth filling layer 53 and the fifth bonding pad 703 are used for subsequent bonding between multiple second bonding bodies 400.

[0097] In some embodiments, after forming the second bonding body 400 , the second bonding body 400 is further singulated using a cutting tool, such as a cutting blade or a laser, to perform singulation processing.

[0098] In the above embodiment, in the process of forming the first bonding body 300 and forming the second bonding body 400, on the basis of utilizing the filling layers to improve the bonding effect between the substrates, each bonding layer is further formed in the gap of the bonding body to cover and fix the uneven parts of the edges of each substrate, thereby omitting the edge trimming of each bonding body, because the unbonded or loosely bonded parts of the edges of each substrate have been fixed by the bonding layers, and the problem of edge material peeling will not occur in subsequent thinning and other process steps, thereby eliminating the edge trimming step and reducing production costs.

[0099] In some embodiments, in combination Fig. 20 and Fig.23 , Fig.23 for Fig. 20A cross-sectional top view along the A1-A2 direction in FIG. The first substrate 10 includes a first dielectric layer 40 disposed on a central region 101 and a first filling layer 50 disposed on an edge region 102. A first bonding layer 60 is further disposed on the periphery of the first filling layer 50. A plurality of first bonding pads 70 are disposed in the first dielectric layer 40. The first bonding pads 70 may be uniformly distributed or unevenly distributed in the first dielectric layer 40. The shape of the first bonding pads 70 may be circular or rectangular or other shapes. The outermost edge of the first dielectric layer 40 in the central region 101 has a radial distance of R1 to the center of the first substrate 10. The maximum radial distance from the outermost edge of the first filling layer 50 to the center of the central region 101 of the first substrate 10 is R2. The maximum radial distance from the outermost edge of the first bonding layer 60 to the center of the central region 101 of the first substrate 10 is R3, wherein the difference between R3 and R2 is less than the difference between R2 and R1. Taking the first substrate 10 as a 12-inch wafer as an example, the difference between R2 and R1 ranges from 1.5mm to 2.5mm, and the difference between R3 and R2 ranges from 0.1mm to 0.5mm, that is, the value of R1 ranges from 147mm to 147.5mm, the value of R2 ranges from 148.5mm to 149.5mm, and the value of R3 is greater than or equal to 150mm. It can be seen that in the embodiment of the present disclosure, by forming the first filling layer 50, a flat area with a width of 1.5mm to 2.5mm can be formed on the edge area 102, thereby improving the bonding stability of the edge area of ​​the first substrate 10. The 0.5mm non-flat area at the outermost edge can be filled with the first bonding layer to achieve the leveling and sealing of the edge of the first substrate 10, eliminating the process of edge trimming of the first substrate 10 and improving the bonding yield.

[0100] The embodiments of the present disclosure also provide a semiconductor structure. Figure 7 As shown, the semiconductor structure includes: a first substrate 10, the first substrate 10 having a central region 101 and an edge region 102 arranged around the central region 101. In some embodiments, the first substrate 10 may be a wafer or a portion of a wafer, the central region 101 may be a region in which a semiconductor device 20 is arranged in the wafer or a portion of the wafer, and the edge region 102 may be an edge region of the wafer or a portion of the wafer, in which the semiconductor device 20 may not be arranged.

[0101] The first dielectric layer 40 covers the central region 101 and the edge region 102, wherein the thickness of the first dielectric layer 40 covering the edge region 102 gradually decreases in a direction away from the central region 101. In other words, the thickness of the first dielectric layer 40 on the edge region 102 is non-uniform, and the thickness of the first dielectric layer 40 in the edge region 102 that is farther away from the central region 101 is smaller.

[0102] The first filling layer 50 is formed above the first dielectric layer 40 in the edge region 102, that is, the first filling layer 50 covers the first dielectric layer 40 in the edge region 102. The surface of the first filling layer 50 is flush with the surface of the first dielectric layer 40 in the central region 101. The flushing here can mean that the surfaces of the two are substantially flush or the height difference of the surfaces of the two is within a predetermined range.

[0103] In some embodiments, another semiconductor structure is provided, such as Fig.13 As shown, the semiconductor structure further includes a second substrate 11, and the second substrate 11 has a central region 111 and an edge region 112 surrounding the central region 111. The second substrate 11 has the same or similar structural features as the first substrate 10, the central region 111 may be a region in a wafer or a portion of a wafer where a semiconductor device 21 is disposed, and the edge region 112 may be an edge region of a wafer or a portion of a wafer where no semiconductor device 21 may be disposed. The semiconductor device 21 and the semiconductor device 20 may be semiconductor devices of the same type or semiconductor devices of different types.

[0104] The second dielectric layer 41 covers the central region 111 and the edge region 112, wherein the thickness of the second dielectric layer 41 covering the edge region 112 gradually decreases in a direction away from the central region 111. In other words, the thickness of the second dielectric layer 41 on the edge region 112 is non-uniform, and the thickness of the second dielectric layer 41 in the edge region 112 that is farther away from the central region 111 is smaller.

[0105] The second filling layer 51 is formed above the second dielectric layer 41 in the edge region 112, that is, the second filling layer 51 covers the second dielectric layer 41 in the edge region 112. The surface of the second filling layer 51 is flush with the surface of the second dielectric layer 41 in the central region 111. The flushing here can mean that the surfaces of the two are substantially flush or the height difference of the surfaces of the two is within a predetermined range.

[0106] The first dielectric layer 40 in the central region 101 of the first substrate 10 and the second dielectric layer 41 in the central region of the second substrate 11 are aligned and bonded, and the first filling layer 50 and the second filling layer 51 are aligned and bonded to form a semiconductor structure.

[0107] In some embodiments, the semiconductor structure further includes a first bonding pad. Figure 7As shown, an interconnection layer 30 is also provided in the central region 101 of the first substrate 10, the interconnection layer 30 is connected to the semiconductor device 20, and a first bonding pad 70 is formed in the first dielectric layer 40, and the first bonding pad 70 passes through the first dielectric layer 40 and is connected to the interconnection layer 30. In some embodiments, the first bonding pad 70 may not be connected to the interconnection layer 30. The first bonding pad 70 is used for the signal lead-out structure of the interconnection layer 30 in the first dielectric layer 40 in the central region and the subsequent structure for bonding interconnection.

[0108] In some embodiments, the semiconductor structure further includes a second bonding pad, such as Figures 13 to 18 As shown, the second bonding pad 71 is aligned and bonded with the first bonding pad 70. The second bonding pad 71 is connected to the interconnection layer 31 provided in the central area 111 of the second substrate 11, and the interconnection layer 31 is connected to the semiconductor device 21. The second bonding pad 71 is provided in the second dielectric layer 41, and is connected to the interconnection layer 31 through the second dielectric layer 41. The first bonding pad 70 and the second bonding pad 71 bonded in the semiconductor structure realize the electrical connection between the semiconductor device 20 and the semiconductor device 21.

[0109] Continue to see Figure 7 and Figures 13 to 18 In some embodiments, the semiconductor structure further includes a through-hole interconnect structure 80 disposed in the first substrate 10 and a through-hole interconnect structure 81 disposed in the second substrate 11. The through-hole interconnect structure 80 is disposed in the central region 101 of the first substrate 10, penetrates or partially penetrates the first substrate 10, and is connected to the interconnect layer 30, and finally connected to the first bonding pad 70. The through-hole interconnect structure 81 is disposed in the central region 111 of the second substrate 11, penetrates or partially penetrates the second substrate 11, and is connected to the interconnect layer 31, and finally connected to the second bonding pad 71.

[0110] In some embodiments, the semiconductor structure further includes a first bonding layer, such as Figure 20 to Figure 23 As shown. The first bonding layer 60 is disposed between the bonded first substrate 10 and the second substrate 11, and the first bonding layer 60 at least covers the unbonded surfaces of the first filling layer 50 and the second filling layer 51. In some embodiments, the first bonding layer 60 covers the outer edge portions of the first filling layer 50 and the second filling layer 51. The first bonding layer 60 also covers the outer edge portions of the first dielectric layer 40 and the second dielectric layer 41. In some embodiments, the material of the first bonding layer 60 can be a filling material with fluidity, such as a bottom filling glue.

[0111] In some embodiments, reference Fig. 20 and Fig.23As shown, the maximum radial distance from the center area 101 of the first substrate 10 in the semiconductor structure to the center of the center area 101 is R1, the maximum radial distance from the first filling layer 50 to the center of the center area 101 is R2, and the maximum radial distance from the first bonding layer 60 to the center of the center area 101 is R3, wherein the difference between R2 and R1 is greater than the difference between R3 and R2. In some embodiments, the difference between R2 and R1 ranges from 1.5 mm to 2.5 mm, and the difference between R3 and R2 ranges from 0.1 mm to 0.5 mm.

[0112] In some embodiments, the number of the first substrate and the second substrate in the semiconductor structure provided by the present invention may be multiple, for example, 6, 8, 12 or even more.

[0113] The semiconductor structure provided by the embodiment of the present disclosure has a first filling layer in the edge region that is flush with the surface of the central region, which can further increase the surface area of ​​the flat region of the edge region and improve the bonding yield during subsequent surface bonding.

[0114] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first substrate, the first substrate having a central region and an edge region; forming a first dielectric layer covering the central region and the edge region, wherein a thickness of the first dielectric layer covering the edge region gradually decreases in a direction away from the central region; forming a first filling layer of the first dielectric layer covering the edge area; planarizing the first filling layer to form a first edge region on the surface of the first filling layer that is flush with the surface of the first dielectric layer in the central region; After forming the first edge region, patterning the first dielectric layer to form a first bonding material layer in the first dielectric layer; The first bonding material layer is planarized to form first bonding pads isolated from each other and exposed to the surface of the first dielectric layer in the central region of the first dielectric layer, wherein the surface of the first bonding pad is flush with the surface of the first dielectric layer.

2. The manufacturing method according to claim 1, characterized in that: Also includes: providing a second substrate, the second substrate having a central region and an edge region; forming a second dielectric layer covering the central region and the edge region on the second substrate, wherein the thickness of the second dielectric layer covering the edge region gradually decreases in a direction away from the central region; forming a second filling layer covering the second dielectric layer on the edge region; planarizing the second filling layer, forming a second edge region on the surface of the second filling layer that is flush with the surface of the second dielectric layer in the central region, wherein the central region is provided with a second bonding pad; The second substrate is aligned and bonded to the first substrate, so that the first bonding pad in the central area of ​​the first substrate is bonded to the second bonding pad in the central area of ​​the second substrate, and the first edge area is bonded to the second edge area.

3. The manufacturing method according to claim 2, characterized in that: Also includes: Performing a first edge trimming on the bonded first substrate and the second substrate, removing a portion of the edge region of the first substrate and a portion of the edge region of the second substrate, and simultaneously removing a portion of the first edge region and a portion of the second edge region; The first substrate is thinned to form a first bonding body.

4. The manufacturing method according to claim 3, characterized in that: A plurality of the first bonding bodies are bonded to each other to form a second bonding body.

5. The manufacturing method according to claim 4, characterized in that: Before bonding the plurality of first bonding bodies to form the second bonding body, after thinning the first substrate, the method further includes: forming a first bonding surface on the surface of the thinned first substrate, wherein the step of forming the first bonding surface includes: Depositing a third dielectric layer covering the central region and the edge region on the surface of the thinned first substrate, wherein the thickness of the third dielectric layer gradually decreases in a direction away from the central region; Depositing a third filling layer on the third dielectric layer in the edge region, planarizing the third filling layer, and forming a third edge region on the surface of the third filling layer that is flush with the surface of the third dielectric layer in the center region; Bonding the plurality of first bonding bodies to each other to form a second bonding body includes: bonding the central regions of the plurality of first bonding bodies to each other, and bonding the third edge regions of the plurality of first bonding bodies to each other.

6. The manufacturing method according to claim 5, characterized in that: Also includes: The second bonding body is subjected to a second edge trimming to remove a portion of the edge region of the second substrate retained after the first edge trimming and a portion of the third edge region in each of the first bonding bodies, wherein a width of the edge region of the second substrate removed in the first edge trimming is the same as a width of the edge region removed in the second edge trimming.

7. The manufacturing method according to claim 5, characterized in that: After the central regions of the plurality of first bonding bodies are bonded to each other and the third edge regions of the plurality of first bonding bodies are bonded to each other, the method further includes: thinning the second substrate to form the second bonding body.

8. The manufacturing method according to claim 7, characterized in that: providing a third substrate, the third substrate having a central region and an edge region; forming a fourth dielectric layer covering the central region and the edge region, wherein a thickness of the fourth dielectric layer covering the edge region gradually decreases in a direction away from the central region; forming a fourth filling layer of the fourth dielectric layer covering the edge region; planarizing the fourth filling layer to form a fourth edge region on the surface of the fourth filling layer that is flush with the surface of the fourth dielectric layer in the central region; forming a second bonding surface on the thinned surface of the second bonding body; The third substrate is aligned and bonded to the second bonding body, so that the central region and the fourth edge region of the third substrate are bonded to the second bonding surface.

9. The manufacturing method according to claim 2, characterized in that: After the second substrate is aligned and bonded to the first substrate, the method further comprises: A first bonding layer is filled between the first substrate and the second substrate, and the first bonding layer at least covers the first dielectric layer, the second dielectric layer, and unbonded surfaces of the first filling layer and the second filling layer.

10. The manufacturing method according to claim 9, characterized in that: After forming the first bonding layer, the first substrate is thinned to form a first bonding body.

11. The manufacturing method according to claim 10, characterized in that: A plurality of the first bonding bodies are bonded to each other to form a second bonding body.

12. The manufacturing method according to claim 11, characterized in that: Before bonding the plurality of first bonding bodies to each other to form a second bonding body, after thinning the first substrate, the method further includes: forming a first bonding surface on the surface of the thinned first substrate, wherein the step of forming the first bonding surface includes: Depositing a third dielectric layer covering the central region and the edge region on the surface of the thinned first substrate, wherein the thickness of the third dielectric layer gradually decreases in a direction away from the central region; Depositing a third filling layer on the third dielectric layer in the edge region, planarizing the third filling layer, and forming a third edge region on the surface of the third filling layer that is flush with the surface of the third dielectric layer in the center region; Bonding the plurality of first bonding bodies to each other to form a second bonding body includes: bonding the central regions of the plurality of first bonding bodies to each other, and bonding the third edge regions of the plurality of first bonding bodies to each other.

13. The manufacturing method according to claim 12, characterized in that: After the central regions of the plurality of first bonding bodies are bonded to each other and the third edge regions of the plurality of first bonding bodies are bonded to each other, a second bonding layer is filled between the first bonding bodies.

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