A secure processor based on tag technology

Abstract

The present invention discloses a security processor based on tag technology, which relates to the field of processor technology. It includes: tag propagation and management: when storing or transmitting data, assign a tag to each data unit, and manage the tag information by using the tag propagation and update mechanism; tag inspection and decision: when the security processor executes the tag information instruction, it checks the tag information of the data and decides whether to enable the security mechanism according to the predefined security policy. The present invention can significantly improve the execution efficiency of the security processor and provide a solid security foundation for various application scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of processors, and more particularly to a secure processor based on tag technology. Background Art

[0002] In the processor field, security tag technology is an innovative hardware security method that aims to improve the overall security of the system. With the development and popularization of information technology, the importance of processors in modern computing devices is increasing. However, this also makes processors a target for attackers, so the security of processors becomes critical. Security tag technology is a solution proposed to meet this challenge.

[0003] Security tag technology implements data and instruction security protection by introducing tags at the processor hardware level. These tags are a type of metadata that can be attached to each data unit or instruction to identify its security attributes or permission information. For example, a data unit can be marked as "sensitive" or "non-sensitive", and the processor will decide whether to allow access or perform corresponding operations based on these tags when executing instructions.

[0004] As security demands continue to grow, security tag technology will play an increasingly important role in the processor field. Future development directions may include more intelligent tag management strategies, deep integration with software security mechanisms, and application exploration in emerging computing platforms (such as quantum computing). In short, as a hardware-level security guarantee, security tag technology can significantly improve the security of processors and the performance of secure processors, providing a solid security foundation for various application scenarios.

[0005] Side channel attacks are a method of inferring encryption keys or sensitive data by analyzing physical parameters such as power consumption, electromagnetic radiation, etc. In order to defend against such attacks, security processors use a variety of technical measures. For example, Synopsys's ARCSEM security processor uses SecureShield technology to design multiple isolated execution environments in the system to ensure the isolation and reliability of the code. This technology combines hardware and software functions to allow designers to create more secure system-level chips for the Internet of Things and mobile applications. By executing cryptographic functions in a secure software environment rather than in dedicated hardware, the silicon area is reduced, the memory protection unit is enhanced, and the development of the SecureShield runtime library trusted execution environment is simplified. In addition, the anti-interference stability suppressor in the SEM system can detect system failures and resist failure attacks.

[0006] To combat side-channel attacks, the ARC SEM processor uses a number of security technologies, such as uniform instruction timing obfuscation and energy consumption randomization, which prevents hackers from leaking details of encryption devices through information such as time consumption, power consumption, or electromagnetic radiation. While these measures improve processor security, they also have a certain impact on its execution efficiency. However, through optimization and design considerations, this impact is minimized, allowing the processor to maintain high execution efficiency while defending against side-channel attacks.

[0007] In general, although the design of a secure processor requires a trade-off between security and execution efficiency, the use of specific technical measures, such as SecureShield technology and energy randomization, can address the problem of reduced execution efficiency to a certain extent, ensuring that the processor can still provide acceptable performance while defending against side-channel attacks.

[0008] Therefore, it is an urgent problem for those skilled in the art to propose a security processor based on tag technology to solve the difficulties existing in the prior art. Summary of the invention

[0009] In view of this, the present invention provides a security processor based on tag technology, which is used to solve the technical problem existing in the prior art, namely, the performance problem of the tagless security processor.

[0010] In order to achieve the above object, the present invention provides the following technical solutions:

[0011] A tag technology-based security processor, comprising:

[0012] Label propagation and management: When storing or transmitting data, a label is assigned to each data unit, and the label information is managed using the label propagation and update mechanism;

[0013] Tag check and decision: When executing instructions with tag information, the security processor checks the tag information of the data and decides whether to enable the security mechanism based on the predefined security policy.

[0014] Optionally, the security processor is an extension of the TIMBER-V architecture, which extends the labels of the memory in the original TIMBER-V architecture to the kernel, and builds a fine-grained trusted execution environment by adding labels to storage units and components in the kernel.

[0015] Optionally, the TIMBER-V architecture adds a 2-bit tag to each 32-bit storage unit, and uses this 2-bit tag to perform horizontal security domain division based on the original vertical privilege level hierarchy of RISC-V, realizing a security domain with a minimum granularity of 32-bit.

[0016] Optionally, each 32-bit memory word in the TIMBER-V architecture carries a 2-bit tag to indicate four security domains.

[0017] Optionally, the four security domains are: general domain N-Tag, trusted user domain TU-Tag, trusted supervisor domain TS-Tag and trusted callable domain TC-Tag.

[0018] Optionally, the secure processor includes: a processor core with a security tag and a main memory with a security tag.

[0019] Optionally, in the processor core, 2-bit hardware tags are added to the instruction-visible general registers and the instruction-invisible program counter PC, respectively, to indicate the security domain where the corresponding storage word and instruction are located.

[0020] Optionally, in the main memory, a 2-bit hardware tag is added to each 32-bit storage unit to indicate the security domain where the corresponding storage word is located.

[0021] Optionally, in the main memory, a 2-bit hardware tag is added to each 32-bit storage unit to indicate the specific content of the security domain where the corresponding storage word is located:

[0022] The value 2'b00, which is 0 in decimal, indicates the general domain N-Tag;

[0023] The value 2'b01, which is 1 in decimal, indicates a trusted callable domain TC-Tag;

[0024] The value 2'b10, which is 2 in decimal, indicates a trusted user domain TU-Tag;

[0025] The value 2'b11, which is 3 in decimal, indicates the trusted supervisor domain TS-Tag.

[0026] It can be seen from the above technical solutions that, compared with the prior art, the present invention discloses a security processor based on tag technology, which has the following beneficial effects:

[0027] 1. It can ensure the security of program execution in the trusted security domain, that is, it can resist specific side-channel attacks when performing "highly sensitive" operations.

[0028] 2. When executing general domain programs (i.e., executing "low-sensitivity" operations), the execution efficiency is improved by about 80% compared to traditional security processors.

[0029] 3. As a hardware-level security protection measure, security tag technology can significantly improve the execution efficiency of security processors and provide a solid security foundation for various application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0031] Figure 1 A flowchart of a security processor based on tag technology provided by the present invention;

[0032] Figure 2 The TIMBER-V architecture diagram provided by the present invention;

[0033] Figure 3 A logical structure diagram of the security processor provided by the present invention;

[0034] Figure 4 A diagram of the processor core structure for security tag expansion provided by the present invention. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] See also Figure 1 As shown, the present invention discloses a security processor based on tag technology, comprising:

[0037] Label propagation and management: When storing or transmitting data, a label is assigned to each data unit, and the label information is managed using the label propagation and update mechanism;

[0038] Tag check and decision: When executing instructions with tag information, the security processor checks the tag information of the data and decides whether to enable the security mechanism based on the predefined security policy.

[0039] Specifically, these tags can represent data attributes such as permission level and confidentiality. Managing these tags requires an efficient tag propagation and update mechanism to ensure that tag information remains consistent and valid throughout the data life cycle.

[0040] If an instruction attempts to access data marked as "sensitive" and the current processing mode or permissions are insufficient to access that data, the security processor blocks the operation and issues a security warning.

[0041] In order to achieve efficient tag management and checking, modern processors need to support it at the hardware level. This usually includes adding dedicated tag registers to the processor architecture, modifying the memory management unit (MMU) to support the storage and transfer of tag information, and optimizing the instruction set to efficiently handle tag operations.

[0042] For further information, see Figure 2 As shown, the security processor is an extension of the TIMBER-V architecture. It extends the memory labels in the original TIMBER-V architecture to the kernel, and builds a fine-grained trusted execution environment by adding labels to storage units and components in the kernel.

[0043] Furthermore, the TIMBER-V architecture adds a 2-bit tag to each 32-bit storage unit, and uses this 2-bit tag to perform horizontal security domain division based on the original vertical privilege level hierarchy of RISC-V, realizing a security domain with a minimum granularity of 32-bit.

[0044] Specifically, this fine-grained trusted execution environment or fine-grained security domain helps solve the common memory fragmentation problem in embedded systems, can optimize data layout to effectively improve the actual utilization of storage resources, and also helps to realize trusted program segments and untrusted program segments sharing the same process (and also sharing the process's stack), and can optimize program layout to further improve the actual utilization of storage resources.

[0045] Furthermore, each 32-bit storage word in the TIMBER-V architecture carries a 2-bit tag to indicate four security domains.

[0046] Furthermore, the four security domains are: general domain N-Tag, trusted user domain TU-Tag, trusted supervisor domain TS-Tag and trusted callable domain TC-Tag.

[0047] Specifically, these security domains indicate the security level to which the corresponding word (data or instruction) belongs. In short, the general domain N-Tag has the lowest security level, the trusted user domain TU-Tag has a medium security level, and the trusted supervisor domain TS-Tag has the highest security level. From an execution perspective, the trusted callable domain TU-Tag, which is the entry point of the trusted user domain TU-Tag or the trusted supervisor domain TS-Tag, has the same security level as the trusted user domain TU-Tag (when the trusted callable domain TC-Tag is the entry point of the trusted user domain TU-Tag) or the trusted supervisor domain TS-Tag (when the trusted callable domain TC-Tag is the entry point of the trusted supervisor domain TS-Tag). Due to the particularity of the trusted callable domain TC-Tag as the entry point from the general domain N-Tag to the trusted domain (Trusted Domain, T-Domain), the trusted callable domain TC-Tag is included in the trusted callable domain TU-Tag and the trusted supervisor domain TS-Tag for discussion (unless the trusted callable domain TC-Tag is specifically pointed out). Therefore, the general domain N-Tag, that is, the untrusted domain, includes U-mode and S-mode of N-Tag, and the trusted domain includes the trusted user domain TU-Tag and the trusted supervisor domain TS-Tag.

[0048] For further information, see Figure 3 As shown, the secure processor includes: a processor core with a security tag and a main memory with a security tag.

[0049] Specifically, between the processor core and the main memory, no matter when and where the data flows, the corresponding security tag always follows it physically, which is like the data has a security domain attribute in terms of time and space scales.

[0050] Furthermore, in the processor core, 2-bit hardware tags are added to the instruction-visible general registers and the instruction-invisible program counter PC, respectively, to indicate the security domain where the corresponding storage word and instruction are located.

[0051] Specifically, in the processor core, tags are mainly used to enable and disable security mechanisms. When the values ​​in the register file (RF) and PC register are sent to the general logic for calculation and control, the security tags corresponding to these values ​​are sent to the tag logic for propagation and inspection, thereby triggering certain security mechanisms. In fact, the general logic is usually composed of calculation logic and control logic, which are functional abstractions of the general processor core and are responsible for the maintenance and update of the RF state and the PC state of the processor respectively. Specifically, the calculation logic is responsible for the instruction calculation work of the processor core, such as calculating the ADD operation; while the control logic is responsible for the instruction control work of the processor core, such as obtaining the next PC value. Similarly, the tag logic is composed of tag propagation logic and tag checking logic, which are abstractions of security extensions. In short, the tag propagation logic is responsible for using the tag input to calculate the tag output, while the tag checking logic is responsible for using the tag input to check security.

[0052] Furthermore, in the main memory, a 2-bit hardware tag is added to each 32-bit storage unit to indicate the security domain where the corresponding storage word is located.

[0053] Specifically, the method definition of tag isolation memory proposed by TIMBER-V will be used to implement storage access isolation, that is, the isolation between different security domains is completed through the collaborative work of tags and tag management logic, and the isolation between different processes in the same security domain is completed through storage management logic. Specifically, as for the hardware functions of the main memory-related structure, the storage management logic and the tag management logic respectively maintain the data and the corresponding security tags in the main memory, including sending the data and the corresponding security tags to their respective storage locations, and taking out the data and the corresponding security tags from their respective storage locations. In essence, the tag management logic is a functional abstraction of TIMBER-V tag management, which can actively communicate with the storage management logic to achieve security isolation in the main memory. In addition, the trusted software (such as TagRoot in the trusted supervisor domain TS-tag, etc.) and firmware (such as M-mode interrupt exception delegation code, etc.) provided by TIMBER-V can work with tags and tag management logic to achieve a typical storage security protection-enclave.

[0054] Furthermore, in the main memory, a 2-bit hardware tag is added to each 32-bit storage unit to indicate the specific content of the security domain where the corresponding storage word is located:

[0055] The value 2'b00, which is 0 in decimal, indicates the general domain N-Tag;

[0056] The value 2'b01, which is 1 in decimal, indicates a trusted callable domain TC-Tag;

[0057] The value 2'b10, which is 2 in decimal, indicates a trusted user domain TU-Tag;

[0058] The value 2'b11, which is 3 in decimal, indicates the trusted supervisor domain TS-Tag.

[0059] Specifically, for electromagnetic-based side channel attack surfaces, a defense mechanism of inserting random pseudo-instructions is adopted. A random number of pseudo-instructions are inserted during the CPU execution process. These pseudo-instructions do not perform any specific operations, but occupy the actual CPU execution cycle. The number of inserted pseudo-instructions is a parameter that cannot be known to the attacker and is often generated by the internal hardware module. The more pseudo-instructions are inserted, the more difficult it is for the attacker to analyze and obtain the specific operations and data executed, but it also increases the CPU operation cycle and reduces the execution efficiency of the program. The key is that the above defense mechanism is not always enabled, but depends on the tag value attached to the executed instruction. Specifically, for non-sensitive program instructions in the general domain N-Tag (2'b00) and the trusted callable domain TC-Tag (2'b01), the defense mechanism is turned off to save CPU overhead; for sensitive program instructions in the trusted user domain TU-Tag (2'b10) and the trusted supervisor domain TS-Tag (2'b11), the defense mechanism is enabled to ensure its security.

[0060] Added Figure 4 The instruction confusion unit shown. The instruction confusion unit is located between the prefetch buffer and the instruction fetch module. Its function is to regenerate the instruction queue according to the instruction tag value obtained from the prefetch module. Specifically, when the obtained tag value is 2'b00 or 2'b01 (the instruction is a sensitive operation), the original instruction sequence will be maintained; when the obtained tag value is 2'b10 or 2'b11 (the instruction is a non-sensitive operation), 0-3 random NOP instructions will be inserted after the instruction sequence, and the generated new instruction queue will be sent to the instruction fetch module in sequence. The NOP instruction generated by the module is essentially different from the NOP instruction that may exist in the program segment. It does not belong to any code segment of the original program. When the processor executes these instructions, the value of the program counter PC will remain unchanged.

[0061] In one embodiment, in order to meet the needs of compilers or programmers to legally modify security labels during program execution, a custom instruction SDT is designed to actively update the security label value in the code. Table 1 lists the detailed information of the SDT instruction.

[0062] Table 1 Custom instruction SDT

[0063]

[0064] As shown in Table 1, although SDT can improve the security level of data, it is limited by the security tag checking rule, which makes the security level to be set no higher than the security level of the instruction itself.

[0065] Let's take a scenario where the security tag needs to be modified: when the U-mode program is running, the N-Tag data is assigned to the TU-Tag function through legal parameter transmission. If the TU-Tag function believes that this legal and open parameter transmission interface will not cause information leakage, the N-Tag data can be modified to TU-Tag data for calculation; if the TU-Tag program believes that the TU-Tag data returned to the N-Tag program will not cause information leakage, the TU-Tag data can be modified to N-Tag data for return. This provides free space for programming to a certain extent.

[0066] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0067] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A secure processor based on tag technology, characterized in that: include: Label propagation and management: When storing or transmitting data, a label is assigned to each data unit, and the label information is managed using the label propagation and update mechanism; Tag check and decision: When executing instructions with tag information, the security processor checks the tag information of the data and decides whether to enable the security mechanism based on the predefined security policy; The secure processor includes: a processor core with a security tag and a main memory with a security tag; In the processor core, tags are used to enable and disable the security mechanism. When the values ​​in the register file and PC register are sent to the general logic for calculation and control, the security tags corresponding to these values ​​are sent to the tag logic for propagation and inspection, thereby triggering the security mechanism. For electromagnetic-based side channel attack surfaces, a defense mechanism called inserting random pseudo-instructions is used. The above defense mechanism is not always enabled, but depends on the tag value attached to the executed instruction. Specifically, for non-sensitive program instructions in the general domain N-Tag2'b00 and the trusted callable domain TC-Tag2'b01, the defense mechanism is disabled to save CPU overhead; for sensitive program instructions in the trusted user domain TU-Tag2'b10 and the trusted supervisor domain TS-Tag2'b11, the defense mechanism is enabled to ensure their security. An instruction confusion unit is added. The instruction confusion unit is located between the prefetch module and the instruction fetch module. Its function is to regenerate the instruction queue according to the instruction label value obtained from the prefetch module. Specifically, when the obtained label value is 2'b00 or 2'b01, the instruction is a sensitive operation and the original instruction queue will be maintained. When the obtained label value is 2'b10 or 2'b11, the instruction is a non-sensitive operation, and 0-3 random NOP instructions are inserted after the original instruction queue. The generated new instruction queue will be sent to the instruction fetch module in sequence. The NOP instruction generated by the module is different from the NOP instruction existing in the program segment. It does not belong to any code segment in the original program. When the processor executes these instructions, the value of the program counter PC will remain unchanged.

2. A tag technology-based security processor according to claim 1, characterized in that: The security processor is an extension of the TIMBER-V architecture. It extends the memory labels in the original TIMBER-V architecture to the kernel, and builds a fine-grained trusted execution environment by adding labels to storage units and components in the kernel.

3. A tag technology-based security processor according to claim 2, characterized in that: The TIMBER-V architecture adds a 2-bit tag to each 32-bit storage unit, and uses this 2-bit tag to perform horizontal security domain division based on the original vertical privilege level hierarchy of RISC-V, realizing a security domain with a minimum granularity of 32-bit.

4. A secure processor based on tag technology according to claim 2, characterized in that: Each 32-bit memory word in the TIMBER-V architecture has a 2-bit tag to indicate four security domains.

5. A tag technology-based security processor according to claim 4, characterized in that: The four security domains are: general domain N-Tag, trusted user domain TU-Tag, trusted supervisor domain TS-Tag and trusted callable domain TC-Tag.

6. The secure processor based on tag technology according to claim 1, characterized in that: In the processor core, the general registers visible to instructions and the program counter PC invisible to instructions are each added with a 2-bit hardware tag to indicate the security domain where the corresponding storage word and instruction are located.

7. The secure processor based on tag technology according to claim 1, characterized in that: In the main memory, a 2-bit hardware tag is added to each 32-bit storage unit to indicate the security domain where the corresponding storage word is located.

8. The secure processor based on tag technology according to claim 7, characterized in that: In the main memory, a 2-bit hardware tag is added to each 32-bit storage unit, indicating the specific content of the security domain where the corresponding storage word is located: The value 2'b00, which is 0 in decimal, indicates the general domain N-Tag; The value 2'b01, which is 1 in decimal, indicates a trusted callable domain TC-Tag; The value 2'b10, which is 2 in decimal, indicates a trusted user domain TU-Tag; The value 2'b11, which is 3 in decimal, indicates the trusted supervisor domain TS-Tag.

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