Electronic fuse control method, chip, device and equipment

Abstract

The present invention relates to the field of chip technology and discloses an electronic fuse control method, chip, device, and apparatus, which are applied to a controller. The method comprises: the controller receives a control instruction, wherein the control instruction includes at least one sending target; when the control instruction is a burn instruction, the controller parses the control instruction to determine a first target register array; and, based on the address of a pre-stored register array, burns the data to be written in the first target register array into the electronic fuse. The controller of this method can receive instructions sent by multiple sending targets, thereby further improving the control efficiency of the electronic fuse by enhancing the controller's reusability.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to an electronic fuse control method, chip, device and equipment. Background Art

[0002] An electronic fuse (eFuse) is a programmable electronic fuse and a non-volatile memory device used to store information and protect chips. As chip performance requirements for yield and safety increase, redundant repair information, chip identity information, and security authentication information in memory need to be stored in eFuse in a solid-state format. In existing technologies, accessing and programming eFuse is limited by specific interfaces and tools, resulting in inefficient access and insufficient flexibility, and inefficient eFuse control. Summary of the Invention

[0003] In view of this, the present invention provides an electronic fuse control method, chip, device and equipment to solve the problem of low control efficiency of electronic fuses.

[0004] In a first aspect, the present invention provides an electronic fuse control method, which is applied to a controller. The method comprises:

[0005] receiving a control instruction, wherein the control instruction is sent to at least one object;

[0006] When the control instruction is a programming instruction, parsing the control instruction to determine a first target register array in the control instruction;

[0007] Based on the address of the pre-stored register array, the data to be written in the first target register array is written into the electronic fuse.

[0008] In a second aspect, the present invention provides a chip, comprising:

[0009] A controller, configured to execute the method of the first aspect or any corresponding embodiment thereof;

[0010] at least one sending object, the sending object being connected to the controller;

[0011] an electronic fuse module, the electronic fuse module being connected to the controller;

[0012] The register array unit is connected to the controller.

[0013] In a third aspect, the present invention provides an electronic fuse control device, comprising:

[0014] An instruction receiving module, configured to receive a control instruction, wherein the control instruction may be sent to at least one object;

[0015] an instruction parsing module, configured to parse the control instruction and determine a first target register array in the control instruction when the control instruction is a programming instruction;

[0016] The data burning module is used to burn the data to be written in the first target register array into the electronic fuse based on the address of the pre-stored register array.

[0017] In a fourth aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0018] In a fifth aspect, the present invention provides a computer program product comprising computer instructions for causing a computer to execute the method of the first aspect or any corresponding embodiment thereof.

[0019] The electronic fuse control method provided in this embodiment is applied to a controller. The controller receives a control instruction. The sending object of the control instruction includes at least one type. When the control instruction is a burn instruction, the control instruction is parsed to determine the first target register array; according to the address of the pre-stored register array, the data to be burned in the first target register array is burned into the electronic fuse. The method provided in this embodiment can obtain instructions sent by multiple sending objects. Accordingly, it can be compatible with data sent by multiple interfaces. Different interfaces can be used in different control scenarios. By improving the reusability of the controller, the control efficiency of the electronic fuse is further improved. Different target storage areas are set in the electronic fuse. During burning, the data to be burned in the target register array is mapped to the target storage area through the address of the pre-stored register array, so that access to one or more storage areas of the electronic fuse is achieved through control instructions, thereby improving the access efficiency of the electronic fuse. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 is a flow chart of an electronic fuse control method according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a chip according to an embodiment of the present invention;

[0023] Figure 3 is a structural block diagram of an electronic fuse control device according to an embodiment of the present invention;

[0024] Figure 4 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0026] An electronic fuse (eFuse) is a programmable fuse technology commonly used in integrated circuit design. It can be used to store information and protect chips. Electronic fuses have a wide range of application scenarios in integrated circuits, including chip protection, power management, circuit calibration, and storage of key information. Memory repair information, chip identification, security identity authentication information, etc. need to be stored in the electronic fuse, where the memory repair information is stored in the electronic fuse during the ATE (Automatic Test Equipment) testing phase, and the identity authentication information may require the user to burn and access the electronic fuse. When storing data in an electronic fuse in different scenarios, it may be necessary to implement it through different types of bus interfaces. When there are multiple scenarios, efficiently storing data from multiple interfaces is a problem that needs to be solved urgently. Based on this, an embodiment of the present invention provides an electronic fuse control method, which is applied to an electronic fuse controller, and the electronic fuse controller is deployed in the chip.

[0027] According to an embodiment of the present invention, an embodiment of an electronic fuse control method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0028] In this embodiment, an electronic fuse control method is provided, which is applied to a controller. Figure 1 FIG. 1 is a flow chart of an electronic fuse control method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0029] Step S101: receiving a control instruction.

[0030] This embodiment is applied to an electronic fuse controller (eFuse controller for short). The controller is located on a chip and can receive control instructions from different sending targets, with the control instructions being sent to at least one target. Different sending targets can use corresponding bus interfaces to send control instructions to the controller. Corresponding to different scenarios, the control instructions can include data programming and data verification for the electronic fuse during the MBIST (Memory Built-In Self-Test) testing phase, as well as data programming and data verification for the electronic fuse during the chip's use phase.

[0031] In some optional implementations, the sending targets of the control instructions include at least a JTAG register and an APB register.

[0032] JTAG (Joint Test Action Group) is an international standard test protocol used for chip testing and debugging. It uses specific interfaces and protocols to access and control internal chip registers. JTAG registers are a core component of JTAG technology.

[0033] In integrated circuit design, especially for large-scale memory arrays (such as SRAM and DRAM), process imperfections can lead to defects that can cause some memory cells to malfunction. To address this, memory repair mechanisms have been introduced. These mechanisms detect defective cells in the memory and replace them with redundant rows or columns, thereby restoring the memory's integrity and functionality. The repair interface sequence depends on the specific tool, and the access sequence can be configured through the JTAG interface. JTAG registers can be accessed through the JTAG interface to the controller, and the controller receives control instructions from the JTAG registers through the JTAG interface.

[0034] In integrated circuit design and application, identity authentication information and similar security keys can be used to ensure device security, authenticate legitimate users or devices, and prevent unauthorized access. Users can store sensitive information by programming and configuring eFuse. In this embodiment, control commands sent from APB registers are received via the Advanced Peripheral Bus (APB) to perform operations such as programming and comparison.

[0035] Step S102 : when the control instruction is a programming instruction, the control instruction is parsed to determine a first target register array in the control instruction.

[0036] The eFuse Local Dispatcher (ELD) consists of a register array. There can be multiple target register arrays, each pre-configured with the data to be programmed. Upon receiving a control instruction, the ELD parses the instruction to determine its specific content. If the control instruction is a programming instruction, the programming instruction includes the register array to which the data to be programmed belongs, i.e., the target register array.

[0037] Step S103 : programming the data to be programmed in the first target register array into the electronic fuse based on the address of the pre-stored register array.

[0038] The controller pre-stores the address corresponding to each target register array in the electronic fuse, that is, the address of the register array, which includes the starting bit address and the position of the highest bit address of the data of the first target register array in the electronic fuse, and may also include the starting bit address and the length of the data to be written in the target register array. Therefore, the storage location of the data to be written in the first target register array in the electronic fuse can be determined based on the address of the pre-stored register array. The controller can be connected to the module where multiple target registers are located. A burn instruction can specify the burning of one or more target register arrays. There are multiple storage areas in the electronic fuse, each storage area corresponds to a different target register array, and can store data from different target register arrays. Based on the address of the pre-stored register array, the data to be written in the first target register array can be burned into the electronic fuse. It should be noted that the electronic fuse in this embodiment can also use other units with similar functions, such as a one-time programmable device (OTP).

[0039] The electronic fuse control method provided in this embodiment is applied to a controller. The controller receives a control instruction. The sending object of the control instruction includes at least one type. When the control instruction is a burn instruction, the control instruction is parsed to determine the first target register array; according to the address of the pre-stored register array, the data to be burned in the first target register array is burned into the electronic fuse. The method provided in this embodiment can obtain instructions sent by multiple sending objects. Accordingly, it can be compatible with data sent by multiple interfaces. Different interfaces can be used in different control scenarios. By improving the reusability of the controller, the control efficiency of the electronic fuse is further improved. Different target storage areas are set in the electronic fuse. During burning, the data to be burned in the target register array is mapped to the target storage area through the address of the pre-stored register array, so that access to one or more storage areas of the electronic fuse is achieved through control instructions, thereby improving the access efficiency of the electronic fuse.

[0040] In some optional embodiments, the method further comprises:

[0041] Step S201, receiving a mode control instruction;

[0042] Step S202: When the mode control instruction corresponds to the test scenario, a designated control instruction sent by a designated sending object is received and the designated control instruction is executed.

[0043] The designated sending target corresponds to the test scenario. The scenario corresponding to the control instruction can be determined by the target to which the control instruction is sent. A test scenario refers to the scenario in which the ATE performs tests such as Mbist. In this scenario, control instructions are transmitted via the JTAG interface, and the corresponding sending target is the JTAG register. In this embodiment, the designated sending target is the JTAG register, and the designated control instruction is the control instruction issued by the JTAG register.

[0044] Specifically, a mode control device (such as a mode control register) is provided in the JTAG register, which can be used to control whether the controller needs to be in test mode. The test mode of the controller is applied to the test scenario. When it is necessary to be in test mode, the JATG register sends a mode control instruction to the controller through the mode control device. The controller receives the mode control instruction issued by JTAG and adjusts to test mode. When the controller is in test mode, the controller only receives the specified control instructions issued by the JATG register and executes the specified control instructions. The specified control instructions may include burn instructions, read instructions, comparison instructions, etc.

[0045] In some optional implementations, step S103 in the above implementation includes the following steps:

[0046] Step S301 : determining a target storage area in an electronic fuse for data to be programmed in a first target register array based on an address of a pre-stored register array.

[0047] The starting bit address and the position of the highest bit address of the data of the first target register array in the electronic fuse are obtained from the address of the pre-stored register array, and the starting bit address and the length of the data to be burned in the target register array can also be included. According to the address of the pre-stored register array, the target storage area in the electronic fuse can be determined, and the target storage area in the electronic fuse corresponds one to one with the first target register array. Exemplarily, when the address of the first target register array includes the starting bit address and the position of the highest bit address of the data of the first target register array in the electronic fuse, the target storage area of ​​the first target register array is determined according to the starting bit address and the highest bit address, and the data to be burned is burned to the target storage area. When the controller receives the burn instruction, it loads the starting bit address of the first target register array in the electronic fuse into the address accumulator register (counting unit).

[0048] Step S302 , sequentially reading the data bits of the data to be programmed in the first target register array, and judging the data bits to obtain a judgment result.

[0049] After determining the first target register array, the controller reads each data bit in the first target register array in sequence, determines the state of the data bit after reading, and obtains a determination result of the state of the data bit.

[0050] Specifically, step S302 includes the following steps:

[0051] Step S3021, sequentially reading the data bits in the target register array;

[0052] Step S3022, determine whether the data bit is the first data bit, and obtain a determination result.

[0053] In this embodiment, the first data bit indicates that the data bit is 1, and the non-first data bit indicates that the data bit is 0.

[0054] Step S303 : Based on the determination result, the data to be programmed is sequentially programmed into the target storage area of ​​the electronic fuse.

[0055] Specifically, step S303 includes the following steps:

[0056] Step S3031: When the data bit is the first data bit, a write access request and an address signal are sent to the read-write conversion module, so that the read-write conversion module writes the data to be written corresponding to the data bit into the electronic fuse based on the write access request and the address signal.

[0057] The read-write conversion module is connected to the electronic fuse and the controller. The read-write conversion module is arranged between the electronic fuse and the controller and is used to convert instructions into access timings that match the electronic fuse.

[0058] The controller reads each bit of data from the first target register array via a serial interface with the first target register array. When a data bit is 1, the controller sends a write access request and address signal to the read-write conversion module. Upon receiving the write access request and address signal, the read-write conversion module sends a control signal to the electronic fuse according to the specific timing requirements of the electronic fuse to program the data. Once programming is complete, a handshake signal is sent to the controller, and a counter in the controller increments by 1. The first target register array then moves to the next bit of data to be programmed, and the next bit of data to be programmed is sent via the serial interface with the controller.

[0059] Step S3032: when the data bit is the second data bit, read the next data bit.

[0060] When the data bit is 0, there is no need to perform data programming, and the next data bit in the first target register array is read.

[0061] Step S3033: When the data bit is the first data bit or the second data bit, counting is performed in the counting unit.

[0062] After each bit of data is read or read and written, the counting unit is incremented by 1, so that the next data bit of the first target register array can be read. The above shifting, judging, and writing process is repeated until the value in the counting unit is the same as the address of the highest-order data bit in the first target register array, indicating that all data bits in the first target register array have been processed and the writing is complete. In some optional embodiments, the method further includes the following steps:

[0063] Step S401 : when the control instruction is a verification instruction, based on the verification instruction, data corresponding to the second target register array is read from the electronic fuse, and expected data is read from the second target register array.

[0064] After data is burned, the controller may receive a verification command. The verification command is executed after the burning command is executed to verify whether all data has been burned successfully.

[0065] Assuming the programmed data corresponds to the second target register array, since the serial data input of the second target register array in the programming instruction is from the corresponding serial data output port, the data in the second target register array remains unchanged after the data programming is complete and still stores the desired programmed data (i.e., the expected data). If verification is required, the controller shifts the expected data out of the second target register array and simultaneously reads the programmed data from the electronic fuse.

[0066] Step S402 : performing an XOR operation on the expected data and the data of the second target register array, and determining a programming result of the data of the second target register array based on the result of the XOR operation.

[0067] An XOR operation is performed on the expected data and the data of the second target register array to determine whether the data of the second target register array is consistent with the expected data. If all are consistent, it indicates that the programming result of the data of the second target register array is successful.

[0068] When performing a specific comparison, each bit of data can be compared. If the compared data bits are different, the result is 1; if they are the same, the result is 0.

[0069] This embodiment provides an electronic fuse control device, comprising: a controller, at least one sending object, an electronic fuse module, and a register array unit, wherein the controller is used to execute the methods of the above-mentioned embodiments and implementation methods, the sending object is connected to the controller, the electronic fuse module is connected to the controller, and the register array unit is connected to the controller.

[0070] For example, Figure 2 The chip under test (C1) is C1, and C1.1 is the controller (eFuse controller). The target devices include the JTAG registers (C1.2) and the APB registers (C1.3). The electronic fuse module includes the EFuse (C1.9) and the read / write converter (C1.8). The register array unit includes modules A, B, and C. Controller C1.1 receives instructions from C1.2 (JTAG registers) or C1.3 (APB registers), decodes them, and coordinates the ELD (register array) and eFuse (electronic fuse) operations. The JTAG registers include a test mode configuration register, which issues mode control commands to the controller, placing it in test mode. In test mode, the controller only receives control commands from the JTAG registers. When not in test mode, it can receive control commands from the APB registers. These commands include programming, reading, comparison verification, and register array clearing.

[0071] The CPU module (C1.4) is the chip's functional control unit. It accesses the controller through APB registers and interface i0. The CPU module can issue control instructions to the controller by accessing the APB registers and also collect information about the electronic fuse's status after executing the control instructions. In the figure, modules A and B, respectively, contain register array units (ELD1 and ELD2), APB registers, and APB interface i7. The CPU module can access the APB registers in modules A or B through interface i0, thereby controlling or sampling the parallel input or output data of the register array units.

[0072] The APB registers in modules A and B establish a bridge for the CPU to access the parallel I / O ports of the ELD. They provide the ELD with programming parallel input data—the desired programming data for the corresponding area in the e-fuse. They also read the ELD's output data via the APB after the eFuse data has been transferred to the ELD, thus providing a data channel for the CPU to program and read eFuse data. The controller stores the e-fuse data in the ELD via the serial interface i5 and displays it on its parallel output port. The APB registers are used to place the data to be programmed on the ELD's parallel input port. Programming instructions are then sent to the eFuse controller via the JTAG registers (C1.2) or the APB registers (C1.3). The eFuse controller interprets the instructions and stores the data in both the eFuse IP and the ELD's internal registers. After executing the programming instruction, a verification command can be sent. The eFuse controller compares the data read from the ELD with the data read from the e-fuse and returns a status message, allowing for quick verification of the programming status.

[0073] The ELD3 unit in module C stores repair information for the static random access memory (SRAM) in the eFuse. Module C includes serial interface i5 and access interface i6, which is defined by the Mbist tool. The BISR (Memory Built-in Self-Repair) controller in module C decompresses the SRAM repair information in the ELD and transfers it to the SRAM port with repair logic.

[0074] In the figure, interface i0 is the general APB interface. Interface i1 is the eFuse controller command interface, which includes commands, a valid flag, an ELD enable bit, and a signal indicating whether the command has been executed. Interface i2 is the test mode enable signal controlled by the JTAG register. Interface i3 is the interface for the eFuse controller to send read and write commands to the eFuse. Interface i4 is the interface signal for the eFuse. Interface i5 is the serial interface for communication between the ELD and the eFuse controller, using the IEEE 1687 protocol. It can shift data from the electronic fuse to the ELD in a shift state, with the data displayed on the parallel output port upon completion. It can also program the ELD's parallel input data into the electronic fuse via the serial interface, achieving solid-state data storage. Interface i6 is the interface between the ELD and the BISR controller, storing SRAM repair information in the ELD and transferring the repair information from the eFuse to the ELD and then to the SRAM port after the repair information is solidified. Interface i7 is the parallel input and output interface between the ELD and the APB register, allowing the CPU to access the ELD's parallel port via the APB bus.

[0075] When testing is required, the ATE (or test terminal) runs the test software, connects to the chip test network through test authentication, and puts the controller into test mode. After receiving the command, the controller performs operations such as programming and verification.

[0076] The method provided by the embodiment of the present invention integrates the test requirements and functional requirements together through a multiplexing controller, can cope with a variety of usage scenarios, support multiple port accesses, and then control the electronic fuse, thereby improving the flexibility of accessing the electronic fuse. The data in the electronic fuse is mapped into multiple ELDs (register array units), the size of each ELD can be independently defined, and by changing the ELD enable signal on the interface, whether the corresponding electronic fuse is accessed is controlled, thereby increasing the flexibility of the instruction. The access logic related to the electronic fuse is packaged to decouple the external interface of the controller from the timing interface of the electronic fuse, thereby improving the reusability between different projects and accelerating the development progress of other interface parts of the project. The ELD that stores repair information can quickly realize the use of various third-party Mbist tools.

[0077] This embodiment also provides an electronic fuse control device for implementing the above-mentioned embodiments and preferred embodiments. Details already described will not be repeated. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0078] This embodiment provides an electronic fuse control device, such as Figure 3 Shown, including:

[0079] The instruction receiving module 501 is used to receive a control instruction, wherein the control instruction may be sent to at least one object;

[0080] An instruction parsing module 502 is configured to parse the control instruction and determine a first target register array in the control instruction when the control instruction is a programming instruction;

[0081] The data writing module 503 is configured to write the data to be written in the first target register array to the electronic fuse based on the address of the pre-stored register array.

[0082] In some optional implementations, the sending targets of the control instructions include at least a JTAG register and an APB register.

[0083] In some optional implementations, the data writing module 503 includes:

[0084] a storage area determining unit, configured to determine a target storage area of ​​the data to be written of the first target register array in the electronic fuse based on the address of the pre-stored register array;

[0085] a data judgment unit, configured to sequentially read the data bits of the data to be programmed in the first target register array, and judge the data bits to obtain a judgment result;

[0086] The programming unit is used to program the data to be programmed into the target storage area of ​​the electronic fuse in sequence based on the judgment result.

[0087] In some optional implementations, the data judgment unit includes:

[0088] a reading subunit, configured to sequentially read the data bits in the target register array;

[0089] The judging subunit is configured to judge whether the data bit is the first data bit and obtain a judgment result.

[0090] In some optional implementations, the programming unit includes:

[0091] a first writing sub-unit, configured to send a writing access request and an address signal to a read-write conversion module when the data bit is a first data bit, so that the read-write conversion module writes the to-be-written data corresponding to the data bit into the electronic fuse based on the writing access request and the address signal, wherein the read-write conversion module is disposed between the electronic fuse and the controller;

[0092] a second reading subunit, configured to read a next data bit when the data bit is the second data bit;

[0093] The counting subunit is used to count in the counting unit when the data bit is the first data bit or the second data bit.

[0094] In some optional embodiments, the device further comprises:

[0095] A mode control instruction receiving module, used for receiving a mode control instruction;

[0096] The designated instruction execution module is used to receive the designated control instruction sent by the designated sending object when the mode control instruction corresponds to the test scenario, and execute the designated control instruction, wherein the designated sending object corresponds to the test scenario.

[0097] In some optional embodiments, the device further comprises:

[0098] a verification reading module, configured to, when the control instruction is a verification instruction, read data corresponding to the second target register array from the electronic fuse based on the verification instruction, and read expected data from the second target register array;

[0099] The comparison module is used to perform an XOR operation on the expected data and the data of the second target register array, and determine a programming result of the data corresponding to the second target register array based on the result of the XOR operation.

[0100] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0101] The electronic fuse control device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0102] An embodiment of the present invention further provides a computer device having the above-mentioned electronic fuse control device.

[0103] See also Figure 4 , Figure 4 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 4 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 4 A processor 10 is taken as an example.

[0104] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0105] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0106] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0107] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0108] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0109] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0110] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0111] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An electronic fuse control method, characterized in that: Applied to a controller, the method includes: receiving a control instruction, wherein the control instruction is sent to at least one object, the control instruction including at least a mode control instruction, a verification instruction, and a programming instruction, and the mode control instruction corresponds to a test scenario; When the control instruction is a programming instruction, parsing the control instruction to determine a first target register array in the control instruction; Based on the address of the pre-stored register array, writing the data to be written in the first target register array to the electronic fuse, comprising: determining a target storage area of ​​the data to be written in the first target register array in the electronic fuse based on the address of the pre-stored register array; sequentially reading the data bits of the data to be programmed in the first target register array, and judging the data bits to obtain a judgment result; Based on the judgment result, the data to be written is sequentially written into the target storage area of ​​the electronic fuse.

2. The method according to claim 1, characterized in that The sending objects of the control instruction include at least a JTAG register and an APB register.

3. The method according to claim 1, characterized in that The sequentially reading the data bits of the data to be programmed in the first target register array and judging the data bits to obtain a judgment result includes: sequentially reading the data bits in the first target register array; It is determined whether the data bit is the first data bit, and a determination result is obtained.

4. The method according to claim 3, characterized in that The method of sequentially programming the data to be programmed into the electronic fuse based on the judgment result includes: When the data bit is the first data bit, sending a write access request and an address signal to a read-write conversion module, so that the read-write conversion module writes the to-be-written data corresponding to the data bit to the electronic fuse based on the write access request and the address signal, wherein the read-write conversion module is arranged between the electronic fuse and the controller; When the data bit is the second data bit, reading the next data bit; When the data bit is the first data bit or the second data bit, counting is performed in the counting unit.

5. The method according to claim 1, wherein The method further comprises: Receive mode control instructions; When the mode control instruction corresponds to a test scenario, a designated control instruction sent by a designated sending object is received, and the designated control instruction is executed, where the designated sending object corresponds to the test scenario.

6. The method according to claim 1, characterized in that The method further comprises: When the control instruction is a verification instruction, based on the verification instruction, reading data corresponding to the second target register array from the electronic fuse, and reading expected data from the second target register array; An exclusive OR operation is performed on the expected data and the data of the second target register array, and a programming result of the data corresponding to the second target register array is determined based on the result of the exclusive OR operation.

7. A chip, characterized in that: The chip includes: A controller for executing the method according to any one of claims 1 to 6; at least one sending object, the sending object being connected to the controller; an electronic fuse module, the electronic fuse module being connected to the controller; The register array unit is connected to the controller.

8. An electronic fuse control device, characterized in that: The device comprises: An instruction receiving module is used to receive a control instruction, wherein the control instruction may be sent to at least one object, and the control instruction may include at least a mode control instruction, a verification instruction, and a programming instruction, wherein the mode control instruction corresponds to a test scenario; an instruction parsing module, configured to parse the control instruction and determine a first target register array in the control instruction when the control instruction is a programming instruction; A data writing module, configured to write the data to be written in the first target register array to the electronic fuse based on the address of the pre-stored register array, comprising: determining a target storage area in the electronic fuse for the data to be written in the first target register array based on the address of the pre-stored register array; sequentially reading the data bits of the data to be programmed in the first target register array, and judging the data bits to obtain a judgment result; Based on the judgment result, the data to be written is sequentially written into the target storage area of ​​the electronic fuse.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the electronic fuse control method according to any one of claims 1 to 6 by executing the computer instructions.

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